JP2002171401A - SIMD type arithmetic unit having a thinning operation instruction - Google Patents

Abstract

(57) [Summary] A thinning process of image data composed of a plurality of pixels can be realized by one instruction, and the calculation time is greatly reduced. A thinning-out instruction determining unit determines whether or not the instruction is a thinning-out operation instruction. As a result, the thinning operation unit 107 calculates m
In addition to inputting n pieces of pixel data represented by bits, data indicating whether the pixel is a thinning target pixel indicated by the source data 2 is input. The pixel data in the source data 1 set as the pixel to be thinned out in the source data 2 is treated as invalid, and the vacant area is filled with adjacent valid pixels to generate data after thinning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing system for performing a data thinning process which is performed at the time of resolution conversion and reduction processing of various information, particularly image information such as a still image and a moving image.
The present invention relates to an IMD type arithmetic device.

[0002]

2. Description of the Related Art First, a SIMD (Single Instruction Multiple) that calculates a plurality of pieces of information collectively and in parallel.
Data) type information processing apparatus will be described.

In a SIMD type information processing apparatus, an operation is performed on each of n m-bit information elements in a register by one operation instruction (m is a natural number, and n is a natural number of 2 or more). The operations include arithmetic operations such as addition, subtraction, and multiplication, bit logical operations such as logical sum and logical product, and shift operations and comparison operations. This SI
The instruction of the MD type information processing device includes a field for specifying the type of operation, a field for specifying two or one source register, and a field for specifying one destination register. However, one source register may also serve as the destination register. There are also fields in the instruction that specify how to divide the elements in the registers, and in some cases the registers are divided into n m-bit elements,
In other cases, it is divided into 2n m / 2-bit elements. Normally, register division has a data length of 8, 16, 32.
It is often divided into bit elements, and the total register length is often 64 bits or 128 bits, but is not limited to these.

In such a SIMD type information processing apparatus,
The operation is performed between corresponding elements between two designated registers as shown in FIG. In this figure, the case where n = 4 is shown, but in other cases, the operation is similarly performed between all the elements. Also, depending on the designation in the instruction (a particular field is reserved), rather than between the corresponding elements between the two registers, as shown in FIG. (Lower element)
And an operation with each element of the other register. In this figure, the case where n = 4 is shown, but in other cases, the operation is similarly performed on all elements of one register. Further, instead of the operation between the two registers, the operation may be performed between the immediate value embedded in the bit pattern of the instruction and each element of the source register as shown in FIG.

[0005] In the information processing apparatus, when all of the above-described operation instructions are realized by hardware to realize the operation function (hard-wired logic system), there is a program for executing the operation inside the apparatus. There is a case where an arithmetic function is realized according to a program (microprogram method). However, this is a difference in the internal structure, and does not have any effect on the program operating on the information processing device.

Now, the image reduction processing will be described.

[0007] When converting the resolution of image information, particularly when performing a reduction process, the simplest method is to perform a thinning process using a fixed pattern. FIG. 7 shows an image reduction process by simple thinning. here,
160 × 160 image composed of 256 × 256 pixels
An example in which the image is reduced to a pixel image is shown. Simply perform a process of thinning out 3 dots for every 8 dots in the horizontal direction,
A reduction process is performed by performing a process of thinning out three lines for every eight lines in the vertical direction.

At this time, when the horizontal thinning is performed by the SIMD type information processing apparatus, it is necessary to perform a process of extracting three data from eight data and extracting five data as shown in FIG. The position for thinning out the data may be any three of the eight data, but it is a position where the data is thinned out as much as possible. FIG. 9 shows an operation in the case where the thinning processing is performed only by general-purpose instructions. This is realized by masking the data to be taken out as shown in this figure, shifting the data to fill the thinned gap, and taking the logical sum of the data.

Further, when performing more accurate reduction processing of image information, linearly interpolated data may be used. In this case, simple thinning-out is not performed, and reduction is performed using data obtained by linearly interpolating five data from eight data as shown in FIG. Similarly, in the vertical direction, a reduction process is performed by performing interpolation in line units. FIG. 11 shows an operation in the case where the interpolation processing in this case is performed using only general-purpose instructions.

As shown in the figure, an interpolation process is performed by preparing two coefficients for linear interpolation, shifting the original data and two multiplication results and shifting one of them for each element. However, in this case as well, it is necessary to perform the thinning process at the end as shown in the figure. In interpolation other than linear interpolation, the above-described thinning processing may be required.

Among the SIMD type information processing apparatuses, FIG.
As shown in FIG. 3, some elements in the register can be rearranged in an arbitrary order. When there is such a rearrangement instruction, the above-described thinning process can be easily implemented.

[0012]

In the case where the above-described image information thinning processing is performed on an SIMD type information processing apparatus, conventionally, calculation is performed by using a bit logical OR for each element or a shift operation for each element. Therefore, there is a problem in that many instructions are required only by these general-purpose instructions, and the calculation time is lengthened. In addition, mounting a reordering instruction capable of rearranging elements in an arbitrary order in the SIMD type information processing device requires a large circuit for the reordering operation, and the SIMD type information processing device itself has a large scale. There was a problem that would be.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a simple structure so that the thinning-out processing of the image data composed of a plurality of pixels can be realized by one instruction, and the calculation time is reduced. An object of the present invention is to provide a SIMD-type operation device that can be significantly shortened.

In order to solve this problem, a SIMD type arithmetic unit having a thinning operation instruction according to the present invention has the following configuration. That is, a SIMD-type arithmetic device that calculates and outputs a plurality of data with one command, a determination unit that determines whether or not the calculation command is related to thinning of an image, and is represented by m bits per pixel. A source register holding n pieces of pixel data, a thinning flag register corresponding to each of the pixel data in the source register, and holding data indicating whether or not each pixel is a thinning target pixel, When it is determined that is, the data of the source register, which is set as a thinning target pixel in the thinning flag register, is invalidated, and adjacent pixel data is filled in a free data area of the pixel data set as invalid. , An arithmetic means for generating continuous effective pixel data, and an output means for outputting the arithmetic means.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 1 is a block diagram showing a SIMD type information processing apparatus according to an embodiment. Particularly characteristic portions of the embodiment are a thinning-out instruction determining unit, a thinning-out operation unit, and an operation data selecting unit.

In this SIMD type information processing apparatus, 1
The instruction supply unit 01 implements a function of reading an instruction from a storage device, and the instruction read out therefrom is used by an instruction decoder unit 102 to extract the type of operation, source register number, and destination register number from the bit string of the instruction. Access source register data and read source data. The operation unit 104 performs an operation on source data based on a control signal indicating the type of operation passed from the instruction decoder unit. According to the type of operation, the operation is divided into an operation requiring two source data and an operation using only one source data. The result of this operation is 10
5 is passed to the memory access unit and the register writing unit. If it is a memory access command, the memory access is performed here. Otherwise, the memory access unit does nothing and the operation result and the memory access result are written in the destination register in the register writing unit. The above is the flow of the calculation in the information processing device.

In the present embodiment, a thinning-out instruction determining unit 106 is provided in the instruction decoder unit, and it is determined whether the read instruction is a specially prepared thinning-out instruction. If it is a thinning command, a signal indicating the thinning command is output in the control signal passed to the arithmetic unit 104.
Further, the arithmetic unit 104 is provided with a thinning arithmetic unit 107 for performing thinning processing from source data. Further, the operation data selection unit 108 is provided with a circuit for selecting, as operation data, the operation result of the thinning operation unit when a signal indicating a thinning instruction is output from the instruction decoder unit. By adding the modules as described above, an information processing apparatus that performs the thinning processing of the present invention is realized.

In the following, in the embodiment, in order to unify the description, the order of the data stored in the register is such that the lower order data of the storage address is stored at the uppermost position of the register, and the result of the thinning process is the upper order of the register. The following description is based on the assumption that the information is stored. However, in the case of the reverse order, that is, when thinning out each element in the register and storing the result of the processing, the data may be stored in the lower part of the register and stored.

In the embodiment, it is assumed that one pixel is represented by 8 bits (256 gradations), and the unit of 8 pixels (=
An example of thinning-out processing in units of (64 bits) will be described.

FIG. 12 shows an example of the operation of a thinning instruction in the embodiment.

As shown in the figure, in the embodiment, when a thinning instruction is received, a register (called a source register) for storing and holding pixel data to be processed and a thinning flag register (simply called a flag register) indicating the thinning target are set. As shown in the figure, the portion of the flag register which is "1" is thinned out, and the result of the operation is stored in a higher order of the destination register.

In the case shown, "FF" is stored in the flag register.
(= 8 bits of “1”), as a result, the thinning-out (shift amount) is performed in units of 8 bits, that is, in units of 1 pixel.

In order to realize the above processing, the thinning-out operation unit 107 in the embodiment may have a structure as shown in FIG. 2, for example. This is an example in which the thinning-out operation unit inside the information processing device is implemented by hard-wired logic. FIG. 2 shows a configuration of 4 bytes (32 bits) for both the source register and the flag register in order to simplify the description.

In the figure, reference numeral 201 denotes a non-zero discriminating unit, which is composed of four OR gates. One byte (8 bits) stored in the flag register is input to each gate, and when at least one of them is "1", its output becomes "1". Reference numeral 202 denotes a thinning data selection unit, which is composed of a number of selectors as shown in the figure. Each selector selects and outputs the input terminal “1” when the output from the non-zero discriminating unit is “1”, and selects the input terminal “0” when the output from the non-zero discriminating unit is “0”. "Is selected and output.

Therefore, the upper part of the flag register is "FF"
If (other than 0, it is not necessary to be FF), the corresponding source register is thinned out, and the lower data shifts to the upper.

Although the figure shows an example in which each pixel is 8 bits, and both the flag and the source register are 32 bits, it is easily supposed that the present invention can be extended to 64 bits by extending this.

In the above example, the non-zero discriminating unit 201 is provided for thinning out in units of 8 bits. However, when thinning out in units of 1 bit is realized, the non-zero discriminating unit 201 becomes unnecessary. The flag register and the source register are 64
The number of bits may be extended, and each selector may select one bit.

As a result, for example, in the case of thinning out an image appearing with 4 bits per pixel, the flag register is set in units of 4 bits, which is "1". Also,
The same applies to an image represented by 6 bits per pixel.
Even if a pixel has 8 bits or more, it can be dealt with by setting the number of bits equal to the number of bits expressing the pixel to “1”. That is, no matter how many bits a pixel appears, the same configuration can cope with it.

<Second Embodiment> FIG. 3 is a flow chart of a thinning-out operation in the second embodiment, and shows a flow chart of a microprogram when a thinning-out operation unit inside an information processing apparatus is implemented by a microprogram. ing.

The instruction read from the storage device is discriminated as a thinning command in step 301 for discriminating a thinning command. If the instruction is not a thinning instruction, it is another instruction, and the process proceeds to the execution step 302 of the other instruction. If it is determined that the instruction is a thinning instruction, the loop variable i is initialized to 0 and the variable j for substitution is initialized to 0.
In step 303, it is determined whether or not the i-th element (in units of 8 bits) of the source data (source register) that determines the elements to be thinned out is zero. If it is zero, the data of the corresponding element (i-th element) of the source data to be decimated in step 304 is extracted, the output data is substituted for the j-th element of the variable to be inserted, and j is incremented. Then, i is incremented, and step 3
At 05, it is determined whether or not processing has been performed on all elements. If not, the process from step 303 is repeated. When processing is completed for all elements,
In step 306, the output data is assigned to the destination register. By incorporating the above microprogram, a thinning command can be implemented in the information processing apparatus.

As described above, m bits (m is a natural number) of information elements (n is a natural number of 2 or more) can be held in an internal register, and n pieces of information in the register can be held by one operation instruction. A SIMD-type information processing device that performs an operation on each of the elements of
A means for thinning out only elements corresponding to non-zero elements of the other source register among elements of one source register, and sequentially packing the remaining elements in the upper direction of the register, and a thinning instruction. If there is a means for storing the above result in the destination register, the thinning process, which requires many instructions and takes time when only conventional general-purpose instructions are used, requires a large-scale circuit. Without preparing the necessary rearrangement instruction, the present invention can be performed by one instruction of the thinning instruction of the present invention,
There is an effect that calculation time for image reduction processing or the like can be reduced.

[0033]

As described above, according to the present invention, the thinning processing of the image data composed of a plurality of pixels can be realized by one instruction, and the calculation time can be greatly reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a SIMD type information processing apparatus according to an embodiment.

FIG. 2 is a detailed block diagram of a thinning calculation unit according to the embodiment.

FIG. 3 is a flowchart of a microprogram according to a second embodiment.

FIG. 4 is a conceptual diagram illustrating an operation between elements of two registers in the SIMD type information processing device.

FIG. 5 is a conceptual diagram showing operations of all elements of a register and the lowest element of another register in the SIMD type information processing apparatus.

FIG. 6 is a conceptual diagram showing the operation of all elements of a register and an immediate value embedded in an instruction in a SIMD type information processing apparatus.

FIG. 7 is a diagram illustrating reduction of an image by thinning.

FIG. 8 is a diagram showing a data thinning method.

FIG. 9 is a diagram illustrating a thinning process using a general-purpose instruction.

FIG. 10 is a diagram illustrating a processing method of linear interpolation.

FIG. 11 is a diagram showing an operation method when linear interpolation is processed by a general-purpose instruction.

FIG. 12 is a diagram illustrating an example of a thinning operation in the embodiment.

FIG. 13 is a diagram illustrating an example of a rearrangement operation.

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Claims (5)

[Claims] 1. A SIMD-type operation device for calculating and outputting a plurality of data with one instruction, a determination means for determining whether or not the operation instruction is related to image thinning, and m bits per pixel A source register holding n pixel data represented by: and corresponding to each of the pixel data in the source register,
A thinning flag register that holds data indicating whether each pixel is a thinning target pixel, and when the determining unit determines that it is a thinning operation instruction,
By invalidating the data of the source register, which is set as the pixel to be decimated in the decimating flag register, and packing the adjacent pixel data into the empty data area of the pixel data set as invalid, continuous valid pixel data And an output means for outputting the calculation means. 2. The SIMD type arithmetic device according to claim 1, wherein said output means outputs to a destination register. 3. The SIMD-type operation device according to claim 1, wherein said operation means further comprises means for filling "0" in a lower free area. 4. The arithmetic means comprises a gate, a selector, and
The SIMD type arithmetic device according to claim 1, wherein the SIMD type arithmetic device is configured by wired logic. 5. The SI according to claim 1, wherein said arithmetic means is constituted by a microprogram.
MD type arithmetic unit.