JP2002171066A - Method for manufacturing multilayer wiring board - Google Patents

Abstract

[PROBLEMS] To provide a method for manufacturing a multilayer wiring board capable of forming a smooth conductor layer filled with a metal conductor in a blind via hole by a direct current electrolysis method without using a special electrolysis method or a plating solution. Is to do. A blind via hole (12, 13) having a closed structure is formed on one side of a resin film (10). After the conductive film 5 is formed on the surface of the resin film 10 including the wall surfaces of the via holes 12 and 13, the metal film 14 is formed by electroplating through the conductive film 5. As an electroplating solution used for electroplating, it is reductively decomposed at the potential for depositing a metal film in the electroplating step, suppressing the deposition of the metal film, and at the same time, the diffusion speed is slow, and the upper side surface of the via hole opening and the lower bottom surface of the via hole closing lower portion. An electroplating solution to which a substance causing a difference in the effect of suppressing the deposition of the metal film, for example, Janus Green (Yasnu Green) is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board such as a thin-film wiring board or a built-up board which requires formation of a high-density wiring pattern, and more particularly to a method for manufacturing a blind via hole having one side closed. The present invention relates to a method for manufacturing a multilayer wiring board suitable for filling a metal conductor film.

[0002]

2. Description of the Related Art In recent years, in order to respond to high performance and miniaturization of electronic devices, a technology for mounting an LSI or the like on a substrate at a high density is required. It is being advanced. In the field of large computers and the like, multi-chip mounting using a multilayer sintered substrate of a ceramic-metal conductor has become mainstream. Further, in order to cope with higher densification, a thin film wiring substrate in which a thin film wiring layer using a photolithographic technique similar to a semiconductor is formed on a ceramic multilayer substrate is used. On the other hand, in the field of consumer products such as personal computers, built-up boards, which are multilayer printed boards using a build-up method, are widely used.

[0003] In these thin film wiring boards and build-up boards, in order to electrically connect the conductor layers that are sequentially laminated,
A contact through hole called a blind via hole having a structure closed on the lower conductor layer side is used. As a method of connecting conductive layers using a blind via hole (hereinafter, referred to as a “via hole”), a via feeling method of filling a hole portion in the via hole with a conductor is to form an upper via hole by overlapping the lower via hole. A via-on-via connection structure can be formed and multilayered, and the degree of design freedom is improved by increasing the wiring pattern area, which is effective for multilayering and increasing the density of wiring. As a method of filling the conductor, a plating method of directly filling a via hole with a metal conductor is effective. However, in the electroplating method, current concentration due to the structure tends to occur in the upper portion of the via hole, and due to the difference in diffusion efficiency, the plating metal ion concentration tends to decrease in the lower portion of the via hole compared to the upper portion of the via hole. In this case, there is a problem that the growth rate of the plating film is high at the upper portion of the via hole opening and slow at the lower portion of the via hole closing portion.

Therefore, for example, Japanese Patent Application Laid-Open No. 7-336017
As described in the publication, those using electrolytic etching or polishing by pulse electrolysis or current reversal electrolysis,
As described in Japanese Patent Application Laid-Open No. 12-068651, it is known to improve via feeling by using a current reversal electrolysis method and a special plating solution composition.

[0005]

However, all of the conventional methods have a problem that a special electrolytic method and a plating solution composition are required. For example, when copper is used as a conductor, a common copper sulfate plating solution called high-throw bath containing copper sulfate, sulfuric acid, and hydrochloric acid is used to form a via hole having a diameter of about 10 to 100 μm such as a thin film wiring board or a build-up board. Within this range, there is a problem that it is difficult to realize sufficient via feeling by a DC electrolysis method.

An object of the present invention is to provide a method of manufacturing a multilayer wiring board capable of forming a smooth conductor layer filled with a metal conductor in a blind via hole by a direct current electrolysis method without using a special electrolysis method or a plating solution. Is to do.

[0007]

In order to achieve the above object, the present invention forms a blind via hole having a closed structure on one side of a resin film insulating layer, and forms a conductive film on the surface of the insulating layer including the wall surface of the via hole. After forming the film, a metal film is formed by electroplating through the conductive film, and a method for manufacturing a multilayer wiring board in which a resin film insulating layer and a conductive layer of the metal film are sequentially and alternately formed on a base material, As the electroplating solution used for the electroplating, the metal film of the electroplating step is reductively decomposed at a potential at which the metal film is deposited, and at the same time, the deposition rate of the metal film is suppressed. In this case, an electroplating solution to which a substance causing a difference in the effect of suppressing the deposition of the metal film is added is used. According to such a method, a smooth conductor layer filled with a metal conductor in a blind via hole can be formed by a direct current electrolysis method without using a special electrolysis method or a plating solution.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer wiring board according to a first embodiment of the present invention will be described below with reference to FIGS. First, the method for fabricating the multilayer wiring board according to the present embodiment will be explained with reference to FIGS. 1 to 7 are process diagrams showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

First, a method for producing a sheet with a copper foil pattern will be described with reference to FIG. The production process of the sheet with the copper foil pattern is a separation process performed independently of the processes of FIGS.

Non-thermoplastic resin film 10 and copper foil 1
The resin film 10 side of the laminated film sheet made of No. 1 is fixed to a titanium (Ti) frame 9 by press-compression through an adhesive film. The titanium (Ti) frame 9 has, for example, an outer dimension of about 180 mm square. Non-thermoplastic resin film 1
The thickness of 0 is, for example, about 15 μm. The thickness of the copper foil 11 is, for example, about 15 μm.

Next, a resist pattern is formed on the surface of the copper foil 11, the copper film is etched using ferric chloride, and then the resist is peeled off to produce a sheet 1 with a copper foil pattern. At this time, it is assumed that an activation process having sufficient adhesiveness to the resin film has already been performed on the copper foil surface.

Since the sheet manufacturing process shown in FIG. 1 is a separation process, by providing only non-defective products to the processes shown in FIG. 2 and thereafter, it is possible to reduce the inspection process time by yield selection and to reduce the cost. Can be planned.

Next, as shown in FIG. 2, the copper foil 11 side of the copper foil-patterned sheet 1 produced in FIG. It is fixed by press bonding. The base substrate 2 is, for example, a glass substrate having an outer dimension of about 150 mm square. The surface of the base substrate 2 is activated. As the base material, a silicon wafer, a printed circuit board, a ceramic substrate, or the like may be used. As the resin film insulating layer 3, for example, a heat-resistant resin sheet having a high fluidity and a thickness of about 30 μm is used. Examples of the heat-resistant resin include a polyimide resin and a polyquinoline resin. In the present embodiment, a polyquinoline resin having a small degassing component at the time of curing is particularly effective, and is formed into a sheet from the viewpoint of handling. A polyquinoline-based resin sheet is used.

At this time, the copper foil 11 serving as the first conductor layer is
Since it is embedded in the resin film insulating layer 3 made of a polyquinoline-based resin, the step of the copper foil pattern is sufficiently flattened, and the polishing step is not required.

After the fixing, the titanium film 9 is removed by cutting the resin film 10 on the inner peripheral side of the titanium frame 9, and unnecessary portions of the sheet 1 with the copper foil pattern are cut off. The resin film 10 of the sheet 1 with a copper foil pattern is used as a second insulating layer in the following steps.

Next, as shown in FIG.
Through the excimer laser, the upper diameter of the opening is about 50
A μm through via hole 12 and a non-through via hole 13 are simultaneously formed. The through via hole 12 is a via hole having a depth of about 45 μm that penetrates the pattern opening diameter of the copper foil 11 about 40 μm and reaches the base substrate 12 under the first insulating layer. During laser processing, the base substrate 12 functions as a stop film. The non-penetrating via hole 13 is a via hole having a depth of about 15 μm, and the copper foil 11 functions as a stop film for laser processing.

Next, as shown in FIG. 4, a plated conductive film 5 is formed on the surface of the resin film 10 in which the via holes are formed. The plating conductive film 5 is made of, for example, chromium (Cr).
The film is about 0.05μm thick and the Cu film is about 0.5μm thick
m, and is formed by sputtering. Next, the surface of the plating conductive film 5, after laminating a film resist, exposure, development, was post-baked to form a resist pattern 6 for plating. The thickness of the resist pattern 6 is, for example, about 20 μm.

Next, as shown in FIG.
Of the filled via hole pad 14A to be the second conductor layer and the wiring 14
B is simultaneously formed.

Here, the configuration of the electric Cu plating apparatus used in the process shown in FIG. 5 will be described with reference to FIG.
FIG. 8 is a cross-sectional view showing a configuration of an electric Cu plating apparatus used in the method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

The substrate 22 to be a cathode is fixed to a substrate jig 23 having a power supply portion, and is inserted vertically into a plating solution 29. At this time, the plating conductive film 5 shown in FIG.
Are fixed to the substrate jig 23 so as to be on the power supply unit side.
A phosphorous copper plate 24 is used for the anode. A shielding plate 25 is inserted in the vicinity of the substrate jig 23 to achieve a uniform plating film thickness. The plating solution 29 is circulated by the pump, and the plating solution flow 27 flows from the liquid discharging portion 26 on the surface of the substrate to be plated 22 from the substrate lower side to the substrate upper direction, and returns to the pump from the overflow portion 28. I have.

Here, the composition of the electric Cu plating solution 29 used in the present embodiment is as follows. -Copper sulfate pentahydrate (manufactured by Wako Pure Chemical) ... 75 g / L-Sulfuric acid (manufactured by Wako Pure Chemical) ... 100 ml / L-Hydrochloric acid (manufactured by Wako Pure Chemical) ... 0.17 ml / L-Sulcup AC90 ( 5 ml / L ・ Janus Green (manufactured by Aldrich) 10
mg / L where Janus Green (Janus Green)
Other compositions are the same as the conventional electric Cu plating solution. Janus Green is
An organic pigment, for example, used as a chromosome dye or the like. Janus Green (Janus Green) suppresses the deposition of the metal film because it undergoes reductive decomposition at the potential at which the plated metal film is deposited, is decomposed and consumed during plating, inhibits isotropic plating growth by adsorption, and has a low diffusion rate. Therefore, it is a substance that produces a remarkable concentration gradient. By adding this substance as a filling component to a normal electroplating solution, the property of preferentially growing a plating film from the bottom surface of the lower portion of the via hole block is developed, and the via feeling is improved. If it has such properties, Ja
A substance other than nus Green (Janus Green) can be used. In addition, Surcup AC
90 is a brightening agent for smoothing the plating surface.

In the electric Cu plating apparatus shown in FIG. 8, the amount of the electric Cu plating solution 29 is about 40 L, and the flow rate is set to about 15 L / min, which is an apparatus condition for realizing the present invention. Using the above-described electric Cu plating solution 29, a current density of 1 A / dm ² and a plating time of about 68 minutes are processed.
An electric Cu plating film for the filled via hole pad 14A and the wiring 14B to be the second conductor layer is simultaneously formed.
The thickness of the wiring 14B is about 15 μm. At this time, the inside of the through-hole 12 and the non-through-hole 13 is also Cu.
It is filled with a plating film and formed simultaneously with the via hole pad 14A. Janus Green
(Green) By using the property of preferentially growing the plating film from the bottom surface of the via hole closing lower portion, the via hole step is sufficiently flattened, so that the polishing step becomes unnecessary.

Here, the via feeling according to the present embodiment will be described with reference to FIG. FIG. 9 is an explanatory diagram of the via feeling in the method for manufacturing the multilayer wiring board according to the first embodiment of the present invention.

In FIG. 9, the horizontal axis represents the upper diameter (μm) of the opening of the via hole, and the vertical axis represents the via feeling. The solid line A connecting the black circles indicates the via feeling when the electric Cu plating solution according to the present embodiment is used. The via feeling is a value obtained by calculating a plating thickness ratio in a via hole with respect to a flat portion plating thickness corresponding to a wiring plating thickness. Further, the solid line B connecting the white circles indicates that the electric Cu plating solution according to the present embodiment described above indicates Jan Jan.
7 shows via feeling when a conventional electric Cu plating solution except for us green (Janus Green) is used.

Here, an experimental sample was prepared according to the steps shown in FIGS. At this time, in the experimental sample, laser via holes having upper diameters of about 20 to 90 μm were formed using metal masks having different opening diameters.

In the case of using the conventional electric Cu plating solution, as shown by the solid line B, the via growth is isotropic plating growth of about 1. On the other hand, in the present embodiment, the via feeling is remarkably improved. In particular, the via feeling is 3 or more when the upper diameter of the via hole opening is 40 μm or less. Therefore, as shown in FIG. 5, a via hole having a depth of about 45 μm is formed with a wiring plating thickness of about 15 μm.
Can be filled.

Next, returning to FIG. 5, an electric Ni plating film is formed on the surface of the Cu plating film by using, for example, a Watt bath containing nickel sulfate, nickel chloride, boric acid and a brightener. The electric Ni plating film is for improving the adhesiveness with the resin film laminated thereon, and is formed to a thickness of about 0.5 μm to form the Cu / Ni plating film 14.

Next, after the resist is removed, the plated conductive film 5 is etched using the Cu / Ni plated film as a mask. In the etching of the plating conductive film 5, for example, a Cu film is etched using sodium persulfate, and a Cr film is etched using potassium permanganate. As a result, the filled via hole pad 14A and the wiring 14B serving as the second conductor layer are simultaneously formed.

Similarly, by repeating the steps of FIGS. 2 to 5, the multilayer wiring portion 15 is formed by successive lamination. That is, similarly to FIG. 2, the sheet 1 with the copper foil pattern manufactured in the separation step of FIG. 1 is formed on the resin film 10 on which the via hole pads 14A and the wirings 14B are formed, via the resin film insulating layer 3 ′. The copper foil 11 'side is fixed by press bonding. Here, the thickness of the resin film insulating layer 3 ′ is about 45 μm. After fixation, the titanium frame is removed by cutting the resin film 10 'at the inner peripheral side of the titanium frame, and unnecessary peripheral portions of the copper foil-patterned sheet 1' are cut.

Next, similarly to FIG. 3, by laser processing,
A through-hole and a non-through-hole are simultaneously formed. Next, similarly to FIG. 4, a plating conductive film 5 'is formed on the surface of the resin film 10' in which the via hole is formed. Next, a resist pattern for plating formation is formed on the surface of the plating conductive film 5 '. Further, as in FIG.
A filled via hole pad 14 serving as a second conductor layer is formed on the surface of the plated conductive film 5 'by using an electric Cu plating apparatus.
A ′ and the wiring 14B ′ are formed simultaneously.

Next, as shown in FIG. 7, an uppermost resin film insulating layer 3 ″ is fixed on the resin film 10 ′ on which the via hole pads 14A ′ and the wirings 14B ′ are formed. Similarly, a non-penetrating via hole is formed by laser processing through a metal mask, and the thickness of the resin film insulating layer 3 ″ is about 30 μm. Then, similarly to FIG. 4, a plated conductive film 5 ″ is formed on the surface of the insulating layer 3 ″ where the via hole is formed. The plating conductive film 5 ″ is, for example,
The chromium (Cr) film is a laminated film having a thickness of about 0.05 μm and the Cu film having a thickness of about 0.5 μm. Next, a resist pattern for forming a plating is formed on the surface of the plating conductive film 5 ″.
μm. Next, an electric Ni plating film having a thickness of about 2 μm is formed using a Watt bath. In order to prevent a decrease in solder wettability due to oxidation of the Ni film, an electric Au plating film is formed to a thickness of about 0.2 μm using gold sodium sulfite.
/ Au plating film 8. After removing the resist, Ni /
Using the Au plating film 8 as a mask, the Cu film and the Cr film constituting the plating conductive film 5 ″ are respectively etched to form LSI connection terminal layers.

As described above, the lowermost first insulating layer 3 and the uppermost insulating layer 3 ″ are a polyquinoline-based resin sheet having a thickness of about 30 μm, and the other inner insulating layers 3 ′ are about 4 μm thick.
A 5 μm polyquinoline-based resin sheet is used.
The above is an example of three layers. In the case of three or more layers, the depth of the through via hole can be made equal to 45 μm by setting the thickness of the inner insulating layer to about 45 μm.

As described above, the filling of the metal conductor into the via hole having a high aspect ratio is performed by utilizing the excellent via feeling. In order to obtain the multilayer wiring portion shown in FIG. 6, the steps of FIGS.
Compared with the example described later, the step of forming the via hole and the step of filling the via hole with the metal conductor are halved, and the processing time can be significantly reduced. Further, if via holes of three or more insulating layers are simultaneously formed according to the via feeling, further cost reduction can be achieved.

As described above, according to the present embodiment, the plating film is preferentially applied to the conventionally used electroplating solution from the bottom bottom surface of the via hole without using a special electrolytic method or plating solution. By simply adding a substance having the property of growing a metal conductor, a smooth conductor layer filled with a metal conductor in a blind via hole can be formed by a direct current electrolysis method. Therefore, there is no need to significantly change the conventional plating method using the DC electrolysis method, so that the method is extremely versatile. Further, since a via-on-via connection structure in which a high-density wiring pattern is formed can be realized without the need for a planarization step such as polishing, which is essential in the prior art, a high-performance and low-cost multilayer wiring substrate can be manufactured.

Furthermore, because of excellent via feeling, the filling of the via hole with the metal conductor and the formation of the wiring pattern are performed at the same time, or the formation of the via hole of two or more insulating layers is performed at the same time. Can be simultaneously performed, and the cost can be reduced by various applications.

Next, a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention will be described with reference to FIGS. 10 to 16 are process diagrams showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention. The same reference numerals as those in FIGS. 1 to 7 indicate the same parts.

As shown in FIG. 10, a polyimide sheet 16 which is a resin film insulating layer is prepared. Polyimide sheet 1
Reference numeral 6 has a thermoplastic portion and a non-thermoplastic portion, and has a thickness of, for example, about 15 μm.

Next, as shown in FIG.
Then, the thermoplastic portion of the polyimide sheet 16 serving as the first insulating layer is fixed to the base substrate 2 side. The base material 2 has an outer dimension of about 150 mm
It is a square glass substrate. Next, processing is performed with an excimer laser through a metal mask 4 to obtain an upper opening diameter of about 50 μm.
A laser via hole 17 having a depth of about 15 μm is formed.

Next, as shown in FIG.
On the surface of the polyimide sheet 16 on which the layer 7 is formed, a laminated film having a thickness of about 0.05 μm of a Cr film and a thickness of about 0.5 μm of a Cu film is formed by sputtering to form a plated conductive film 5. After laminating a film resist on the surface of the plating conductive film 5, exposure, development and post-baking are performed to form a resist pattern 6 for plating formation with a thickness of about 20 μm.

Next, as shown in FIG. 13, an electric Cu plating film having a thickness of about 15 μm is formed in the same manner as in the step of FIG. At this time, since the inside of the via hole 17 is filled, the step of the via hole is sufficiently flattened, and the polishing step becomes unnecessary. Further, in order to improve the adhesiveness with the resin film, an electric Ni plating film is formed to a thickness of about 0.5 μm on the surface of the Cu plating film using a Watt bath to form a Cu / Ni plating film 14. After the resist is stripped, the Cu film forming the plated conductive film 5 is etched using sodium persulfate using the Cu / Ni plating film 14 as a mask, and the Cr film is etched using potassium permanganate. At this time,
The filled via hole pad 14A and the wiring 14B to be the first conductor layer are simultaneously formed.

Next, as shown in FIG. 14, a polyquinoline-based resin sheet 3 having a thickness of about 30 μm serving as a second insulating layer was formed.
Via-hole pad 1 as first conductor layer by press bonding
4A and the wiring 14B. At this time, the first
Since the conductor layer is embedded in the polyquinoline-based resin sheet 3, the step of the conductor pattern is sufficiently flattened, and the polishing step is not required.

Similarly, the steps of FIGS. 11 to 14 are repeated to form the multilayer wiring portion 15 by successive lamination. However, the insulating layers 3, 3 ', other than the lowermost first insulating layer 16,
3 ″ and 3 ′ ″ all use a polyquinoline-based resin sheet having a thickness of about 30 μm.

Next, as shown in FIG. 16, in the same manner as in the step of FIG. 7, a Ni / Au plating film 8 is formed, and an LSI connection terminal layer is formed.

As described above, according to the present embodiment, the plating film is preferentially applied to the conventionally used electroplating solution from the bottom surface under the via hole block without using a special electrolytic method or a plating solution. By simply adding a substance having the property of growing a metal conductor, a smooth conductor layer filled with a metal conductor in a blind via hole can be formed by a direct current electrolysis method. Further, since a via-on-via connection structure in which a high-density wiring pattern is formed can be realized without the need for a planarization step such as polishing, which is essential in the prior art, a high-performance and low-cost multilayer wiring substrate can be manufactured.
Furthermore, because of the excellent via feeling, the metal conductor is filled into the via hole and the wiring pattern is formed at the same time. Can be simultaneously performed, and the cost can be reduced by various applications.

Next, a method for manufacturing a multilayer wiring board according to the third embodiment of the present invention will be described with reference to FIGS. 17 to 23 are process diagrams showing a method for manufacturing a multilayer wiring board according to the third embodiment of the present invention. The same reference numerals as those in FIGS. 1 to 7 and FIGS. 11 to 16 indicate the same parts.

First, as shown in FIG. 17, a glass substrate having an outer dimension of about 150 mm square is used as the base substrate 2. After the surface of the base material 2 and the coupling treatment, spin coating, subjected to cure baking, to a thickness of about 6μm forming a polyimide film 18 serving as the first insulating layer.

Next, as shown in FIG. 18, a liquid resist is spin-coated on the surface of the polyimide film 18 and baked, and then exposed, developed and post-baked to form a polyimide processing resist pattern 19 having a thickness of about 5 μm is formed. The resist pattern 19 is used as a mask, and after etching using hydrazine, the resist is peeled off to form a photo via hole 21 having a depth of about 6 μm.

Next, as shown in FIG.
On the surface of the polyimide film 18 on which 1 is formed, a laminated film having a thickness of about 0.05 μm of a Cr film and a thickness of about 0.5 μm of a Cu film is formed by sputtering to form a plated conductive film 5. A resist pattern 20 for forming a plating is formed on the surface of the plating conductive film 5 to a thickness of about 8 μm.

Next, as shown in FIG. 20, an electric Cu plating film 14 having a thickness of about 5 μm is formed in the same manner as in the step of FIG. At this time, the processing was performed at a current density of 1 A / dm ² and a plating time of about 22 min, and only the target film thickness was changed.
At this time, since the inside of the via hole is filled, the step of the via hole is flattened, and the polishing step becomes unnecessary. Further, in order to improve the adhesiveness with the resin film 18, the Cu plating film 14
An electric Ni plating film having a thickness of about 0.5 μm is formed on the surface of the substrate by using a Watt bath to form a Cu / Ni plating film 14. After the resist is stripped, the Cu film constituting the plated conductive film 5 is etched using sodium persulfate using the Cu / Ni plating film 14 as a mask, and the Cr film is etched using potassium permanganate. At this time, the filled via hole pad 14A and the wiring 14B serving as the first conductor layer are formed.
Are simultaneously formed.

Next, similar to the process shown in FIG.
A polyimide film 18 'having a thickness of about 6 [mu] m to be a second insulating layer is formed. At this time, since the polyimide film 18 'has a thickness sufficient to flatten the first conductive layer, the step of the conductive pattern is flattened, and the polishing step becomes unnecessary.

Similarly, the steps shown in FIGS. 18 to 21 are repeated to form a multilayer wiring portion 15 by successive lamination.

Further, similarly to the process shown in FIG.
A Ni / Au plating film 8 is formed, and an LSI connection terminal layer is formed.

As described above, according to the present embodiment, the plating film is preferentially applied to the conventionally used electroplating solution from the bottom bottom surface of the via hole without using a special electrolytic method or a plating solution. By simply adding a substance having the property of growing a metal conductor, a smooth conductor layer filled with a metal conductor in a blind via hole can be formed by a direct current electrolysis method. Further, since a via-on-via connection structure in which a high-density wiring pattern is formed can be realized without the need for a planarization step such as polishing, which is essential in the prior art, a high-performance and low-cost multilayer wiring substrate can be manufactured.
Furthermore, because of the excellent via feeling, the metal conductor is filled into the via hole and the wiring pattern is formed at the same time. Can be simultaneously performed, and the cost can be reduced by various applications.

[0054]

According to the present invention, it is possible to form a smooth conductor layer in which metal conductors are filled in blind via holes by a direct current electrolysis method without using a special electrolysis method or a plating solution.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a multilayer wiring board according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 3 is a process chart showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 5 is a process chart showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 6 is a process chart showing a method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 7 is a process chart showing a method for manufacturing the multilayer wiring board according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a configuration of an electric Cu plating apparatus used in the method for manufacturing a multilayer wiring board according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram of via feeling in the method for manufacturing the multilayer wiring board according to the first embodiment of the present invention.

FIG. 10 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 11 is a process chart illustrating a method for manufacturing a multilayer wiring board according to a second embodiment of the present invention.

FIG. 12 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 13 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 14 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 15 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 16 is a process chart showing a method for manufacturing a multilayer wiring board according to the second embodiment of the present invention.

FIG. 17 is a process chart illustrating the method for manufacturing the multilayer wiring board according to the third embodiment of the present invention.

FIG. 18 is a process chart illustrating the method for manufacturing the multilayer wiring board according to the third embodiment of the present invention.

FIG. 19 is a process chart illustrating the method for manufacturing the multilayer wiring board according to the third embodiment of the present invention.

FIG. 20 is a process chart illustrating the method for manufacturing the multilayer wiring board according to the third embodiment of the present invention.

FIG. 21 is a process chart showing a method for manufacturing a multilayer wiring board according to the third embodiment of the present invention.

FIG. 22 is a process chart illustrating the method for manufacturing the multilayer wiring board according to the third embodiment of the present invention.

FIG. 23 is a process chart showing a method for manufacturing a multilayer wiring board according to the third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Sheet with copper foil pattern 2 ... Base base material 3 ... Polyquinoline-based resin sheet 4 ... Metal mask 5 ... Plating conductive film 6 ... Film resist pattern (for plating formation) 8 ... Ni / Au plating film 9 ... Ti frame 10 ... Resin film 11 Copper foil 12 Through via hole 13 Non-through via hole 14 Cu / Ni plating film 14 A Via hole pad 14 B Wiring 15 Multilayer wiring portion 16 Polyimide sheet 17 21 21 Via hole 18 Polyimide film 19 20 ... resist pattern 22 ... substrate to be plated 23 ... substrate jig 24 ... phosphorus-containing copper plate 25 ... shielding plate 26 ... liquid discharge part 27 ... plating liquid flow 28 ... overflow part 29 ... plating liquid

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Haruhiko Matsuyama 1st Horiyamashita, Hadano-shi, Kanagawa F-term in the Enterprise Server Division, Hitachi, Ltd. 4K024 AA02 AA03 AA09 AA11 AB01 AB02 BA09 BB11 BC02 GA16 5E317 AA24 BB01 BB11 CC33 CC53 GG16 5E346 CC02 CC08 CC10 CC55 EE12 EE13 EE18 EE19 EE20 FF01 FF07 FF10 FF14 GG15 GG17 GG27 GG28 HH07 HH11

Claims (4)

[Claims] A blind via hole having a closed structure is formed on one side of an insulating layer of a resin film, a conductive film is formed on the surface of the insulating layer including the wall surface of the via hole, and a metal is formed by electroplating through the conductive film. In a method for manufacturing a multilayer wiring board, wherein a film is formed and a resin film insulating layer and a conductor layer of a metal film are alternately and sequentially formed on a base material, the metal film of the electroplating step is used as an electroplating solution used for the electroplating. Addition of a substance that reduces and decomposes at the potential at which the metal film is deposited, suppresses the deposition of the metal film and, at the same time, slows the diffusion rate and produces a difference in the effect of suppressing the deposition of the metal film on the upper side surface of the via hole opening and the lower bottom surface of the via hole closure. A method for manufacturing a multilayer wiring board, comprising using a prepared electroplating solution. 2. The method for manufacturing a multilayer wiring board according to claim 1, wherein a step of filling the via hole with a metal film, and a step of forming a conductive layer on the smooth layer other than the via hole forming portion, above the insulating layer. Forming a metal film wiring pattern at the same time. 3. The method for manufacturing a multilayer wiring board according to claim 1, wherein a through via hole penetrating a conductor layer below the insulating layer and a non-penetrating via hole up to the conductor layer below the insulating layer are simultaneously formed. Forming a through hole and simultaneously filling a metal film in the through-hole and the non-through-hole. 4. The method for manufacturing a multilayer wiring board according to claim 1, wherein the step of forming a conductor layer below the insulating layer is a separation step.