JP2002170470A - Semiconductor micro relay and manufacturing method thereof - Google Patents
Semiconductor micro relay and manufacturing method thereofInfo
- Publication number
- JP2002170470A JP2002170470A JP2000361975A JP2000361975A JP2002170470A JP 2002170470 A JP2002170470 A JP 2002170470A JP 2000361975 A JP2000361975 A JP 2000361975A JP 2000361975 A JP2000361975 A JP 2000361975A JP 2002170470 A JP2002170470 A JP 2002170470A
- Authority
- JP
- Japan
- Prior art keywords
- conductive portion
- movable
- semiconductor
- fixed
- movable conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000007747 plating Methods 0.000 claims abstract description 48
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 12
- 238000005452 bending Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 239000011651 chromium Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H59/00—Electrostatic relays; Electro-adhesion relays
- H01H59/0009—Electrostatic relays; Electro-adhesion relays making use of micromechanics
Landscapes
- Micromachines (AREA)
- Thermally Actuated Switches (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体マイクロリ
レー及びその製造方法に関し、詳しくは半導体基板上へ
のメッキ積層構造により基板面の鉛直方向に開閉動作す
る接点構造を実現した半導体マイクロリレー及びその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor microrelay and a method for manufacturing the same, and more particularly, to a semiconductor microrelay realizing a contact structure which can be opened and closed in a vertical direction on a substrate surface by plating a semiconductor substrate. It relates to a manufacturing method.
【0002】[0002]
【従来の技術】一般に半導体基板の基板面の鉛直方向に
開閉動作する接点構造を有する縦開閉型の半導体マイク
ロリレーは、ベース基板上に該ベース基板とはクリアラ
ンスを開けて対向する梁状の可動部を基板面の鉛直方向
に湾曲動作可能に支持固定し、該可動部とベース基板と
の接触位置に電極を夫々形成して開閉接点部とした構造
を有している。従来のこの種の半導体マイクロリレー
は、異方性エッチング等による凹所や開口の形成、並び
に酸化膜層或いは埋込犠牲層の除去による空隙部の形成
といったマイクロ加工を主に駆使してシリコン基板を加
工することにより接点部の開閉構造を実現したものであ
った。しかしながら、シリコン基板のマイクロ加工は一
般にシリコンの結晶方位性に依存するため構造設計上の
自由度に制約を受けるものであり、また意図する構造を
形成するには複雑な製造工程を要するものであった。一
方、半導体基板上に設けたメッキ層により接点開閉構造
を形成する半導体マイクロリレーも知られているが、こ
れは基板平面方向に開閉接点の動作部が並設され且つこ
れらが該水平方向に開閉する横開閉型のものであった。2. Description of the Related Art In general, a vertical opening / closing type semiconductor microrelay having a contact structure that opens and closes in a vertical direction on a substrate surface of a semiconductor substrate is provided on a base substrate with a beam-like movable surface facing the base substrate with a clearance therebetween. The movable portion and the base substrate are supported and fixed so as to be able to bend in the vertical direction of the substrate surface, and electrodes are formed at contact positions between the movable portion and the base substrate to form a switching contact portion. Conventional semiconductor micro relays of this type mainly use micro processing such as formation of recesses and openings by anisotropic etching and the like, and formation of voids by removal of an oxide film layer or a buried sacrificial layer. In this way, the opening and closing structure of the contact portion was realized by processing. However, microfabrication of a silicon substrate generally depends on the crystal orientation of silicon and is therefore limited in the degree of freedom in structural design, and requires a complicated manufacturing process to form an intended structure. Was. On the other hand, there is also known a semiconductor microrelay in which a contact switching structure is formed by a plating layer provided on a semiconductor substrate. However, in this case, operating parts of switching contacts are arranged side by side in a plane direction of the substrate and these are opened and closed in the horizontal direction. It was of the horizontal opening and closing type.
【0003】[0003]
【発明が解決しようとする課題】本発明は上記事情に鑑
みてなされたものであり、その目的は、構造設計上の制
約を受けることなく比較的簡便な製造工程にて製造可能
な縦開閉型の半導体マイクロリレー及びその製造方法を
提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a vertical opening / closing type which can be manufactured by a relatively simple manufacturing process without being restricted by a structural design. And a method of manufacturing the same.
【0004】[0004]
【課題を解決するための手段】請求項1記載の半導体マ
イクロリレーにおいては、半導体基板と、この基板上に
形成された絶縁層と、この絶縁層上にメッキにより形成
された固定導電部と、この固定導電部と電気的に分離し
た状態で間隔をあけて対向するようメッキにより形成さ
れた梁状の可動導電部と、上記固定導電部よりも上位に
立ち上がって上記可動導電部の一部に連結され該可動導
電部を上記基板に対し物理的に支持する支持部と、上記
可動導電部上に形成され該可動導電部の一部を上記固定
導電部に電気的に導通するよう上記半導体基板の基板面
の鉛直方向に撓ませる作動部と、を備えたことを特徴と
する。この半導体マイクロリレーにおいては、上記作動
部の作用により上記可動導電部が基板面方向へ撓んで固
定導電部と導通するようになることでリレーとしての役
目をするものであって、上記固定導電部と可動導電部は
共にメッキにより形成されているので、このメッキやマ
スクの積層工程の組み合わせによって、比較的簡易な工
程で製造することができる。さらに従来のような基板の
結晶方位性等の材料の特性による構造設計上の制約を受
けることもない。According to a first aspect of the present invention, there is provided a semiconductor microrelay, comprising: a semiconductor substrate; an insulating layer formed on the substrate; a fixed conductive portion formed on the insulating layer by plating; A beam-shaped movable conductive portion formed by plating so as to face the fixed conductive portion at an interval while being electrically separated from the fixed conductive portion, and rise up above the fixed conductive portion to form a part of the movable conductive portion. A supporting portion connected to the substrate to physically support the movable conductive portion, and the semiconductor substrate formed on the movable conductive portion and electrically connecting a part of the movable conductive portion to the fixed conductive portion. And an operating portion for bending the substrate surface in the vertical direction. In this semiconductor micro relay, the movable conductive part is bent toward the substrate surface by the action of the operating part and becomes conductive with the fixed conductive part, thereby serving as a relay. Since the and the movable conductive portion are both formed by plating, it can be manufactured in a relatively simple process by a combination of the plating and the lamination process of the mask. Further, there is no restriction on the structural design due to the characteristics of the material such as the crystal orientation of the substrate as in the related art.
【0005】請求項2記載の半導体マイクロリレーにお
いては、請求項1記載の半導体マイクロリレーにおい
て、上記可動導電部の基板側対向面には撓んだときに上
記固定導電部に導通する接点部が突接されていることを
特徴とする。このものでは、突設した上記接点部によっ
て、上記固定導電部の接点部と確実に接触させることが
できる。According to a second aspect of the present invention, there is provided the semiconductor micro relay of the first aspect, wherein the movable conductive portion has a contact portion which is electrically connected to the fixed conductive portion when the movable conductive portion is bent. It is characterized by being abutted. In this case, the projecting contact portion can surely make contact with the contact portion of the fixed conductive portion.
【0006】ここで上記作動部は上記可動導電部を基板
面方向へ撓ませるものであり、この作動部は自ら可動導
電部へ作用するものであって良く、或は上記可動導電部
と協働するものであっても良い。即ち上記作動部として
は、例えば請求項3記載の如く圧電素子や、請求項4記
載の如く形状記憶合金といった、自ら可動導電部へ作用
するものであって良く、また請求項5記載の如く、上記
可動導電部よりも熱膨張係数の大きい薄膜層として設け
て可動導電部と協働する、いわゆるバイメタルとして機
能するようにしても良い。請求項3記載のような、上記
作動部が圧電素子である半導体マイクロリレーにおいて
は、この圧電素子に電圧を印加すると、上記作動部が上
記可動導電部を上記基板面に向かって作動させる。従っ
て上記可動導電部の接点部と上記固定導電部の接点部が
接触する。請求項4記載のような、上記作動部が形状記
憶合金である半導体マイクロリレーにおいては、上記可
動導電部を加熱する加熱手段が備わっているので、この
加熱手段により上記作動部を加熱することにより、該作
動部である形状記憶合金が変形して、上記可動導電部を
上記基板面に向かって作動させ、ひいては上記可動導電
部の接点部と上記固定導電部の接点部が接触する。請求
項5記載のような、上記作動部が上記可動導電部より熱
膨張係数が大きい薄膜層である半導体マイクロリレーに
おいては、上記可動導電部を加熱する加熱手段が備わっ
ているので、この加熱手段が作動すると、上記作動部が
上記可動導電部よりも大きく膨張するので、バイメタル
の作用により、上記作動部は上記可動導電部を上記基板
面に向かって作動させ、ひいては上記可動導電部の接点
部と上記固定導電部の接点部が接触する。Here, the operating portion bends the movable conductive portion toward the surface of the substrate, and the operating portion may act on the movable conductive portion by itself, or may cooperate with the movable conductive portion. You may do. That is, the actuating section may be one that acts on the movable conductive section by itself, such as a piezoelectric element as described in claim 3 or a shape memory alloy as described in claim 4. It may be provided as a thin film layer having a larger thermal expansion coefficient than that of the movable conductive portion and function as a so-called bimetal which cooperates with the movable conductive portion. In a semiconductor microrelay in which the operating section is a piezoelectric element, when a voltage is applied to the piezoelectric element, the operating section operates the movable conductive section toward the substrate surface. Therefore, the contact part of the movable conductive part and the contact part of the fixed conductive part come into contact with each other. In the semiconductor micro relay in which the operating part is a shape memory alloy as described in claim 4, since the heating means for heating the movable conductive part is provided, the heating part heats the operating part. Then, the shape memory alloy as the operating portion is deformed, and the movable conductive portion is operated toward the substrate surface, so that the contact portion of the movable conductive portion comes into contact with the contact portion of the fixed conductive portion. A semiconductor microrelay according to claim 5, wherein the operating portion is a thin film layer having a larger coefficient of thermal expansion than the movable conductive portion, since the heating portion for heating the movable conductive portion is provided. When actuated, the operating portion expands more than the movable conductive portion, and the action of the bimetal causes the operating portion to actuate the movable conductive portion toward the substrate surface, and thus the contact portion of the movable conductive portion. And the contact portion of the fixed conductive portion contacts.
【0007】請求項6記載の半導体マイクロリレー製造
方法は、基板上に絶縁層を設け該絶縁層上に電気的に分
離した状態でベース電導部及び固定導電部をメッキにて
形成する工程と、上記ベース電導部を除く箇所にレジス
トを積載する工程と、上記ベース電導部上に起端部を、
上記レジスト上に可動導電部を、夫々メッキにて形成す
る工程と、上記レジストを除去し空隙部を形成する工程
と、上記空隙部に接した上記可動導電部上に、上記可動
導電部を基板面に対して鉛直方向に作動させる作動部を
載置する工程と、を含むことを特徴とする。この工程で
は上記レジストの厚さを大きくすることにより、上記可
動導電部と上記固定導電部との空間を大きくすることが
できる。従って上記空間の大きい半導体マイクロリレー
が製造される。また、メッキの形成条件を調整すること
により、上記可動導電部に内在する内部応力を自由にコ
ントロールすることができ、上記可動導電部の反りの発
生を抑えることができる。またメッキの積層、レジスト
積載、及びレジスト除去の工程により、この半導体マイ
クロリレーが形成されるので、製造工程が比較的簡単で
あるとともに、基板の結晶方位性等の材料の特性を気に
せずに製造することができる。A method of manufacturing a semiconductor micro relay according to claim 6, wherein an insulating layer is provided on a substrate, and a base conductive portion and a fixed conductive portion are formed by plating while being electrically separated on the insulating layer; A step of loading a resist at a location other than the base conductive part, and a starting part on the base conductive part,
Forming a movable conductive portion on the resist by plating, removing the resist to form a void, and mounting the movable conductive portion on the movable conductive portion in contact with the void. Mounting an operating part that operates in a vertical direction with respect to the surface. In this step, the space between the movable conductive part and the fixed conductive part can be increased by increasing the thickness of the resist. Therefore, a semiconductor microrelay with a large space is manufactured. Further, by adjusting the plating conditions, the internal stress existing in the movable conductive portion can be freely controlled, and the occurrence of warpage of the movable conductive portion can be suppressed. In addition, since this semiconductor micro relay is formed by the steps of lamination of plating, loading of resist, and removal of resist, the manufacturing process is relatively simple, and the characteristics of the material, such as the crystal orientation of the substrate, are not considered. Can be manufactured.
【0008】請求項7記載の半導体マイクロリレー製造
方法は、請求項6記載の半導体マイクロリレーの製造方
法に関して、上記レジスト形成工程において、積載され
たレジスト層の上面には上記可動導電部の接点に相当す
る位置に凹所が設けられることを特徴とする。この工程
により上記可動導電部の接点部が突出された半導体マイ
クロリレーが、メッキの積層、レジスト積載及びレジス
ト除去の工程により製造される。According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor microrelay according to the sixth aspect, in the resist forming step, an upper surface of the stacked resist layer is provided with a contact of the movable conductive portion. A recess is provided at a corresponding position. By this step, a semiconductor micro relay from which the contact portion of the movable conductive part is projected is manufactured by the steps of stacking plating, loading resist, and removing resist.
【0009】[0009]
【発明の実施の形態】以下、本発明の実施形態について
説明する。Embodiments of the present invention will be described below.
【0010】図1は、実施形態に係る半導体マイクロリ
レーの構造を示す斜視図である。絶縁層(シリコン酸化
膜)7が表面に形成されたN型シリコン基板1(以後シ
リコン基板1と称す)上に、2個の固定導電部21a、
21bが設けられている。この2個の固定導電部21
a、21bに電気的に分離した状態で間隔をあけて対向
するようにメッキにて形成された可動導電部31が梁状
に設けられており、2個の固定導電部21a、21bよ
りも上位に立ち上がって可動導電部31の一部に連結さ
れ、可動導電部31を基板1に対し物理的に支持する支
持部51が基板1に設けられている。この支持部51
は、後述するベース電導部20、ベース電導部20上に
載置される後述の第二導電層5、及び後述の第二メッキ
層6により構成される。さらに可動導電部31上に、可
動導電部31の一部を2個の固定導電部21a、21b
に電気的に導通するようにシリコン基板1面の鉛直方向
に撓ませる作動部8が載置されている。この作動部8
は、例えば後述する圧電素子35(図1)、形状記憶合
金36(図4)、或は可動導電部31よりも熱膨張係数
の大きい薄膜層37(図5)として設けることができる
ものである。FIG. 1 is a perspective view showing the structure of the semiconductor micro relay according to the embodiment. On an N-type silicon substrate 1 (hereinafter referred to as a silicon substrate 1) having an insulating layer (silicon oxide film) 7 formed on the surface, two fixed conductive portions 21a,
21b is provided. These two fixed conductive parts 21
A movable conductive part 31 formed by plating is provided in a beam shape so as to oppose at a distance while being electrically separated from a and 21b, and is higher than the two fixed conductive parts 21a and 21b. The substrate 1 is provided with a supporting portion 51 that rises to the position and is connected to a part of the movable conductive portion 31 and physically supports the movable conductive portion 31 with respect to the substrate 1. This support 51
Is composed of a base conductive portion 20 described later, a second conductive layer 5 described below mounted on the base conductive portion 20, and a second plating layer 6 described later. Further, on the movable conductive part 31, a part of the movable conductive part 31 is divided into two fixed conductive parts 21a and 21b.
An operating section 8 is provided to bend in the vertical direction of the surface of the silicon substrate 1 so as to be electrically connected to the silicon substrate 1. This operating part 8
Can be provided, for example, as a piezoelectric element 35 (FIG. 1), a shape memory alloy 36 (FIG. 4), or a thin film layer 37 (FIG. 5) having a larger thermal expansion coefficient than the movable conductive part 31 described later. .
【0011】作動部8により可動導電部31が基板面の
鉛直方向にシリコン基板1の方向へ撓み、可動導電部3
1が2個の固定導電部21a、21bに接触する。これ
により2個の固定導電部21a、21bは電気的に導通
する状態になる。The movable conductive part 31 is bent in the direction of the silicon substrate 1 in the vertical direction of the substrate surface by the operating part 8, and the movable conductive part 3
1 contacts the two fixed conductive portions 21a and 21b. As a result, the two fixed conductive portions 21a and 21b enter a state of being electrically conductive.
【0012】図2に半導体マイクロリレーの製造方法の
一例を示す。FIG. 2 shows an example of a method for manufacturing a semiconductor microrelay.
【0013】まずシリコン基板1上に絶縁層(シリコン
酸化膜)7を形成した後、第一導電層2を電子ビーム蒸
着(以後EB蒸着と称す)またはスパッタ等装置により
形成する。第一導電層2の材料は後述の第一メッキ層4
と密着性が確保できる材料であり、例えば第一メッキ層
4の材料がニッケルである場合、第一導電層2の材料は
ニッケル或はチタン等を選択することができる。次に第
一メッキ層4を形成しない部分に予めレジスト3をスピ
ン塗布により形成する。このレジスト3の厚みはレジス
ト3の粘度、スピン塗布時の回転数及び時間の選択によ
り自由に設定できる。次に第一メッキ層4を第一導電層
2上の上記レジスト3を除く部分に形成する。そしてレ
ジスト3をレジスト剥離液(例えばアセトン)により剥
離除去し、それにより表面に露出する第一導電層2を硝
酸を用いてエッチングし除去する。こうしてベース電導
部20と固定導電部21が形成される。次にレジスト3
を、シリコン基板1上のベース電導部20を除く部分、
即ちシリコン基板1上における、絶縁層7上及び固定導
電部21上にスピン塗布により厚みを調整しながら形成
する。次に第二導電層5をレジスト3上及びベース電導
部20上にEB蒸着またはスパッタ等装置により形成
し、その後第二メッキ層6を該第二導電層5上に形成す
る。その後レジスト3をレジスト剥離液により剥離除去
することで、空間10が形成される。こうして空間10
上に梁形状に形成された第二導電層5及び第二メッキ層
6が、可動導電部31と成る。そして可動導電部31上
に、可動導電部31をシリコン基板1面鉛直方向に作動
させる作動部8を載置する。なお、レジスト剥離液によ
りレジスト3を剥離除去する工程と、可動導電部31上
に作動部8を載置する工程は、どちらが先であっても構
わない。First, after an insulating layer (silicon oxide film) 7 is formed on the silicon substrate 1, the first conductive layer 2 is formed by an apparatus such as electron beam evaporation (hereinafter referred to as EB evaporation) or sputtering. The material of the first conductive layer 2 is a first plating layer 4 described later.
For example, when the material of the first plating layer 4 is nickel, nickel or titanium can be selected as the material of the first conductive layer 2. Next, a resist 3 is previously formed by spin coating on a portion where the first plating layer 4 is not formed. The thickness of the resist 3 can be freely set by selecting the viscosity of the resist 3, the number of rotations during spin coating, and the time. Next, a first plating layer 4 is formed on the first conductive layer 2 except for the resist 3. Then, the resist 3 is stripped and removed with a resist stripping solution (for example, acetone), and thereby the first conductive layer 2 exposed on the surface is etched and removed using nitric acid. Thus, the base conductive part 20 and the fixed conductive part 21 are formed. Next, resist 3
A portion of the silicon substrate 1 excluding the base conductive portion 20,
That is, it is formed on the insulating layer 7 and the fixed conductive portion 21 on the silicon substrate 1 while adjusting the thickness by spin coating. Next, a second conductive layer 5 is formed on the resist 3 and the base conductive part 20 by an apparatus such as EB evaporation or sputtering, and then a second plating layer 6 is formed on the second conductive layer 5. Thereafter, the resist 3 is stripped and removed with a resist stripping solution, so that the space 10 is formed. Thus space 10
The second conductive layer 5 and the second plating layer 6 formed in a beam shape on the upper side constitute the movable conductive portion 31. Then, on the movable conductive part 31, the operation part 8 for operating the movable conductive part 31 in the vertical direction of the silicon substrate 1 is placed. Either of the step of removing the resist 3 with the resist removing liquid and the step of placing the operating unit 8 on the movable conductive unit 31 may be performed first.
【0014】作動部8が圧電素子35の場合を説明する
(図1)。圧電素子35は可動導電部31上に接着剤に
て貼り付ける。圧電素子35と第二メッキ層6に直流電
圧を印加すると、圧電素子35の作用により、可動導電
部31は2個の固定導電部21a、21bの方向へ撓み
接触する。従って2個の固定導電部21a、21bは電
気的に導通する状態になる。直流電圧の印加を停止する
と、可動導電部31は2個の固定導電部21a、21b
から離れる。従って2個の固定導電部21a、21bは
電気的に絶縁状態になる。こうして半導体マイクロリレ
ーとして構成される。The case where the operating section 8 is a piezoelectric element 35 will be described (FIG. 1). The piezoelectric element 35 is attached on the movable conductive part 31 with an adhesive. When a DC voltage is applied to the piezoelectric element 35 and the second plating layer 6, the action of the piezoelectric element 35 causes the movable conductive part 31 to bend and contact in the direction of the two fixed conductive parts 21a and 21b. Therefore, the two fixed conductive portions 21a and 21b are in a state of being electrically conductive. When the application of the DC voltage is stopped, the movable conductive part 31 becomes two fixed conductive parts 21a and 21b.
Move away from Therefore, the two fixed conductive portions 21a and 21b are electrically insulated. Thus, it is configured as a semiconductor micro relay.
【0015】この圧電素子35を可動導電部31上に載
置した半導体マイクロリレーでは、圧電素子35への印
加電圧の調整により、可動導電部31の、2個の固定導
電部21a、21bへ撓む力を大きくすることができ、
故に可動導電部31の、2個の固定導電部21a、21
bへの接圧を大きくすることができる。従って可動導電
部31と固定導電部21との接圧が確保された半導体マ
イクロリレーが設計できる。In the semiconductor microrelay in which the piezoelectric element 35 is mounted on the movable conductive part 31, the movable conductive part 31 is bent to the two fixed conductive parts 21a and 21b by adjusting the voltage applied to the piezoelectric element 35. Force can be increased,
Therefore, the two fixed conductive portions 21a, 21 of the movable conductive portion 31
The contact pressure with b can be increased. Therefore, a semiconductor micro relay in which the contact pressure between the movable conductive part 31 and the fixed conductive part 21 is ensured can be designed.
【0016】作動部8が形状記憶合金36の場合を説明
する(図3)。形状記憶合金36は可動導電部31上に
接着剤にて貼り付けられる。この形状記憶合金36を加
熱する手段が必要になるが、この加熱手段として例えば
シリコン基板1内にボロンを半導体不純物拡散工程によ
り形成される拡散抵抗40を用いる。この拡散抵抗40
の一部に電圧印加のためにコンタクト窓41を形成し、
さらにこのコンタクト窓41にアルミ配線42を形成す
る。このアルミ配線42を介して上記拡散抵抗40に電
圧を印加すると、上記拡散抵抗40が加熱され、シリコ
ン基板1から可動導電部31の第二メッキ層6及び形状
記憶合金36へ熱が伝わり、形状記憶合金36が温度上
昇する。これにより形状記憶合金36が可動導電部31
に作用し、可動導電部31は2個の固定導電部21a、
21bへ撓み接触する。電圧印加を停止すると加熱が停
止し、形状記憶合金36が冷却し、可動導電部31が2
個の固定導電部21a、21bから離れる。こうして可
動導電部31が2個の固定導電部21a、21bへO
N、OFFすることによりリレーとして機能する。The case where the operating portion 8 is made of a shape memory alloy 36 will be described (FIG. 3). The shape memory alloy 36 is attached on the movable conductive part 31 with an adhesive. A means for heating the shape memory alloy 36 is required. As the heating means, for example, a diffusion resistor 40 formed by boron in the silicon substrate 1 by a semiconductor impurity diffusion step is used. This diffusion resistor 40
Forming a contact window 41 for voltage application on a part of
Further, an aluminum wiring 42 is formed in the contact window 41. When a voltage is applied to the diffusion resistor 40 through the aluminum wiring 42, the diffusion resistor 40 is heated, and heat is transmitted from the silicon substrate 1 to the second plating layer 6 of the movable conductive part 31 and the shape memory alloy 36, and The temperature of the memory alloy 36 rises. As a result, the shape memory alloy 36 is
, The movable conductive part 31 has two fixed conductive parts 21a,
21b. When the voltage application is stopped, the heating stops, the shape memory alloy 36 cools, and the movable conductive part 31
It is separated from the fixed conductive portions 21a and 21b. In this way, the movable conductive part 31 is connected to the two fixed conductive parts 21a and 21b by O.
When N is turned off, it functions as a relay.
【0017】ここで形状記憶合金36においては、可動
導電部31と固定導電部31との空間の大きさに応じて
設計、或は選定をすれば良い。例えば可動導電部31と
固定導電部21との隙間が10μmであるとき、可動導
電部31の固定導電部21との接点部における、基板1
面鉛直方向の変位が10μm以上になるような形状記憶
合金36を選定すればよい。従ってこの可動導電部31
の可動接点部における基板1面鉛直方向の変位を大きく
することで、上記可動接点部と固定導電部21上の接点
部との接圧が確保できる。従って作動層8に形状記憶合
金36を用いることで、接圧が確保された半導体マイク
ロリレーが設計できる。Here, the shape memory alloy 36 may be designed or selected in accordance with the size of the space between the movable conductive part 31 and the fixed conductive part 31. For example, when the gap between the movable conductive part 31 and the fixed conductive part 21 is 10 μm, the substrate 1 in the contact part of the movable conductive part 31 with the fixed conductive part 21 is used.
What is necessary is just to select the shape memory alloy 36 whose displacement in the surface vertical direction is 10 μm or more. Therefore, the movable conductive part 31
By increasing the displacement of the movable contact portion in the vertical direction on the substrate 1 surface, the contact pressure between the movable contact portion and the contact portion on the fixed conductive portion 21 can be secured. Therefore, by using the shape memory alloy 36 for the operation layer 8, a semiconductor micro relay with a secured contact pressure can be designed.
【0018】作動部8が、請求項5に記載の第二メッキ
層6よりも熱膨張係数の大きい薄膜層37の場合とし
て、例えば、第一メッキ層4及び第二メッキ層6がクロ
ム(Cr)で形成され、上記薄膜層37がニッケル(N
i)で形成される場合を考える(図4)。この場合は、
第一導電層及び第二導電層にはクロムを用いる。Crで
ある第二メッキ層6上にはNi/Cr層をEB蒸着し、
このNi/Cr層上にNi層をメッキし薄膜層37を形
成する。そして、予めシリコン基板1内にボロンを半導
体不純物拡散工程により拡散抵抗40を形成し、この拡
散抵抗40の一部に電圧印加のためにコンタクト窓41
を形成し、さらにこのコンタクト窓41にアルミ配線4
2を形成しておく。このアルミ配線42を介して上記拡
散抵抗40に電圧を印加すると、上記拡散抵抗40が加
熱され、シリコン基板1から可動導電部31の第二メッ
キ層6及び薄膜層37へ熱が伝わり、第二メッキ層6及
び薄膜層37が温度上昇する。ここで薄膜層37のニッ
ケルの方が第二メッキ層6のクロムよりも大きく膨張す
るので、バイメタルの機能を果たし、可動導電部31は
2個の固定導電部21a、21bへ撓み接触する。電圧
印加を停止すると、加熱が停止され、可動導電部31の
第二メッキ層6及び薄膜層37の冷却に伴い可動導電部
31が2個の固定導電部21a、21bから離れる。こ
うして可動導電部31が2個の固定導電部21a、21
bへON、OFFすることによりリレーとして機能す
る。In the case where the operating portion 8 is a thin film layer 37 having a larger thermal expansion coefficient than the second plating layer 6 according to claim 5, for example, the first plating layer 4 and the second plating layer 6 may be made of chromium (Cr). ), And the thin film layer 37 is formed of nickel (N
Consider the case formed in i) (FIG. 4). in this case,
Chromium is used for the first conductive layer and the second conductive layer. On the second plating layer 6 of Cr, a Ni / Cr layer is EB deposited,
A thin layer 37 is formed by plating a Ni layer on the Ni / Cr layer. Then, a diffusion resistor 40 is formed in advance in the silicon substrate 1 by a semiconductor impurity diffusion step of boron, and a contact window 41 is formed on a part of the diffusion resistor 40 to apply a voltage.
Is formed, and the aluminum wiring 4 is formed in the contact window 41.
2 is formed in advance. When a voltage is applied to the diffusion resistor 40 through the aluminum wiring 42, the diffusion resistor 40 is heated, and heat is transmitted from the silicon substrate 1 to the second plating layer 6 and the thin film layer 37 of the movable conductive part 31, and The temperature of the plating layer 6 and the thin film layer 37 rises. Here, the nickel of the thin film layer 37 expands more than the chromium of the second plating layer 6, so that it functions as a bimetal, and the movable conductive portion 31 flexes and contacts the two fixed conductive portions 21a and 21b. When the voltage application is stopped, the heating is stopped, and the movable conductive part 31 is separated from the two fixed conductive parts 21a and 21b as the second plating layer 6 and the thin film layer 37 of the movable conductive part 31 are cooled. Thus, the movable conductive part 31 is divided into two fixed conductive parts 21a and 21.
By turning ON and OFF to b, it functions as a relay.
【0019】この場合、作動部8である薄膜層37は、
メッキや蒸着等の半導体プロセスの利用により形成され
るものである。従って、一枚の基板から半導体プロセス
により、一度に大量の半導体マイクロリレーを製造する
ことができる。その結果製造コストが抑えられる。In this case, the thin film layer 37 serving as the operating section 8 is
It is formed by utilizing a semiconductor process such as plating or vapor deposition. Therefore, a large number of semiconductor microrelays can be manufactured at once by a semiconductor process from one substrate. As a result, manufacturing costs are reduced.
【0020】なお、例えば第二メッキ層6がニッケルの
場合は、作動部8にはアルミニウムを使用する。このア
ルミニウムは第二メッキ層6にスパッタリングにより形
成する。When the second plating layer 6 is made of nickel, for example, aluminum is used for the operating portion 8. This aluminum is formed on the second plating layer 6 by sputtering.
【0021】図5に半導体マイクロリレーの製造方法の
別例を示す。シリコン基板1上に絶縁層(酸化膜)7を
形成した後、第一導電層2をEB蒸着で形成する。第一
導電層2の材料は後述の第一メッキ層4と密着性が確保
できる材料を用いる。次に第一メッキ層4を形成しない
部分に予めレジスト3をスピン塗布により形成する。次
に第一メッキ層4を第二導電層2上の上記レジスト3を
除く部分に形成する。そしてレジスト3をレジスト剥離
液(例えばアセトン)により剥離除去し、それにより表
面に露出する第一導電層2を、硝酸を用いてエッチング
して除去し、ベース電導部20と固定導電部21を形成
する。次に第一レジスト25を、厚みを調整しながらシ
リコン基板1上及び固定導電部21上にスピン塗布によ
り形成する。次に第二レジスト26を第一レジスト25
上に形成する。但しこの第二レジスト26は、固定導電
部21上に載置された第一レジスト25上の所定箇所2
7には、形成されない。次に第二導電層5を第二レジス
ト25上及びベース電導部20上及び所定箇所27にお
ける第一レジスト25上にEB蒸着により形成し、その
後第二メッキ層6を該第二導電層5上に形成する。その
後第一レジスト25及び第二レジスト26をレジスト剥
離液により剥離除去し、空間28を形成する。この空間
28上に梁形状のように形成されている第二導電層5及
び第二メッキ層6が、可動導電部32と成る。そして可
動導電部32上に、可動導電部32を基板1面鉛直方向
に作動させる作動部8を載置する。なお、レジスト剥離
液により第一レジスト25及び第二レジスト26を剥離
除去する工程と、可動導電部32上に作動部8を載置す
る工程は、どちらが先であっても構わない。FIG. 5 shows another example of a method for manufacturing a semiconductor microrelay. After forming the insulating layer (oxide film) 7 on the silicon substrate 1, the first conductive layer 2 is formed by EB evaporation. As a material of the first conductive layer 2, a material that can secure adhesion to a first plating layer 4 described later is used. Next, a resist 3 is previously formed by spin coating on a portion where the first plating layer 4 is not formed. Next, a first plating layer 4 is formed on the second conductive layer 2 except for the resist 3. Then, the resist 3 is stripped and removed with a resist stripping solution (for example, acetone), and thereby the first conductive layer 2 exposed on the surface is removed by etching using nitric acid to form the base conductive portion 20 and the fixed conductive portion 21. I do. Next, the first resist 25 is formed on the silicon substrate 1 and the fixed conductive portion 21 by spin coating while adjusting the thickness. Next, the second resist 26 is replaced with the first resist 25.
Form on top. However, the second resist 26 is located at a predetermined position 2 on the first resist 25 placed on the fixed conductive portion 21.
No. 7 is not formed. Next, the second conductive layer 5 is formed on the second resist 25 and the base conductive portion 20 and on the first resist 25 at a predetermined location 27 by EB evaporation, and then the second plating layer 6 is formed on the second conductive layer 5. Formed. Thereafter, the first resist 25 and the second resist 26 are stripped and removed with a resist stripping solution to form a space 28. The second conductive layer 5 and the second plating layer 6 formed like a beam on the space 28 form the movable conductive portion 32. Then, on the movable conductive part 32, the operating part 8 for operating the movable conductive part 32 in the vertical direction of the substrate 1 is placed. Either of the steps of stripping and removing the first resist 25 and the second resist 26 with the resist stripping solution and the step of placing the operating unit 8 on the movable conductive unit 32 may be performed first.
【0022】ここで所定箇所27には突起部50が形成
される。この突起部50は、作動部8により可動導電部
32が固定導電部21へ撓み接触する可動接点部とな
る。一方この突起部50である可動接点部と接触する固
定導電部上の接触部が固定接点部となる。こうして接点
が突設された半導体マイクロリレーが製造できる。Here, a projection 50 is formed at the predetermined location 27. The protruding portion 50 serves as a movable contact portion where the movable conductive portion 32 flexes and contacts the fixed conductive portion 21 by the operating portion 8. On the other hand, the contact portion on the fixed conductive portion that comes into contact with the movable contact portion, which is the projection 50, becomes the fixed contact portion. In this manner, a semiconductor microrelay having a contact protruding can be manufactured.
【0023】[0023]
【発明の効果】以上説明したように、本発明の半導体マ
イクロリレーによれば、リレーの接点開閉部として働く
固定導電部と可動導電部を半導体基板上にメッキにより
形成した構造を有しているので、従来の如くシリコン基
板のマイクロ加工による構造と比較して構造設計上の制
約を受けることなく且つ比較的簡単な製造工程で製造す
ることができる。As described above, the semiconductor microrelay of the present invention has a structure in which a fixed conductive part and a movable conductive part serving as a contact switching part of a relay are formed on a semiconductor substrate by plating. Therefore, as compared with a conventional structure obtained by micro-processing a silicon substrate, it can be manufactured by a relatively simple manufacturing process without being restricted by a structural design.
【図1】本発明の実施形態に係る半導体マイクロリレー
の第一例の斜視図である。FIG. 1 is a perspective view of a first example of a semiconductor micro relay according to an embodiment of the present invention.
【図2】本発明の実施形態に係る半導体マイクロリレー
の一例を示す製造工程図である。FIG. 2 is a manufacturing process diagram showing an example of a semiconductor micro relay according to an embodiment of the present invention.
【図3】本発明の実施形態に係る半導体マイクロリレー
の第二例の斜視図である。FIG. 3 is a perspective view of a second example of the semiconductor micro relay according to the embodiment of the present invention.
【図4】本発明の実施形態に係る半導体マイクロリレー
の第三例の斜視図である。FIG. 4 is a perspective view of a third example of the semiconductor micro relay according to the embodiment of the present invention.
【図5】本発明の実施形態に係る半導体マイクロリレー
の別例を示す製造工程図である。FIG. 5 is a manufacturing process diagram showing another example of the semiconductor micro relay according to the embodiment of the present invention.
1 半導体基板 7 絶縁膜 21 固定電極部 31 可動電極部 51 支持部 8 作動部 35 圧電素子 36 形状記憶合金 37 薄膜層 20 ベース電導部 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 7 Insulating film 21 Fixed electrode part 31 Movable electrode part 51 Support part 8 Operating part 35 Piezoelectric element 36 Shape memory alloy 37 Thin film layer 20 Base conductive part
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01H 37/52 H01H 37/52 A H01L 41/09 H01L 41/08 U 41/22 41/22 Z ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01H 37/52 H01H 37/52 A H01L 41/09 H01L 41/08 U 41/22 41/22 Z
Claims (7)
絶縁層と、この絶縁層上にメッキにより形成された固定
導電部と、この固定導電部と電気的に分離した状態で間
隔をあけて対向するようメッキにより形成された梁状の
可動導電部と、上記固定導電部よりも上位に立ち上がっ
て上記可動導電部の一部に連結され該可動導電部を上記
基板に対し物理的に支持する支持部と、上記可動導電部
上に形成され該可動導電部の一部を上記固定導電部に電
気的に導通するよう上記半導体基板の基板面の鉛直方向
に撓ませる作動部と、を備えたことを特徴とする半導体
マイクロリレー。1. A semiconductor substrate, an insulating layer formed on the substrate, a fixed conductive portion formed by plating on the insulating layer, and a gap in a state electrically separated from the fixed conductive portion. And a beam-shaped movable conductive portion formed by plating so as to face the upper portion, and rises above the fixed conductive portion and is connected to a part of the movable conductive portion to physically support the movable conductive portion with respect to the substrate. A supporting portion, and an operating portion formed on the movable conductive portion and bending a portion of the movable conductive portion in the vertical direction of the substrate surface of the semiconductor substrate so as to electrically conduct to the fixed conductive portion. A semiconductor micro relay.
だときに上記固定導電部に導通する接点部が突接されて
いることを特徴とする請求項1記載の半導体マイクロリ
レー。2. The semiconductor microrelay according to claim 1, wherein a contact portion that is electrically connected to the fixed conductive portion when the movable conductive portion is bent is in contact with the fixed conductive portion.
とする請求項1又は2記載の半導体マイクロリレー。3. The semiconductor micro-relay according to claim 1, wherein said operating portion is a piezoelectric element.
に上記可動導電部を加熱する加熱手段を備えたことを特
徴とする請求項1又は2記載の半導体マイクロリレー。4. The semiconductor microrelay according to claim 1, wherein said operating portion is made of a shape memory alloy, and further comprising heating means for heating said movable conductive portion.
係数が大きい薄膜層であり、さらに上記可動導電部を加
熱する加熱手段を備えたことを特徴とする請求項1又は
2記載の半導体マイクロリレー。5. The semiconductor according to claim 1, wherein said operating portion is a thin film layer having a larger thermal expansion coefficient than said movable conductive portion, and further comprises heating means for heating said movable conductive portion. Micro relay.
導電部および該固定導電部と電気的に分離したベース電
導部をメッキにて形成する第一のメッキ工程と、上記ベ
ース電導部を除いて固定導電部および該固定導電部と上
記ベース電導部との分離部位にレジストを積載するレジ
スト形成工程と、上記レジスト及びベース電導部の上に
メッキを施すことにより上記レジストを介して上記固定
導電部と対向する可動導電部を形成すると共に上記ベー
ス電導部上にメッキ層を積み上げて上記可動導電部を支
持するための支持部を形成する第二のメッキ工程と、上
記レジストを除去して空隙部を形成する工程と、上記可
動導電部上に該可動導電部を上記固定導電部に向かって
基板面の鉛直方向に撓ませる作動部を積載形成する工程
と、を含むことを特徴とする半導体マイクロリレーの製
造方法。6. A first plating step of forming a fixed conductive portion and a base conductive portion electrically separated from the fixed conductive portion on an insulating layer provided on a semiconductor substrate by plating, and the base conductive portion. Except for the fixed conductive portion and a resist forming step of loading a resist on a separation portion between the fixed conductive portion and the base conductive portion, and by plating the resist and the base conductive portion through the resist, A second plating step of forming a movable conductive portion facing the fixed conductive portion and forming a support portion for supporting the movable conductive portion by stacking a plating layer on the base conductive portion, and removing the resist. Forming a gap portion, and stacking and forming on the movable conductive portion an operating portion for bending the movable conductive portion toward the fixed conductive portion in the vertical direction of the substrate surface. Manufacturing method of semiconductor micro relay.
れたレジスト層の上面には上記可動導電部の接点に相当
する位置に凹所が設けられることを特徴とする請求項6
記載の半導体マイクロリレーの製造方法。7. The resist forming step, wherein a concave portion is provided at a position corresponding to a contact point of the movable conductive portion on an upper surface of the stacked resist layer.
A manufacturing method of the semiconductor microrelay described in the above.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000361975A JP2002170470A (en) | 2000-11-28 | 2000-11-28 | Semiconductor micro relay and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000361975A JP2002170470A (en) | 2000-11-28 | 2000-11-28 | Semiconductor micro relay and manufacturing method thereof |
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|---|---|
| JP2002170470A true JP2002170470A (en) | 2002-06-14 |
Family
ID=18833326
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|---|---|---|---|
| JP2000361975A Pending JP2002170470A (en) | 2000-11-28 | 2000-11-28 | Semiconductor micro relay and manufacturing method thereof |
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