JP2002164788A - Differential output type da converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential output type DA converter which has a wide voltage range with a signal ground as a center and can also output a differential voltage having satisfactory linearity. SOLUTION: A digital signal is decoded by a decoder, and a decode signal is outputted. A current cell array is composed of a constant current source where a current direction is only one direction, and a plurality of current cells having first current paths to be current paths when selected by the decode signal and second current paths to be current paths when unselected are arranged. A current returning circuit generates first and second currents by supplying a sink current or a source current to an added current obtained by adding the currents of a plurality of first current paths and an added current obtained by adding the currents of a plurality of the second current paths, and an IV conversion circuit converts the first and second currents into analog signals of voltage levels corresponding to the first and second currents, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a digital signal,
The present invention relates to a differential output type D / A converter for converting an analog signal of a voltage level corresponding to the input code.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a circuit for obtaining a differential output using a conventional DA converter. A DA converter (hereinafter referred to as DAC) 62 shown in FIG. 1 is a current cell type digital-analog converter for converting a digital signal into an analog signal having a voltage level corresponding to the input code thereof.
Decoder 64, current cell array 66, IV converter 6
8 and an inverting circuit 78.

In the DAC 62 shown in the figure, a decoder 64 first outputs decode signals Sn to S1 corresponding to an input code of a digital signal. This decoded signal Sn
S1 to S1 are signals for controlling the switching elements of the next current cell array 66.

The current cell array 66 has a decode signal Sn
To supply currents corresponding to .about.S1 and is composed of n current cells 70. Each current cell 70 includes a current source 72 and a switch element 74.

In each current cell 70, a current source 72
Supplies a predetermined constant current I, and is connected between the power supply and the switch element 74. Switch element 74
Switches the current I from the current source 72 to either the internal node A or the ground B and supplies it.
It is configured to be connectable between the current source 72 and the internal node A and the ground B, and is connected to either the internal node A or the ground B according to the state of the decode signals Sn to S1.

The IV converter 68 converts the total current supplied from the current cell array 66 into a voltage, and the inverting circuit 78 inverts the output voltage of the IV converter 68 and This is for obtaining a differential output together with the output.

The IV converter 68 includes an operational amplifier OP1 and
And a resistance element R1. The signal ground SG1 is connected to the terminal + of the operational amplifier OP1, and the terminal-
Is connected to the internal node A. The resistance element R1 is
One output signal VoutN, which is connected between the terminal − of the operational amplifier OP1 and the output terminal and forms a differential output voltage, is output from the operational amplifier OP1.

The inverting circuit 78 includes an operational amplifier OP2
And two resistance elements R2. Operational amplifier O
The signal ground SG2 is connected to the terminal + of P2,
The terminal-is connected to an operational amplifier OP via a resistance element R2.
1 output signal VoutN is connected. A resistor R is connected between the terminal-of the operational amplifier OP2 and the output terminal.
2 is connected, and an output signal Vo is output from the operational amplifier OP2.
The other output signal VoutP constituting the differential output voltage, which is obtained by inverting utN, is output.

In the illustrated DAC 62, a predetermined constant current I is supplied from a current source 72 of each current cell 70.
The input code of the digital signal is decoded by the decoder 64, and decoded signals Sn to S1 are obtained. The connection state of switch element 74 of each current cell 70 is determined according to the state of decode signals Sn to S1, and current I supplied from current source 72 changes to the connection state of switch element 74 of each current cell 70. Accordingly, the current flows to either the internal node A side or the ground B side.

All the currents I flowing to the internal node A side are added, and the total current IR1 is converted by an IV converter 68 into an analog signal VoutN of a voltage level corresponding to the input code of the digital signal, and is inverted. At 78, the analog signal VoutN is converted to VoutP which is an inverted version of the analog signal VoutN. For example, assuming that the power supply voltage is Vdd and the signal ground SG1 = SG2 = 1/2 × Vdd, the analog signal is represented as VoutN = − (IR1 × R1). Further, the analog signal VoutP is the signal ground SG.
2 is an inverted signal of the analog signal VoutN centered at 2.

FIG. 8 is a schematic diagram of another example of a conventional DA converter. 7 is different from the DAC 62 shown in FIG. 7 in that each positive side current cell 70 forming the current cell array 66
To each of the negative side current cells 79.
Functions to extract a current from the internal node A to the ground.

Each positive-side current cell 70 has a positive-side current source 72a and a switching element 74a, and each negative-side current cell 79 has a negative-side current source 72b and a switching element 74b.

In each of the current cells 70 and 79, the positive side current source 72a is connected between the power supply and the positive side switch element 74a, and the positive side switch element 74a is connected to the positive side current source 72a. It is configured to be connectable to the internal node A. The negative current source 72b is connected between the ground and the negative switch element 74b. The negative switch element 74b is connected to the negative current source 72b and the internal node A.
It is configured to be connectable between

The positive side switch element 74a of each positive side current cell 70 has a decode signal S
nP to S1P are input, and decode signals SnN to S1N are input from the decoder 64 to the negative switch element 74b of each negative current cell 79. Note that the decode signals SnP to S1P and the decode signals SnN to S1
The switches on both the positive and negative sides are not simultaneously turned on by N, and only one of the positive side current cells 70 and each of the negative side current cells 79 has a current according to the input code of the digital signal. In a flowing state.
Here, P means a positive electrode and N means a negative electrode.

The switch elements 74a and 74b are provided according to the states of the decode signals SnP to S1P and SnN to S1N.
Connected to internal node A or set to open state.

The positive switch element 74a is connected to the internal node A
Is connected to the internal node A, a predetermined constant current Ip is supplied from each positive side current cell 70 via the positive side current source 72a and added. On the other hand, when the negative switch element 74b is connected to the internal node A, a predetermined constant current In is drawn from the internal node A via the negative current sources 72b of the respective negative current cells 79. . The subsequent operation is the same as that of the DAC 62 shown in FIG.

[0017]

The DAC 62 shown in FIG.
Then, for example, the analog signal VoutN outputs only a voltage lower than the signal ground SG1.

On the other hand, there is a method of solving this problem by setting the signal ground SG1 to a voltage higher than, for example, 1/2 × Vdd.

However, for example, when the power supply voltage Vdd is about 3 V and the signal ground SG1 is 2.5 V, the power supply voltage is reduced by 10% to 2.7 V due to the power supply voltage fluctuation.
, Vds (drain-source voltage) of the transistor constituting the current source 72 of the current cell 70 = 2.
7V-2.5V = approximately 200mV, which makes it difficult to operate at a constant current in a saturated state.

At this time, this problem can be avoided by lowering the signal ground SG1, but this will necessarily narrow the differential output voltage range of the analog signals VoutN and VoutP.

On the other hand, in the DAC 80 shown in FIG. 8, when the positive switch element 74a is selected, a voltage lower than the signal ground SG is output to VoutN, and conversely, the negative switch element 74b is selected. Then, a voltage higher than the signal ground SG is output to VoutN.

However, as shown in FIG. 8, a DAC 80 having positive and negative current sources 72a and 72b is
In the case of S, the current source 72a on the positive side is a P-type MOS transistor (PMOS), and the current source 72b on the negative side is an N-type M transistor.
Although it is common to use an OS transistor (NMOS), it is very difficult to match the characteristics of the PMOS and NMOS, that is, the constant current characteristics of the current sources 72a and 72b of the current cell 70. If they do not match, the linearity will be greatly degraded.

Therefore, it is difficult to obtain a wide output range with good linearity of the output differential voltage in both the case of FIG. 7 and the case of FIG.

An object of the present invention is to solve the above-mentioned problems of the prior art, to provide a differential output type DA converter having a wide voltage range centered on a signal ground and capable of outputting a differential voltage with good linearity. Is to provide.

[0025]

In order to achieve the above object, the present invention comprises a decoder for decoding a digital signal and outputting a decoded signal, and a constant current source having only one direction of current, A current cell array in which a plurality of current cells each having a first current path serving as the current path when selected by the decode signal and a second current path serving as the current path when not selected; and a plurality of the first current paths A current return circuit that generates a first current and a second current by supplying a sink current or a source current to an addition current obtained by adding the currents of the first and second current paths and a current obtained by adding the currents of the plurality of second current paths; And an IV conversion circuit for converting an analog signal of a voltage level corresponding to each of the first and second currents into an analog signal. There is provided a A converter.

Here, it is preferable that the source current corresponds to substantially half of the total current flowing through the current cell array, and the sink current substantially corresponds to the total current. Further, the current folding circuit generates the source current by first and second constant current sources connected to a first voltage, and generates third and fourth constant current sources connected to a second voltage. It is preferable to generate the sink current by

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a differential output type DA converter according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a differential output type DA converter according to the present invention. Differential output type D shown in FIG.
An A converter (hereinafter, referred to as DAC) 10 converts a digital signal into two analog signals of a differential output having a voltage level corresponding to an input code of the digital signal.
An analog converter, basically comprising a decoder 12;
Current cell array 14, current folding circuit 16, IV
And a conversion circuit 18.

In the illustrated DAC 10, first, the decoder 12 decodes a digital signal and outputs a decoded signal corresponding to the input code. In the case of the illustrated example, the decoder 12 includes two-bit digital signals D1 and D2.
0, and decode signals S3N to S0N and S3P to S0P corresponding to the input code are output. These decode signals S3N to S0N and decode signal S3P
ＳS0P are exclusive signals.

Subsequently, the current corresponding to the decode signal input from the decoder 12 is supplied to the first current cell array 14.
And the currents are added to the second internal nodes P1 and N1, respectively, and these currents are added. In the illustrated example, four current cells 20 are provided. Each current cell 20
P-type MOS transistor serving as a current source (hereinafter referred to as PMOS
22) and two PMOSs 2 serving as switch circuits.
4, 26.

In each current cell 20, PMOS2
2 has a source connected to the power supply and a drain connected to the PMOS.
24 and 26, and the drains of the PMOSs 24 and 26 are connected to internal nodes P1 and N1, respectively, which are first and second internal nodes. The current is added.
The gate of the PMOS 22 is commonly connected to the bias voltage VB1, and the gates of the PMOSs 24 and 26 are supplied with decode signals S3N to S0N and S3P to S0P, respectively.

The PMOS2 of the current source of each current cell 20
2 constitutes a current mirror circuit. Therefore, in the present embodiment, a substantially constant current a is supplied from the power supply to the internal nodes P1 and N1 via the respective current cells 20 in accordance with the voltage level of the bias voltage VB1. In the present invention, the sum of the currents supplied from all the current cells 20 constituting the current cell array 14 is referred to as a total current. In the case of the present embodiment, the total current is 4a.

The PMOSs 24, 26 of the switch circuit
Are the decode signals S3N to S0N and S3P to S0P
, One of them turns on and the other turns off. Here, when the PMOS 24 is turned on, the PM
The current a is supplied to the internal node P1 via the OS 24,
Is added. Similarly, when the PMOS 26 is turned on, the current a is supplied from the current source 22 to the internal node N1 via the PMOS 26, and is added.

The current folding circuit 16 supplies a source current corresponding to half of the total current from the power supply to the internal nodes P1 and N1.
And a sink current corresponding to the total current is drawn from the internal nodes P1 and N1 to the ground, and a current corresponding to half of the total current is supplied from the power supply to the internal node P1.
1 and N1, and a ground-side current source 30 that draws a current corresponding to the total current from the internal nodes P1 and N1 to the ground.

The current source 28 on the power supply side includes two PMOS3
2, 34. These PMOSs 32 and 34 are respectively connected between the power supply and the internal nodes P1 and N1, and the gates thereof are commonly connected to the bias voltage VB1.

The PMOSs 32 and 34 of the current source 28 on the power supply side
Constitutes a current mirror circuit together with the PMOS 22 of the current source of the current cell array 14. In the present embodiment, a substantially equal constant source current 2a corresponding to half of the total current of the current cell array 14 is supplied from the power supply via the PMOSs 32 and 34.

On the other hand, the ground side current source 30 has two N
Type MOS transistor (hereinafter referred to as NMOS) 36,
38. The NMOSs 36 and 38 are connected between the internal nodes P1 and N1 and the ground, respectively, and the gates thereof are commonly connected to the bias voltage VB2.

The NMOS 36 of the current source 30 on the ground side
38 constitutes a current mirror circuit. In this embodiment,
From each of the internal nodes P1 and N1, the NMOS 36,
A substantially equal constant sink current 4a corresponding to the total current of the current cell array 14 is drawn to the ground via 38.

A current corresponding to the input code of the digital signal is supplied from the current cell array 14 to the internal nodes P1 and N1. Then, by the current turning circuit 16,
A current 2a corresponding to half of the total current of the current cell array 14 is supplied from the power supply to the internal nodes P1 and N1,
A current 4a corresponding to the total current of the current cell array 14 is drawn from the internal nodes P1 and N1 to the ground. That is, in the current folding circuit 16, the current 2 corresponding to half of the total current of the current cell array 14 is calculated based on the current of the current cell array 14 supplied to the internal nodes P1 and N1.
a is extracted, and this current becomes the output currents IP and IN of the current turning circuit 16 and is input to the IV conversion circuit 18.

Lastly, the IV conversion circuit 18 converts the current output from the current return circuit 16 into two analog signals having voltage levels corresponding to the current. Current IP,
IN is set to an analog signal Vo of a voltage level corresponding to IN.
two IV converters 40 for converting the signals into outP and VoutN,
42 are provided.

Here, the IV converter 40 includes an operational amplifier O
P1 and a resistance element RFB1 are provided. The signal ground SG is connected to the terminal + of the operational amplifier OP1 of the IV converter 40, and the internal node P1 is connected to the terminal-. The resistance element RFB1 is connected between the terminal − of the operational amplifier OP1 and the output terminal, and the operational amplifier OP1 outputs an output voltage VoutP.

Similarly, the IV converter 42 includes an operational amplifier O
P2 and a resistance element RFB2. The signal ground SG is connected to the terminal + of the operational amplifier OP2 of the IV converter 42, and the internal node N1 is connected to the terminal-. The resistance element RFB2 is connected between the terminal-of the operational amplifier OP2 and the output terminal, and the operational amplifier OP2 outputs the output voltage VoutN.

In this embodiment, the resistance elements RFB1,
The resistance values of RFB2 are equal and are expressed as resistance value R. The potentials of the terminals-of the operational amplifiers OP1 and OP2 are virtually grounded to the signal ground SG, and the currents IP and IN output from the current return circuit 16 pass through the nodes of the terminals-of the operational amplifiers OP1 and OP2 and are connected to the resistance element. It flows to RFB1 and RFB2. Therefore, the output voltages VoutP, VoutN of these IV converters 40, 42 are
Since RFB1 = RFB2 = R, VoutP = −
(IP × RFB1) = − (IP × R) [V0p: zero peak voltage], VoutN = − (IN × RFB2) = −
(IN × R) [V0p] and signal ground SG
And a differential voltage output centered at

Next, referring to Table 1 shown in FIG.
The operation of AC10 will be described.

In the illustrated DAC 10, first, the decoder 12 decodes the 2-bit digital signals D1 and D0, and outputs the decoded signal S3 corresponding to the input code.
N to S0N and S3P to S0P are input to the current cell array 14.

Subsequently, in the current cell array 14, the decode signals S3N to S0N, S
Currents corresponding to 3P to S0P are supplied to internal nodes P1 and N1, respectively.

Further, a current 2a corresponding to half of the total current is supplied from a power supply to each of internal nodes P1 and N1 by current folding circuit 16, and internal node P1
A current 4a corresponding to the total current is drawn from 1, N1 to the ground. That is, the internal nodes P1, N1
Is extracted from the current supplied to the current cell array 14 by 2a corresponding to half of the total current of the current cell array 14, and this current is output from the current return circuit 16 by the output current IP,
IN.

Then, the output currents IP and IN of the current folding circuit 16 are converted by the IV conversion circuit 18 into analog signals VoutP and Vout, which are differential voltage outputs corresponding thereto.
Converted to tN.

As shown in Table 1 of FIG. 2, for example, when the digital signals D1 and D0 = 0 and 1, the decode signals S3N to
S0N = 1,0,0,0, decode signals S3P to S0P
= 0, 1, 1, 1 and 3 of the four current cells 20
The PMOS 24 of one current cell 20 is turned on, the PMOS 26 of one current cell 20 is turned on, and the current cell array 14
From the internal node P1 via the PMOS 24 to the current 3a
However, the current a is supplied to the internal node N1 via the PMOS 26.

A current 2a corresponding to half of the total current is supplied from the power supply to each of internal nodes P1 and N1 by current folding circuit 16, and internal node P1
A current 4a corresponding to the total current is drawn from 1, N1 to the ground. That is, the internal nodes P1, N1
Is extracted from the current supplied to the current cell array 14 by 2a corresponding to half of the total current of the current cell array 14, and this current is output from the current return circuit 16 by the output current IP,
IN. As a result, the output currents IP and IN of the current folding circuit 16 are respectively IP = 3a + 2a-4a =
a, IN = a + 2a-4a = -a.

The output currents IP and IN of the current folding circuit 16 are input to an IV conversion circuit 18 where R = RF
Assuming that B1 = RFB2, the analog signal VoutP = −
(IP × R) = − (a × R) = − a × R [V0p: zero peak voltage], analog signal VoutN = − (IN ×
R) = − (− a × R) = a × R [V0p], which is converted into a differential voltage centered on the signal ground SG.

The same operation is performed when the digital signals D1, D0 = 1, 0 and 1, 1. Note that the DAC of the present invention is configured to output a differential voltage, and to output differential voltages VoutP, VoutP,
It is assumed that VoutN is 0 [V0p], that is, bipolar zero BPZ, and digital signals D1 and D0 =
The case of 0,0 shall be excluded.

In the DAC 10 shown in the drawing, an operation equivalent to reducing the current corresponding to half of the total current with respect to the current supplied from each current cell array 20 to the internal nodes P1 and N1 by the current folding circuit 16 is performed. The current cell 20 constituting the current cell array 14 may be, for example, only a current source having a current in only one positive side, which supplies a current from a power supply, as in the case of the DAC 80 shown in FIG. Since a negative current source for drawing a current to the ground is not required, the configuration can be simplified.

In the DAC 10, the current cell array 1
4 and the current sources 28 and 30 of the current folding circuit 16 are both in a range where the current mirror operation can be performed, and the IV conversion circuit 1
There is also an advantage that the power supply voltage can be lowered within a range where the eight operational amplifiers OP1 and OP2 can operate.

In the DAC 10, the analog signal Vo
The output voltage range of utP and VoutN is IV conversion circuit 1.
8 is determined by the output voltage ranges of the resistance elements RFB1 and RFB2 and the operational amplifiers OP1 and OP2 used in FIG. 8, and a wide output voltage range can be obtained by appropriately changing these.

Next, a differential output DA converter according to the present invention will be described with reference to another embodiment shown in FIG.

FIG. 3 is a schematic diagram showing the configuration of another embodiment of the differential output type DA converter according to the present invention. DAC 44 shown in FIG.
Is the current cell array 1 in the DAC 10 shown in FIG.
4 which is a current source of each current cell 20 constituting
2, and a cascode connection of a current source 28 on the power supply side and a current source 30 on the ground side that constitute the current folding circuit 16.

That is, the current source of each current cell 20 of the current cell array 14 is further provided between the drain of the PMOS 22 of the current source and the sources of the PMOSs 24 and 26 of the switching elements, as compared with the case of the DAC 10 shown in FIG. A connected PMOS 46 is provided.

The current source 28 on the power supply side of the current folding circuit 16 further includes PMOSs 32 and 34 and internal nodes P1 and P2, respectively, as compared with the case of the DAC 10 shown in FIG.
There are provided two PMOSs 48 and 50 connected between N1 and N1. The PMOS 46 of the current cell array 14
The bias voltage VB3 is commonly connected to the gates of the PMOSs 48 and 50 of the current folding circuit 16, and these PMOSs 46, 48 and 50 constitute a current mirror circuit.

Similarly, the current source 30 on the ground side of the current folding circuit 16 further includes NMOSs 36 and 38 and internal nodes P1 and N1 as compared with the DAC 10 shown in FIG.
And two NMOSs 52 and 54 connected between them. The gates of these NMOSs 52 and 54 are commonly connected to a bias voltage VB4 to form a current mirror circuit.

In the DAC 10 shown in FIG.
1, N1 are operational amplifiers OP1, OP2 of the IV converter 18
, The internal nodes P1 and N1 are fixed to the potential of the signal ground SG by the virtual ground. Therefore, Vds (drain-source voltage) of the current sources 28 and 30 on the power supply side and the ground side of the current turning-back circuit 16 are, respectively, the power supply voltage Vdd-the signal ground voltage SG, the signal ground voltage SG-the ground voltage Vss. Become.

On the other hand, in the example shown in FIG.
52, 54 are PMOS 32, 34, NMOS 36, 38
And a cascode configuration, it is possible to suppress the Early effect of the transistors of these constant current sources and improve the constant current characteristics.

Next, a differential output DA converter according to the present invention will be described with reference to another embodiment shown in FIG.

FIG. 4 is a schematic diagram showing the configuration of another embodiment of the differential output type DA converter according to the present invention. DAC 56 shown in FIG.
Indicates that the digital signal of the DAC 44 shown in FIG.
Bit, that is, the current cell array 14 has 256
The current cell 20 is provided. The other configuration is the same as that of the DAC 44 shown in FIG.

In this case, the total current of the current cell array 14 is 256a, and a current of 128a corresponding to half of the total current is supplied from the current source 28 on the power supply side of the current folding circuit 16 and the current source 30 on the ground side. , A current of 256a corresponding to the total current is extracted.

As shown in Table 2 of FIG. 5, when the digital signal is 8 bits, the current I flowing through the IV converters 40 and 42
P and IN are values of 255 steps from -127a to 127a with 0 being the center. In Table 2, FS
Represents full scale, BPZ represents bipolar zero, and V0p represents zero peak voltage. Assuming that R = RFB1 = RFB2, the analog signal VoutP = − (IP × R) [V0
p], VoutN = − (IN × R) [V0p],
A differential output voltage corresponding to the currents IP and IN and centering on the signal ground SG is obtained.

As in this example, the differential output type DA of the present invention is used.
In the converter, the number of bits of the digital signal, that is, the number of current cells in the current cell array is not limited at all.

Next, a differential output DA converter according to the present invention will be described with reference to another embodiment shown in FIG.

FIG. 6 is a conceptual diagram showing the configuration of an embodiment of the differential output type DA converter according to the present invention. DAC 58 shown in FIG.
Is divided into two parts, one for the upper bit and the other for the lower bit, which operate in response to the upper and lower bits of the digital signal, respectively. The decoder 12, the upper current cell array 14a and the current folding circuit 1
6a, a lower-order current cell array 14b, a current folding circuit 16b, and an IV conversion circuit 18.

The digital signal is input to the decoder 12,
The upper and lower decoded signals obtained by decoding the upper and lower bits of the digital signal are output from the decoder 12 to the upper and lower current cell arrays 1.
4a and 14b.

The upper current cell array 14a supplies a current corresponding to the upper decode signal to the internal nodes P1 and N1, and the lower current cell array 14b supplies the current to the internal nodes P2 and N2. A current corresponding to the lower decode signal is supplied.

Further, a current corresponding to half of the total current of upper current cell array 14a is supplied from power supply to internal nodes P1 and N1, and a current corresponding to the total current is supplied to internal node P1,
The current is pulled out from N1 to the ground, and the output currents of the higher-order current turning-back circuit 16a become IP1 and IN1. Similarly, a current corresponding to half of the total current of lower current cell array 14b is supplied from power supply to internal nodes P2 and N2 by lower current folding circuit 16b, and a current corresponding to the total current is generated by internal nodes P2 and N2. To the ground, and the output currents of the lower current return circuit 16b become IP2 and IN2.

Then, the output currents IP1 and IN1 of the higher-order current return circuit 16a and the lower-order current return circuit 16a
The output currents IP2 and IN2 of b are input to the IV converters 40 and 42 of the IV conversion circuit 18, respectively, and are converted into analog signals VoutP and VoutN. However, the IV converters 40 and 42 have the same feedback resistance RFB.

As in this example, the DAC 58 of the present invention uses the current cell array 1 according to the bit of the digital signal.
4 and a plurality of the current folding circuits 16 may be provided.

Further, when the output signal band of the DAC is a low-frequency signal band, for the purpose of achieving higher precision,
It is also possible to incorporate element matching technology into the current cell array. The element matching technique itself is described in, for example, US Pat. No. 4,935,740.

In the embodiment of the present invention, the sink current and the source current are set to the total current and half of the total current, but these values are not limited and can be set arbitrarily.

The differential output voltage of the differential output type DA converter of the present invention is the same as a known differential voltage. That is, the voltage of the differential output terminal VoutP and V
When the voltage of outN is the same as the ground potential (ground GND) or the signal ground SG, the voltage becomes the in-phase voltage. Further, a potential difference between both output terminals of VoutP and VoutN becomes a differential voltage.

The differential output DA converter of the present invention is basically as described above. As described above, the differential output type DA converter of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0079]

As described in detail above, the differential output type DA converter according to the present invention is constituted by a constant current source having only one direction of current, and serves as a current path when selected by a decode signal. Using a current cell array in which a plurality of current cells each having a first current path and a second current path serving as a current path when not selected are arranged, and using a current folding circuit, an added current obtained by adding the currents of the plurality of first current paths is provided. Multiple second
A first current and a second current are generated by supplying a sink current or a source current to the addition current obtained by adding the currents of the current paths, and the IV conversion circuit corresponds to the first and second currents, respectively. In this case, the signal is converted into an analog signal having the following voltage level. Thus, according to the differential output type DA converter of the present invention, the current cell array needs only a current source in only one direction, and can be simply configured. According to the differential output type DA converter of the present invention, the current mirror of the current source of the current cell and the current source of the current folding circuit can both perform the current mirror operation.
In addition, there is an advantage that the power supply voltage can be reduced as long as the operational amplifier of the IV conversion circuit can operate. Further, according to the differential output type DA converter of the present invention, I
By appropriately adjusting the V conversion circuit, a wide output voltage range can be obtained as an analog signal.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a differential output type DA converter according to the present invention.

FIG. 2 is a table of an embodiment showing an operation of the differential output type DA converter shown in FIG. 1;

FIG. 3 is a configuration circuit diagram of another embodiment of the differential output type DA converter of the present invention.

FIG. 4 is a configuration circuit diagram of another embodiment of the differential output type DA converter of the present invention.

FIG. 5 is a table of an example showing an operation of the differential output type DA converter shown in FIG. 4;

FIG. 6 is a conceptual diagram illustrating a configuration of a differential output DA converter according to an embodiment of the present invention.

FIG. 7 is an example of a circuit for obtaining a differential output using a conventional DA converter.

FIG. 8 is a schematic diagram showing the configuration of another example of a conventional DA converter.

[Explanation of symbols]

10, 44, 56, 58, 60, 62, 80 DA converter (DAC) 12, 64 decoder 14, 14a, 14b, 66 Current cell array 16, 16a, 16b Current folding circuit 18 IV conversion circuit 20, 66, 70, 79 Current cell 22, 24, 26, 32, 34, 46, 48, 50 P
MOS transistors (PMOS) 28, 30, 72, 72a, 72b Current sources 36, 38, 52, 54 N-type MOS transistors (N
MOS) 40, 42, 68 IV converter 74, 74a, 74b Switch element 78 Inverting circuit OP1, OP2 Operational amplifier RFB1, RFB2, R1, R2 Resistance element C Capacitance element D1, D0 Digital signal S3N to S0N, S3P to S0P Decode signal P1, P2, N1, N2 Internal nodes VoutP, VoutN Analog signal VB1, VB2, VB3, VB4 Bias voltage SG, SG1, SG2 Signal ground

Claims (3)

[Claims] 1. A first current path, comprising: a decoder for decoding a digital signal and outputting a decode signal; and a constant current source having a current flowing in only one direction, the first current path being a current path when selected by the decode signal. And a current cell array in which a plurality of current cells each having a second current path serving as the current path when not selected, an addition current obtained by adding a plurality of currents in the first current path, and a plurality of the second current paths A current folding circuit that generates a first current and a second current by supplying a sink current or a source current to the added current obtained by adding the currents; and a voltage level corresponding to each of the first and second currents. And a IV conversion circuit for converting the analog signal into an analog signal. 2. The differential according to claim 1, wherein said source current corresponds to substantially half of a total current flowing through said current cell array, and said sink current substantially corresponds to said total current. Output type DA converter. 3. The current folding circuit generates the source current by first and second constant current sources connected to a first voltage, and generates third and fourth currents connected to a second voltage. The differential output type DA converter according to claim 1, wherein the sink current is generated by a constant current source.