JP2002159198A - Inverter device - Google Patents

Abstract

(57) [Problem] To provide an inverter device capable of decelerating and stopping a motor regardless of an operation state when a power failure occurs. A voltage detector for detecting a DC bus voltage.
And an inverter unit 34 composed of a transistor and a diode, which converts DC power into variable frequency and variable voltage AC power, calculates an output frequency and an output voltage based on the input frequency setting, and A control unit 1a for outputting a transistor control signal for turning on / off a transistor, a storage unit 4a for storing a phase coefficient α1 by which an output frequency is multiplied, wherein the control unit 1a To
The output frequency at the time when the power failure occurs is multiplied by the phase coefficient α1 to calculate the output frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device for driving and controlling a motor, and more particularly to an inverter device capable of extending a maintenance period of a control power supply when a power failure occurs.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing a configuration of a conventional inverter device. In the figure, 31 is a three-phase AC power supply, 32
Is a three-phase AC power supply
A converter unit for converting the three-phase AC power supplied from 1 into DC power, a smoothing capacitor 33 for smoothing the DC voltage converted by the converter unit 32, and a smoothing capacitor 33 composed of a transistor and a diode. An inverter 35 for converting a DC voltage into a variable frequency, variable voltage AC power is a motor such as an induction motor driven and controlled by the AC power output from the inverter 34. Reference numeral 36 denotes a voltage detector for detecting a DC bus voltage.

A control unit 37 controls on / off of a transistor of the inverter unit 34. Control unit 37
Outputs a transistor control signal 40 to the inverter unit 34 so that the output average voltage becomes a sine wave by the high carrier frequency sine PWM control, makes the switching pulse width for turning on / off the transistor variable, and sets an arbitrary frequency and voltage. Is output. An acceleration / deceleration time setting unit 38 sets an acceleration / deceleration time based on a frequency setting as an input speed command and a preset basic acceleration time and basic deceleration time. The reference numeral 39 denotes an output frequency and an output voltage based on a preset V / F pattern and an acceleration / deceleration time set by the acceleration / deceleration time setting unit 38, thereby turning on / off the transistor of the inverter unit 34. A V / F control unit that outputs a transistor control signal 40 to be turned on.

FIG. 11 is a diagram showing the relationship between voltage and voltage phase angle. FIG. 12 is a diagram showing a flowchart for calculating the output voltage phase angle in the control unit in the conventional inverter device. In the figure, ω is an angular velocity, Δt is an interrupt time which is a control cycle, θ is a voltage phase angle, Δ
θ is a voltage phase lead angle.

The operation of voltage control in a conventional inverter device will be described with reference to FIGS. The control unit calculates the voltage phase angle θ by an interrupt process for each interrupt time Δt that is a control cycle. In step S20, the voltage phase angle θ advanced between the previous interrupt time and the current interrupt time is calculated as the voltage phase advance angle Δθ. Δθ = ω * Δt (1) In step S21, the voltage phase angle θ at the current interrupt time is calculated by adding the voltage phase advance angle Δθ to the voltage phase angle θ at the previous interrupt time. θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage phase angle θ at the current interrupt time is output.

In the conventional inverter device, the current voltage phase angle θ is calculated by adding the current voltage phase lead angle Δθ to the previous voltage phase angle θ at every interrupt time Δt interval. And interrupt time Δ
If t is constant, the current voltage phase lead angle Δθ is constant, so that the voltage phase angle θ can be advanced at regular intervals as shown in FIG.

FIG. 13 shows a conventional inverter device.
FIG. 7A is a diagram showing an electric deceleration operation, in which FIG.
Voltage V_AC, (B) shows the DC bus voltage V_PN, (C) is the output cycle
The wave number fo, (d) is the motor rotation speed N. Figure smell
A is the inverter input voltage V _ACIs no longer supplied
At this point, B has fallen below the lower limit voltage at which the control power can be maintained.
At this point, C indicates the output frequency when the control power is maintained.
This is the point in time when deceleration stop control is performed on the number fo to 0 Hz. Input power
Pressure V_ACIs normal, the DC bus voltage V_PNIs 300V
And the output frequency fo and the motor speed N are also
Controlled as instructed. However, a power outage occurred,
Inverter input voltage V_ACIs no longer available
Is the DC bus voltage V_PNThe control power supply lower limit voltage drops
Then, the motor stops in the free run.

Further, in the case of a power failure in which power is not supplied to the inverter device, the DC bus voltage is maintained by utilizing the regenerative energy from the motor so that the motor is free even if a power failure occurs. There is a power failure deceleration stop function that safely decelerates and stops the motor without running. However, if the regenerative energy from the motor is not sufficient, such as during a power running load, the regenerative energy from the motor cannot be used even if there is a power failure deceleration stop function. _VPN falls below the control power supply maintenance lower limit voltage.

FIG. 14 shows, for example, Japanese Patent Application Laid-Open No. H6-165582.
FIG. 1 is a diagram showing a schematic configuration of a main circuit of a conventional inverter device disclosed in Japanese Patent Laid-Open Publication No. H10-15095. This conventional inverter device switches the inverter output arm to the reflux state and stops the integration of the voltage phase at the same time when it becomes necessary to stop the induction motor rotating at high speed in an emergency, thereby reducing the magnetic flux inside the induction motor. The deceleration torque can be increased steeply while keeping it constant, and the inverter continuously flows the limit current that does not cause overcurrent, thereby maximizing the primary copper loss and secondary copper loss of the induction motor. As a result, the rotational energy can be effectively consumed, and a large deceleration torque can be generated.

In FIG. 1, reference numeral 51 denotes a positive DC bus P, 52 denotes a negative DC bus N, and 53 denotes a main circuit capacitor disposed between the DC buses PN and holding a voltage between the DC buses PN. 54 is a U-phase positive side main switching element, 55 is a U-phase negative side main switching element, 56 is a V-phase positive side main switching element, 57 is a V-phase negative side main switching element, and 58 is a W-phase positive side main switching element. The element 59 is a W-phase negative side main switching element. U-phase positive-side main switching element 54 and U-phase negative-side main switching element 55, V-phase positive-side main switching element 56 and V-phase negative-side main switching element 57, W-phase positive-side main switching element 58 and W-phase negative-side main switching element The switching elements 59 operate complementarily, and when one is on, the other is off.

Reference numeral 60 denotes an induction motor. 61 detects each phase current of the motor current flowing to the output side of the inverter, that is, the induction motor 60, in two or three phases, extracts the one having the largest absolute value among them, and outputs this as a current detection value I. Is an absolute value rectifier circuit. Reference numeral 62 compares the current limit level Oc with the current detection value I. If the current detection value I does not exceed the current limit level Oc, the current reduction signal S1
Is a comparator that outputs. The current limit level Oc is set to a value somewhat lower than the overcurrent protection level of the inverter. Reference numeral 63 denotes a DC bus voltage detector that outputs a DC bus voltage detection value Vdc. A comparator 64 compares the DC bus voltage detection value Vdc with the DC bus voltage limit level Ov, and outputs a voltage drop signal S2 when the DC bus voltage detection value Vdc does not exceed the DC bus voltage limit level Ov. . Reference numeral 65 denotes an AND circuit that outputs a reflux state switching signal S3 when both the current decrease signal S1 and the voltage decrease signal S2 are output.

Reference numeral 66 denotes a control circuit. Control circuit 6
6 is PW when the return state switching signal S3 is not input.
An M signal is generated to switch the main circuit switching elements 54 to 59
Is driving. When the reflux state switching signal S3 is input, of the main circuit switching elements 54 to 59, the positive U-phase positive main switching element 54, the V-phase positive main switching element 56, and the W-phase positive main switching element 58 Is turned on, the U-phase negative-side main switching element 55, the V-phase negative-side main switching element 57, and the W-phase negative-side main switching element 59 are turned off to short-circuit the terminals of the induction motor 60, and at the same time a PWM signal is generated. To stop the progress of the phase angle. Thereby, the induction motor 60 has zero frequency and
The state becomes zero voltage, and a deceleration torque is rapidly generated.

The conventional inverter device shown in FIG.
When it is necessary to stop the induction motor 60 during high-speed rotation, the detected current value I output from the absolute value rectifier circuit 61 does not exceed the current limit level Oc, and the output of the DC bus voltage detector 63 If the DC bus voltage limit level Ov is not exceeded, the inverter output arm is switched to the reflux state and the integration of the voltage phase is stopped at the same time. Therefore, the deceleration torque can be sharply increased while keeping the magnetic flux inside the induction motor 60 constant, and the inverter can continue to stably flow the limit current that does not cause overcurrent.

The conventional inverter device shown in FIG.
When an emergency stop of the induction motor during high-speed rotation is required, the purpose is to quickly decelerate and stop the induction motor without using a power regeneration function or a circuit to discharge the charge of the capacitor. When the bus voltage is not excessive and the motor current is not excessive, the inverter output is returned to a reflux state, and the PWM waveform control is stopped at that point, so that the deceleration torque is sharply maintained while keeping the magnetic flux inside the induction motor constant. Can be increased.

[0015]

In the conventional inverter device shown in FIGS. 10 to 13 [0005], when a power failure occurs, the DC bus voltage V _PN is control power maintenance lower limit voltage of the inverter prior to decelerate and stop the motor It becomes as follows (Fig. 1
3B), there is a problem that the motor coasts. In addition, the conventional inverter device shown in FIG.
_PN is raised, but when the power supply voltage is normal, it becomes necessary to stop the induction motor urgently,
The inverter can efficiently use regenerative energy by continuously flowing a limit current that does not cause overcurrent,
Since the deceleration torque is sharply increased, there is a problem that the control power cannot always be maintained when a power failure occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide an inverter device capable of decelerating and stopping a motor regardless of an operation state when a power failure occurs. .

[0017]

A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, An inverter unit composed of a transistor and a diode that converts DC power into variable frequency and variable voltage AC power, and calculates an output frequency and an output voltage based on the input frequency setting, and turns on the transistor in the inverter unit. A control unit for outputting a transistor control signal for turning on / off, a storage unit for storing a phase coefficient by which an output frequency is multiplied, wherein the control unit has a power failure when a power failure occurs The output frequency is calculated by multiplying the output frequency at the time by the phase coefficient.

The storage unit stores the number of output frequency reduction processes for forcibly reducing the output frequency, and when a power failure occurs, the control unit stores the phase coefficient in the output frequency at the time of the power failure. The multiplication process is performed by the number of times of the output frequency reduction process.

A phase coefficient stored in the storage unit;
The number of times of the output frequency reduction processing can be set as a parameter from the outside.

A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, a transistor and a diode. An inverter configured to convert DC power into AC power having a variable frequency and a variable voltage, and a transistor for calculating an output frequency and an output voltage based on an input frequency setting and for turning on / off a transistor of the inverter. And a control unit that outputs a control signal.
A storage unit for storing a phase coefficient of the output frequency, a first number of output frequency reduction processes for forcibly reducing the output frequency, a second number of output frequency reduction processes, and a DC bus voltage check value for determining whether control power can be maintained. The control unit, when a power failure occurs, calculates the output frequency by multiplying the output frequency at the time of the power failure by the first phase coefficient, and the DC bus voltage at the time of the power failure is the DC When the DC bus voltage becomes equal to or less than the DC bus voltage check value, the output frequency at the time when the DC bus voltage becomes equal to or less than the DC bus voltage check value is multiplied by the second phase coefficient to calculate the output frequency. .

Further, the storage unit stores a first output frequency reduction process number and a second output frequency reduction process frequency for forcibly reducing the output frequency, and the control unit, when a power failure occurs, A process of calculating the output frequency by multiplying the output frequency at the time of occurrence of the first phase coefficient by the first phase coefficient the number of times of the first output frequency reduction process, and the DC bus voltage at the time of the power failure is the DC bus voltage When the DC bus voltage becomes equal to or less than the check value, the output frequency at the time when the DC bus voltage becomes equal to or less than the DC bus voltage check value is multiplied by the second phase coefficient to calculate the output frequency. This is performed only for the number of reduction processes.

Further, the first phase coefficient and the second phase coefficient, the first number of output frequency reduction processes, the second number of output frequency reduction processes, and the DC bus voltage check value stored in the storage unit are externally input. It is a parameter that can be set.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a diagram showing a configuration of the inverter device according to Embodiment 1 of the present invention. In the figure, reference numerals 31 to 36, 38, 39, and 40 are the same as those in FIG. 10 as a conventional example, and a description thereof will be omitted.
1a turns on / off the transistor of the inverter unit 34;
The control unit 2 for turning off the power is a power failure detection unit that detects a power failure. Further, 3a calculates an output frequency and an output voltage based on a preset V / F pattern and an acceleration / deceleration time set by the acceleration / deceleration time setting unit 38, and turns on / off the transistor of the inverter unit 34. A V / F control unit 4a that outputs a transistor control signal 40 to perform a phase coefficient α1 (100%> α1 ≧ 1%) and a storage number n1 (n1 ≧ 1) for forcibly reducing the output frequency. Department. When a power failure occurs and the inverter input voltage _VAC is no longer supplied, the V / F control unit 3a controls the output frequency to extend the control power supply maintenance time after the power failure.

FIG. 2 is a diagram showing control of the output frequency when a power failure occurs in the control unit 1a of the inverter device according to Embodiment 1 of the present invention. In the figure, fo is the output frequency, fo1 is the output frequency when a power failure occurs, α1 is the phase coefficient (100%> α ≧ 1%), Δt is the interrupt time as a control cycle, and n1 is the output frequency fo1 × α1.
(N1 ≧ 1). When a power failure occurs, the output frequency is set to fo1 × α1 for Δt × n1 time.

FIG. 3 is a diagram showing the relationship between the voltage and the voltage phase angle in the inverter device according to the first embodiment of the present invention. In the figure, ω is an angular velocity, Δt is an interrupt time as a control cycle, θ is a voltage phase angle, Δθ is a voltage phase advance angle, and α1 is a phase coefficient (100%> α ≧ 1%). When a power failure occurs, the voltage phase lead angle Δθ is set to Δθ × α1 for Δt × n1 time (in the figure, n1 = 1 and the output frequency is changed to fo1 × α1 for one interrupt time Δt). Examples were shown). Equation (1) can be replaced with equation (3) for the voltage phase lead angle Δθ. Δθ = ω * Δt Equation (1) Δθ = 2πf * Δt Equation (3) Multiplying the output frequency fo1 by the phase coefficient α1 is equivalent to multiplying the voltage phase lead angle Δθ by the phase coefficient α1.

FIG. 4 shows a control section of the inverter device according to Embodiment 1 of the present invention, in which the inverter input voltage V _AC
FIG. 7 is a diagram showing a flowchart for calculating an output voltage phase angle at the time when the supply of the output voltage is stopped.

FIGS. 5A and 5B are diagrams showing a power failure deceleration operation in the inverter device according to the first embodiment of the present invention. FIG. 5A shows the input voltage V _AC of the inverter device, FIG. 5B shows the DC bus voltage V _PN , and FIG. ) Is the output frequency fo, and (d) is the motor speed N. In the figure, A is the point when the inverter input voltage _VAC is no longer supplied.

In FIG. 5B, B1 is a phase coefficient α1.
Is set to a small value and the rise of the DC bus voltage V _PN is increased, and B2 is a curve when the phase coefficient α1 is set to a large value and the rise of the DC bus voltage V _PN is reduced. is there. Further, by increasing the output frequency reduction processing number n1 of the output frequency and fo1 × [alpha] 1, it is possible to increase the rise of the DC bus voltage V _PN. When the rise of the DC bus voltage V _PN is small, as shown by the curve B2, before the motor is decelerated and stopped, the DC bus voltage V _PN becomes equal to or lower than the control power supply lower limit lower voltage, and the motor runs free. The phase coefficient α1 and the output frequency are fo1 ×
It is necessary to set the number of output frequency reduction processes n1 to be α1 according to the operation specifications.

The power-supply deceleration operation of the inverter device according to the first embodiment will be described with reference to FIGS. The controller 1a calculates the voltage phase angle θ by an interrupt process for each interrupt time Δt that is a control cycle.

In step S20, the voltage phase angle θ advanced from the previous interrupt time to the current interrupt time is calculated as the voltage phase advance angle Δθ. Δθ = ω * Δt (1)

In step S1, it is determined whether the power supply voltage is normal or a power failure occurs. If the power supply voltage is normal, in step S21,
The voltage phase angle θ at the current interrupt time is calculated by adding the voltage phase lead angle Δθ to the voltage phase angle θ at the previous interrupt time. θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage phase angle θ at the current interrupt time is output.

If it is determined in step S1 that a power failure has occurred,
Subsequently, in step S2, it is determined whether the process is the first process at the time of a power failure,
If it is not the first process at the time of power failure, the process proceeds to step S4. In the case of the first process at the time of power failure, the number of output frequency reduction processes n1 (n1 ≧ 1) for setting the output frequency to fo1 × α1 is fetched from the storage unit 4a in step S3. The counter used for comparison is reset, and the process proceeds to step S4.

In step S4, the count value of the counter used for comparison with the output frequency reduction processing count n1 and the output frequency reduction processing count n1 for setting the output frequency to fo1 × α1.
If the count value exceeds the number n1 of output frequency reduction processes, the process proceeds to step S21, in which the voltage phase advance angle Δθ is added to the voltage phase angle θ in the previous interrupt time, and the current interrupt time The voltage phase angle θ is calculated (the same process as in the normal voltage). θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage phase angle θ at the current interrupt time is output.

If it is determined in step S4 that the count value is less than the number n1 of output frequency reduction processes, step S5
Proceed to. In step S5, a value obtained by multiplying the voltage phase lead angle Δθ by the phase coefficient α1 (100%> α1 ≧ 1%) is added to the voltage phase angle θ at the previous interrupt time to calculate the voltage phase angle θ at the current interrupt time. I do. θ = θ + α1 * Δθ (4) In step S6, the count value is updated. Step S2
In step 2, the voltage phase angle θ at the current interrupt time is output.

In the first embodiment, a power failure occurs (see FIG. 5).
In the case of (A) (point A), the output frequency is set to fo1 × α1 (10
0%> α1 ≧ 1%) (fo1 is the output frequency at the occurrence of a power failure), the output frequency is set to be lower than the actual rotation speed, so that the regenerative energy is easily returned and the DC bus voltage V _PN
Can be raised (FIG. 5B). Also, by changing the value of the phase coefficient α1, the rate of increase of the DC bus voltage _VPN can be adjusted as shown in FIG. For example, in an operation specification in which the regenerative energy from the motor is large and the DC bus voltage V _PN suddenly jumps up, the value of the phase coefficient α1 is set to a large value so that the increase in the DC bus voltage V _PN is reduced. As a result, the motor can be safely decelerated and stopped without tripping the inverter device due to an overvoltage error.

Embodiment 2 FIG. 6 is a diagram showing a configuration of an inverter device according to Embodiment 2 of the present invention. In the figure, reference numerals 31 to 36, 38, 39, and 40 are the same as those in FIG. 10 as a conventional example, and a description thereof will be omitted. Also, 1
Reference numeral b denotes a control unit that controls on / off of the transistor of the inverter unit 34, and reference numeral 2 denotes a power failure detection unit that detects a power failure. 3b is a preset V / F pattern,
Based on the acceleration / deceleration time set by the acceleration / deceleration time setting unit 38,
Calculate the output frequency and output voltage,
A V / F control unit that outputs a transistor control signal 40 for turning on / off the transistor 4 is a phase coefficient α1,
α2 (100%> α1, α2 ≧ 1%), the number of output frequency reduction processes n1, n2 (n1,
n2 ≧ 1), and is a storage unit for storing the DC bus voltage check value V _PN2 . When a power failure occurs and the inverter input voltage _VAC is no longer supplied, the V / F control unit 3b controls the output frequency to extend the control power supply maintenance time after the power failure, and controls the DC bus voltage. When V _PN falls below the DC bus voltage check value V _PN2 , the output frequency fo
Is not 0 Hz, control for extending the control power supply maintaining time is performed again.

FIG. 7 is a diagram showing control of the output frequency when a power failure occurs in the control unit 1b of the inverter device according to the second embodiment of the present invention. In the figure, fo is the output frequency, fo1 is the output frequency when a power failure occurs, and fo2
Is the output frequency when the DC bus voltage V _PN becomes equal to or less than the DC bus voltage check value V _PN 2, α1 and α2 are phase coefficients (100%> α1, α2 ≧ 1%), and Δt is an interrupt time as a control cycle , N1 and n2 denote the output frequency as f
o1 × α1, fo2 × α2, the number of output frequency reduction processes (n1, n2 ≧ 1). If a power failure occurs, with a Delta] t × n1 hours only the output frequency fo1 × [alpha] 1, if the output frequency fo when the DC bus voltage V _PN is equal to or less than the DC bus voltage check value V _PN 2 is not 0Hz Has the output frequency fo2 for Δt × n2 time.
× α21.

FIG. 8 shows a control section of an inverter device according to Embodiment 2 of the present invention, in which the inverter input voltage V _AC
FIG. 7 is a diagram showing a flowchart for calculating an output voltage phase angle at the time when the supply of the output voltage is stopped.

FIG. 9 is a diagram showing a power failure deceleration operation in the inverter device according to the second embodiment of the present invention. FIG. 9A shows the input voltage V _AC of the inverter device, FIG. 9B shows the DC bus voltage V _PN , and FIG. ) Is the output frequency fo, and (d) is the motor speed N. In the figure, A is the point when the inverter input voltage _VAC is no longer supplied.

A power outage deceleration operation in the inverter device according to the second embodiment will be described with reference to FIGS. The control unit 1b calculates the voltage phase angle θ by an interrupt process for each interrupt time Δt that is a control cycle.

In step S20, the voltage phase angle θ advanced from the previous interrupt time to the current interrupt time is calculated as a voltage phase advance angle Δθ. Δθ = ω * Δt (1)

In step S1, it is determined whether the power supply voltage is normal or a power failure occurs. If the power supply voltage is normal, in step S21,
The voltage phase angle θ at the current interrupt time is calculated by adding the voltage phase lead angle Δθ to the voltage phase angle θ at the previous interrupt time. θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage phase angle θ at the current interrupt time is output.

If it is determined in step S1 that a power failure has occurred,
Subsequently, in step S2, it is determined whether the process is the first process at the time of a power failure,
If it is not the first process at the time of power failure, the process proceeds to step S4. In the case of the first process at the time of power failure, the number of output frequency reduction processes n1 (n1 ≧ 1) for setting the output frequency to fo1 × α1 is fetched from the storage unit 4b in step S3. The counter used for comparison is reset, and the process proceeds to step S4.

In step S4, the count value of the counter used for comparison with the output frequency reduction processing frequency n is compared with the output frequency reduction processing frequency n1 for setting the output frequency to fo1 × α1, and the count value is determined as the output frequency. If the number is less than n1, the process proceeds to step S5, and the value obtained by multiplying the voltage phase lead angle Δθ by the phase coefficient α1 (100%> α1 ≧ 1%) is added to the voltage phase angle θ in the previous interrupt time. Voltage phase angle θ at interrupt time this time
Is calculated. θ = θ + α1 * Δθ (4) In step S6, the count value is updated. Step S2
In step 2, the voltage phase angle θ at the current interrupt time is output.

In step S4, the count value is lower than the output frequency.
If it is determined that the number of reduction processing times n1 has been exceeded,
DC bus voltage V at step S7_PNCheck the DC bus power
Pressure V _PNIs the DC bus voltage check value V_PNIf you are over 2
If so, the process proceeds to step S21, and the
The voltage phase lead angle Δθ to the voltage phase angle θ at
Calculate the voltage phase angle θ at the interrupt time this time
(Same processing as when the voltage is normal). θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage at the current interrupt time
Output the phase angle θ.

If it is determined in step S7 that the DC bus voltage V _PN is equal to or less than the DC bus voltage check value V _PN2 , it is then determined in step S8 whether or not the output frequency fo is 0 Hz. In the case of 0 Hz, step S
21, the process proceeds to step S22.

If the output frequency fo is not 0 Hz in step S8, the flow advances to step S9 to perform control for extending the control power supply maintaining time. The output frequency when the DC bus voltage V _PN is determined to be equal to or less than the DC bus voltage check value V _PN 2 is f
o2. In step S9, it is determined whether the process is the first process,
If it is not the first process at the time of power failure, the process proceeds to step S11.
Further, in the case of the first process, the number of output frequency reduction processes n2 (n2 ≧ 1) for setting the output frequency to fo2 × α2 is fetched from the storage unit 4b in step S10 and compared with the number of output frequency reduction processes n2. The counter used is reset, and the process proceeds to step S11.

In step S11, the count value of the counter used for comparison with the output frequency reduction processing frequency n2 and the output frequency reduction processing frequency n for setting the output frequency to fo2 × α2
If the count value is less than the number n2 of output frequency reduction processes, the process proceeds to step S12, and the phase coefficient α2 (100%> α2 ≧ 1%) is applied to the voltage phase advance angle Δθ.
Is added to the voltage phase angle θ at the previous interrupt time to calculate the voltage phase angle θ at the current interrupt time. θ = θ + α2 * Δθ (5) In step S13, the count value is updated. Step S
In step 22, the voltage phase angle θ at the current interrupt time is output.

If it is determined in step S11 that the count value has exceeded the number n2 of output frequency reduction processes, the process proceeds to step S21, in which the voltage phase advance angle Δθ is added to the voltage phase angle θ in the previous interrupt time, and the current interrupt time Is calculated (the same process as when the voltage is normal). θ = θ + Δθ = θ + ω * Δt (2) In step S22, the voltage phase angle θ at the current interrupt time is output.

In the first embodiment, when a power failure occurs (point A in FIG. 5A), the output frequency is set to fo1 × α1
As (100%> α1 ≧ 1% ) (fo1 the output frequency of the power failure), an example has been described which is adapted to raise the DC bus voltage V _PN, in the second embodiment, further deceleration stop motor If it is difficult to maintain the control power supply before performing the control, the output frequency is set to fo2 × α2 (100%> α
As 2 ≧ 1%) (fo2 output frequency at which the DC bus voltage V _PN is equal to or less than the DC bus voltage check value V _PN 2), control to extend the control power maintenance time by increasing the DC bus voltage V _PN Is performed.

In the above description, the storage unit stores the phase coefficients α1, α2 (100%> α1, α2 ≧ 1%), the number of output frequency reduction processes n1, n2 forcibly reducing the output frequency.
(N1, n2 ≧ 1), the DC bus voltage check value V _PN2 has been described as an example, but the parameter may be externally set as a parameter.

[0052]

Since the present invention is configured as described above, it has the following effects.

A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, a transistor and a diode. An inverter unit that converts DC power into AC power of variable frequency and variable voltage, and based on the input frequency setting,
A control unit that calculates an output frequency and an output voltage and outputs a transistor control signal for turning on / off a transistor of the inverter unit; and a storage unit that stores a phase coefficient by which the output frequency is multiplied. When the power failure occurs, the control unit calculates the output frequency by multiplying the output frequency at the time of the power failure by the phase coefficient, so that the regenerative energy can be easily returned, As a result, the DC bus voltage V _PN can be increased (the control power can be maintained), so that the motor can be safely decelerated and stopped without free running.

Further, the storage unit stores the number of output frequency reduction processes for forcibly reducing the output frequency, and when a power failure occurs, the control unit stores the phase coefficient in the output frequency at the time of the power failure. Since the multiplying process is performed by the number of times of the output frequency reduction process, the rate of increasing the DC bus voltage _VPN can be easily adjusted.

Further, a phase coefficient stored in the storage unit,
The output frequency reduction processing times, since to be able parameter set from the outside, Opereta is externally can easily adjust the ratio to increase the DC bus voltage V _PN.

A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, a transistor and a diode. An inverter configured to convert DC power into AC power having a variable frequency and a variable voltage, and a transistor for calculating an output frequency and an output voltage based on an input frequency setting and for turning on / off a transistor of the inverter. And a control unit that outputs a control signal.
A storage unit for storing a phase coefficient of the output frequency, a first number of output frequency reduction processes for forcibly reducing the output frequency, a second number of output frequency reduction processes, and a DC bus voltage check value for determining whether control power can be maintained. The control unit, when a power failure occurs, calculates the output frequency by multiplying the output frequency at the time of the power failure by the first phase coefficient, and the DC bus voltage at the time of the power failure is the DC Since the output frequency at the time when the DC bus voltage becomes equal to or less than the DC bus voltage check value is calculated by multiplying the output frequency when the DC bus voltage becomes equal to or less than the DC bus voltage check value, the power failure occurs. in a time when the generation timing and the DC bus voltage at the time of power failure is equal to or less than the DC bus voltage check value, so that it can raise the DC bus voltage V _PN (to keep the control power) Ri, it is possible to increase the efficiency DC bus voltage V _PN.

Further, the storage unit stores a first number of output frequency reduction processes and a second number of output frequency reduction processes for forcibly reducing the output frequency. A process of calculating the output frequency by multiplying the output frequency at the time of occurrence of the first phase coefficient by the first phase coefficient the number of times of the first output frequency reduction process, and the DC bus voltage at the time of the power failure is the DC bus voltage When the DC bus voltage becomes equal to or less than the check value, the output frequency at the time when the DC bus voltage becomes equal to or less than the DC bus voltage check value is multiplied by the second phase coefficient to calculate the output frequency. Since the reduction process is performed only the number of times, the rate at which the DC bus voltage _VPN is increased can be easily adjusted.

Further, the first phase coefficient and the second phase coefficient stored in the storage section, the first number of output frequency reduction processes, the second number of output frequency reduction processes, and the DC bus voltage check value are stored in an external device. since to allow parameter setting from Opereta is externally can easily adjust the ratio to increase the DC bus voltage V _PN.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an inverter device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing control of an output frequency when a power failure occurs in control unit 1a of the inverter device according to Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a relationship between a voltage and a voltage phase angle in the inverter device according to Embodiment 1 of the present invention.

FIG. 4 is a diagram showing a flowchart for calculating the output voltage phase angle at the time when the inverter input voltage _VAC is no longer supplied in the control unit of the inverter device according to Embodiment 1 of the present invention;

FIG. 5 is a diagram showing a power outage deceleration operation in the inverter device according to Embodiment 1 of the present invention.

FIG. 6 is a diagram showing a configuration of an inverter device according to Embodiment 2 of the present invention.

FIG. 7 is a diagram showing control of an output frequency when a power failure occurs in a control unit 1b of the inverter device according to Embodiment 2 of the present invention.

FIG. 8 is a diagram showing a flowchart for calculating the output voltage phase angle at the time when the inverter input voltage _VAC is no longer supplied in the control unit of the inverter device according to Embodiment 2 of the present invention.

FIG. 9 is a diagram showing a power outage deceleration operation in the inverter device according to Embodiment 2 of the present invention.

FIG. 10 is a diagram showing a configuration of a conventional inverter device.

FIG. 11 is a diagram showing a relationship between a voltage and a voltage phase angle.

FIG. 12 is a diagram showing a flowchart for calculating an output voltage phase angle in a control unit in a conventional inverter device.

FIG. 13 is a diagram showing a power outage deceleration operation in a conventional inverter device.

FIG. 14 is a diagram showing a schematic configuration of a main circuit of a conventional inverter device disclosed in, for example, Japanese Patent Application Laid-Open No. H6-165582.

[Explanation of symbols]

1a, 1b control unit, 2 power failure detection unit, 3a, 3b
V / F control section, 4a, 4b storage section, 31 three-phase AC power supply, 32 converter section, 33 smoothing capacitor, 34 inverter section, 35 motor, 36
Voltage detector, 37 control unit, 38 acceleration / deceleration time setting unit, 39 V / F control unit, 40 transistor control signal, ω angular velocity, Δt interrupt time, θ
Voltage phase angle, [Delta] [theta] voltage phase advance angle, the input voltage, V _PN DC bus voltage V _AC inverter, N motor speed, fo output frequency, the output frequency at fo1 power failure, fo2 DC bus voltage V _PN is the DC bus The output frequency at the time when the voltage check value V _PN 2 or less, α1, α2 phase coefficient (100%> α1, α2
≧ 1%), n1, n2 Number of output frequency reduction processing (n
1, n2 ≧ 1), V _PN 2 DC bus voltage check value.

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Claims (6)

[Claims] A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, a transistor and a diode. An inverter configured to convert DC power into AC power having a variable frequency and a variable voltage, and a transistor for calculating an output frequency and an output voltage based on an input frequency setting and for turning on / off a transistor of the inverter. A control unit that outputs a control signal; anda storage unit that stores a phase coefficient by which the output frequency is multiplied.If the power failure occurs, the control unit outputs the output frequency at the time of the power failure. Wherein the output frequency is calculated by multiplying the phase coefficient by the phase coefficient. 2. The storage unit stores the number of output frequency reduction processes for forcibly reducing an output frequency, and the control unit includes:
2. The inverter device according to claim 1, wherein when a power failure occurs, a process of multiplying the output frequency at the time of the power failure by the phase coefficient is performed by the number of times of the output frequency reduction process. 3. The inverter device according to claim 1, wherein parameters of the phase coefficient and the number of output frequency reduction processes stored in the storage unit can be externally set. 4. A converter for converting three-phase AC power to DC power, a smoothing capacitor for smoothing the DC voltage converted by the converter, a voltage detector for detecting a DC bus voltage, a transistor and a diode. An inverter configured to convert DC power into AC power having a variable frequency and a variable voltage, and a transistor for calculating an output frequency and an output voltage based on an input frequency setting and for turning on / off a transistor of the inverter. A control unit that outputs a control signal, a first phase coefficient and a second phase coefficient by which the output frequency is multiplied, a first output frequency reduction process for forcibly reducing the output frequency, and a second phase coefficient. Storage unit for storing the number of output frequency reduction processes and the DC bus voltage check value for determining whether the control power supply can be maintained or not The control unit, when a power failure occurs, calculates the output frequency by multiplying the output frequency at the time of the power failure by the first phase coefficient, and the DC bus voltage at the time of the power failure is the DC When the bus voltage is equal to or less than the bus voltage check value, the output frequency is calculated by multiplying the output frequency when the DC bus voltage becomes equal to or less than the DC bus voltage check value by the second phase coefficient. And an inverter device. 5. The storage unit stores a first number of output frequency reduction processes for forcibly reducing an output frequency and a second number of output frequency reduction processes, and the control unit, when a power failure occurs, causes a power failure. A process of calculating the output frequency by multiplying the output frequency at the time of occurrence of the first phase coefficient by the first phase coefficient the number of times of the first output frequency reduction process, and the DC bus voltage at the time of the power failure is the DC bus voltage When the DC bus voltage becomes equal to or less than the check value, the output frequency at the time when the DC bus voltage becomes equal to or less than the DC bus voltage check value is multiplied by the second phase coefficient to calculate the output frequency.
5. The inverter device according to claim 4, wherein the number of times of the output frequency reduction processing is reduced. 6. A first phase coefficient and a second phase coefficient stored in the storage unit, a first number of output frequency reduction processes, a second phase coefficient,
6. The inverter device according to claim 4, wherein the number of times of the output frequency reduction processing and the DC bus voltage check value can be externally set as parameters.