JP2002158928A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small size and simple structure solid-state image pickup device with memories which are provided in pixels and in which pixel information is stored to widen a dynamic range. SOLUTION: This solid-state image pickup device has memory units 11M which are provided in pixels 11P and in which first information is written in every charge accumulation period 13A. If the signal voltage of the pixel exceeds a reference voltage Vref before the charge accumulation period, second information is written in the memory unit 11M and the photodiode 711 of the pixel 11P is reset. If the first information is recorded in the memory unit 11M after the charge accumulation period 13A, the signal voltage is outputted as the signal of the pixel 11P. If the second information is recorded in the memory unit 11M, a signal obtained by adding the reference voltage Vref to the signal voltage is outputted as the signal of the pixel 11P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device which has a wide dynamic range, has a simple element structure, and is suitable for miniaturization.

[0002]

2. Description of the Related Art Conventionally, as a method of expanding a dynamic range in a solid-state imaging device, for example, Japanese Patent Laid-Open No.
There is a method disclosed in Japanese Patent No. 3490. Hereinafter, a conventional solid-state imaging device will be described with reference to the accompanying drawings.
FIG. 2 shows operation timing in the solid-state imaging device,
(A) shows a timing of a charge accumulation time, and (b) shows an operation timing chart of a part in non-destructive readout of all pixels.

FIG. 3 is a block diagram of a conventional solid-state imaging device. In FIG. 3, a solid-state imaging device includes an amplification type solid-state imaging device 1A having a phototransistor, and a reset circuit 2A (usually a photo-electric device) that selectively performs a reset operation on pixels that are sequentially read out from the imaging device 1A by switching. A signal is read from the source of the transistor, and in this case, a source reset circuit), a current-voltage conversion circuit 3A that similarly performs a current-voltage conversion on an output signal (current) from the imaging device 1A,
A sample and hold circuit 4A that samples and holds the output of the current-voltage conversion circuit 3A, a voltage comparison circuit 6A that compares the output voltage of the sample and hold circuit 4A with the voltage of a reference voltage input terminal 5A arbitrarily given from the outside,
A switch 7A controlled by the output of the voltage comparison circuit 6A, and a reset potential 8A for applying a reset potential to the amplification type solid-state imaging device 1A through the switch 7A.
And a signal processing circuit 9A that processes an output signal of the current-voltage conversion circuit 3A to generate an image pickup output signal.

The signal processing circuit 9A includes an amplifier circuit 10A for amplifying an output signal of the current-voltage conversion circuit 3A.
And a register 11A for temporarily storing operation information of the voltage comparison circuit 6A, and a switch for switching between an output signal of the current-voltage conversion circuit 3A and an output signal via the amplifier circuit 10A based on the information output from the register 11A. 12A
It is comprised including.

Next, referring to FIGS. 2A and 2B,
The operation of the solid-state imaging device will be described. In the amplification type solid-state imaging device 1A that performs photoelectric conversion and charge accumulation operation for each pixel, all-pixel non-destructive readout 14A is performed at a speed twice or more the normal readout speed during the charge accumulation period 13A.

The output signal (current) read at this time is:
A sample-and-hold circuit 4A that converts the voltage into a voltage by a current-voltage conversion circuit 3A and samples and holds this output
Is input to the input terminal aa of the voltage comparison circuit 6A. The voltage at the input terminal aa and the voltage at the reference voltage input terminal 5A (input terminal b
The voltage of the input terminal aa is higher than the voltage of the input terminal bb. If the voltage of the input terminal aa is higher than the voltage of the input terminal bb, it is determined that the accumulated charge amount of the pixel read at that time is larger than the set reference value. I do.

The voltage at the input terminal bb, ie, the reference voltage, can be set arbitrarily.
For example, in a pixel to which strong light within the imaging range of the amplification type solid-state imaging device 1A is incident, the voltage is determined to be such that if the charge accumulation is continued during the normal accumulation period, the pixel may be saturated. If the voltage of the input terminal aa is higher than the voltage of the input terminal bb, the voltage comparison circuit 6A
(Cc point) is turned on, the switch 7A is controlled to conduct between dd and ee, and the reset potential 8A is applied to the read line ee of the pixel being read.

The read line ee is connected to the source of the phototransistor (in the amplification type solid-state imaging device 1A, not shown) of the pixel being read,
The source potential of the phototransistor becomes lower than the gate potential, and as a result, the charge stored in the pixel is discharged and reset (this reset operation is called a source reset method).

This situation will be described for two consecutive pixels. First, the output signal 1 being read out at the pixel 15A is output.
6A and the output signal 17A during reset.
In the succeeding next pixel 18A, the voltage of the input terminal aa is lower than the voltage of the input terminal bb and is not reset, and the operation shifts to reading of the next pixel.

A reset amplification type solid-state imaging device 1
The pixel A discharges all the accumulated charges up to that point, and thereafter starts the accumulation operation again. That is, non-destructive readout of all pixels is performed in the middle of the normal charge accumulation period (one field period) 13A, and the electronic shutter operation is arbitrarily performed for each pixel. The amount of accumulated charge can be reduced (1
(See pixel period 15A).

On the other hand, in a pixel having a small accumulated charge amount in this readout, charge accumulation continues during a regular accumulation period (1).
(See the pixel period 18A.) Information indicating whether each pixel has been reset or not has been temporarily stored in the register 11A, and when performing all-pixel reading 19A for reading an imaging output signal, the stored data is shifted for a predetermined time. Read.

At the end of the regular charge accumulation period 13A shown in FIG. 2A, the final all-pixel reading 19A is performed at substantially the same reading speed as that for the above-described electronic shutter operation. The signal is processed by the processing circuit 9A and then output. That is, the pixels that have not been reset in the middle of the charge accumulation period 13A output the output of the current-voltage conversion circuit 3A as it is through ff-hh of the switch 12A during all-pixel reading 19A, but are reset in the middle. Since the accumulated charge amount of the pixel is reduced, the output is amplified by the amplifying circuit 10A by the reduced amount, and is output between gg and hh of the switch 12A. The switch 12A is switched by the register 11
This is performed based on the information output while sequentially shifting one pixel from A.

As described above, an image pickup output signal is output from a pixel having a small accumulated charge amount as in normal reading, and the accumulated charge amount is saturated for a pixel having a large accumulated charge amount due to strong input light. It is possible to output an image pickup output signal corresponding to the input light intensity. This makes it possible to expand the dynamic range of the output of the amplification type solid-state imaging device.

[0014]

As described above, in the conventional solid-state imaging device, a memory as a register is provided outside the solid-state imaging device in order to expand the dynamic range, and the memory for the pixel is provided in the memory. Information was stored and signal processing was performed based on the information. On the other hand, there has been a demand for a simpler and smaller solid-state imaging device.

Accordingly, the present invention provides a solid-state imaging device,
An object of the present invention is to provide a small-sized and simple solid-state imaging device in which a memory for storing pixel information is provided in a pixel so that a dynamic range can be expanded.

[0016]

As a means for achieving the above object, the present invention provides a photodiode and amplifies a charge generated by photoelectric conversion during a charge accumulation period in the photodiode and converts the amplified signal into a signal voltage. In a solid-state imaging device in which a pixel having an amplifying transistor to be converted is arranged in a matrix and the signal voltage is sequentially read from the pixel after the charge accumulation period to be an image signal, the pixel is arranged in the pixel. The first charge accumulation period
And the second information is written to the memory unit when the signal voltage of the pixel exceeds the reference voltage before the charge accumulation period is reached. Resets the photodiode of the pixel and outputs the signal voltage as a signal of the pixel when the first information is recorded in the memory unit after the charge accumulation period. When the second information is recorded in the pixel, a signal obtained by adding the reference voltage to the signal voltage is output as a signal of the pixel.

[0017]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. <Embodiment> The basic operation of the solid-state imaging device of this embodiment is as follows. First, a signal from a pixel is read out at a speed higher than the normal reading speed (preferably an integer multiple speed) and non-destructively (hereinafter, also referred to as non-destructive reading). Next, it is determined whether or not the non-destructively read signal exceeds an arbitrarily set level.

Next, when it is determined that the read signal exceeds the set level, the photodiode of the pixel is reset and written to the memory in the pixel. Next, the in-pixel memory information of each pixel is read, and when it exceeds the set level and is reset, it is added (or amplified) to the output signal at the time of normal reading. Pixels for which the photodiode is not reset are output as they are. In this way, the dynamic range is expanded.

Hereinafter, the configuration of this embodiment will be described in detail.
The pixel 11P will be described as an example. FIG. 1 is a block diagram showing an embodiment of the solid-state imaging device according to the present invention. 2A and 2B show operation timings in the solid-state imaging device. FIG. 2A is a timing chart of a charge accumulation period, and FIG. 2B is an operation timing chart of a part in non-destructive readout of all pixels.

As shown in FIG. 1, in the solid-state imaging device 1 according to the present embodiment, the pixel 11P includes a memory unit 11M and a sensor unit 11S, and such pixels are arranged in a predetermined matrix. , Column select shift register 1
00 and the row selection shift register 300, and are reset by the column reset shift register 200 and the row reset shift register 400. In FIG. 1, only three pixels are displayed for convenience of display. In FIG. 1, G, S, and D indicate the gate, source, and drain of the MOS transistor, respectively.

The memory section 11M comprises a memory switching transistor 111 and a memory capacity 211. The gate of the memory switching transistor 111 is connected to the row reset signal line RR1, the drain is connected to the memory signal line B1,
The sources are connected to one ends of the memory capacitors 211, respectively. The row reset signal line RR1 is connected to the row reset shift register 400, and receives a row reset signal. The other end of the memory capacity 211 is grounded.

The sensor section 11S includes a reset transistor 3
11, a reset transistor 411, an amplification transistor 511, a row selection transistor 611, and a photodiode 711. P of photodiode 711
The N type region is grounded, and the N type region is an amplifying transistor 511.
And the source of the reset transistor 411. The gate of the reset transistor 411 is connected to the row reset signal line RR1 and the drain is connected to the source of the reset transistor 311. The gate of the reset transistor 311 is connected to the column reset line A1, and the drain is connected to the reference voltage supply line Vdd. The drain of the amplification transistor 511 is connected to the reference voltage supply line Vdd, and the source is connected to the drain of the row selection transistor 611. Row selection transistor 61
One gate is connected to the row selection signal line RS1, and the source is connected to the signal output line SL1. Row selection signal line RS1
Are connected to a row selection shift register 300 and supplied with a row selection signal.

The column selection signal line CS1 connected to the column selection shift register 100 and supplied with a column selection signal is connected to the gate of the memory read column switching transistor 31 and the gate of the column signal selection switching transistor 41. I have. The drain of the column signal selection switching transistor 41 is connected to the signal output line SL1, and the source is connected to the signal output line SL.

The signal output line SL is connected to the signal changeover switch 700
Are connected to a common terminal b. Signal switch 700
Is connected to one input terminal C ′ of the voltage comparison circuit 500.
The terminal d is connected to one input terminal d 'of the output switching circuit / voltage adding circuit 600. The drain of the memory read column switching transistor 31 is connected to the source of the memory read switching transistor 21, and the source is connected to the address output line AL.

The address output line AL is connected to the other input terminal u 'of the output switching circuit / voltage adding circuit 600.
From the output terminal f of the output switching circuit / voltage adding circuit 600,
Time-series signals from the pixels are output to a signal processing circuit (not shown).

A column reset signal line CR connected to the column reset shift register 200 and supplied with a column reset signal.
1 is connected to the input terminal 1 of the AND circuit 61. The output terminal n of the AND circuit 61 is connected to a column reset line A1 connected to the drain of the memory write switching transistor 101.
Connected to

The gate of the memory write switching transistor 101 is connected to a write signal line W connected to the terminal j.
The sources are respectively connected to the memory signal lines B1 connected to the input terminal p of the amplifier 51. The gate of the memory read switching transistor 21 is connected to the read signal line R connected to the terminal k, and the drain is connected to the output terminal q of the amplifier 51.

A reference signal Vref is supplied to an input terminal a 'of the voltage comparison circuit 500. This reference signal Vre
f denotes an input terminal v ′ to the output switching circuit / voltage load circuit 600.
Supplied by The output terminal e of the voltage comparison circuit 500 is connected to the terminal g of the AND circuit
Is connected to one end of a reset potential 2 whose other end is grounded, and the input terminal m of the AND circuit 61 is connected to the common terminal i.

Memory column reset line MC connected to terminal r
The gates of the column reset transistors 71 and 72 and the gates of the column reset transistors 81 and 82 are connected to R. The source of the column reset transistor 71 is grounded, the drain is connected to the memory signal line B1, the source of the column reset transistor 81 is grounded, and the drain is connected to the column reset line A1.

Next, the operation of the solid-state imaging device 1 according to the embodiment will be described. As shown in FIG. 2A, in the present embodiment, all-pixel non-destructive reading 19A, which is normal reading, is performed at the end of the charge accumulation period 13A. A reset 14A is performed.

First, the nondestructive readout 14A will be described for the pixel 11P as an example. When the normal signal reading from the pixel is completed, the pixel 11P is reset. That is, the column reset shift register 200 sets the column reset signal line CR1 to high (hereinafter, also simply referred to as H), the row reset shift register 400 sets the row reset signal line RR1 to H, and the AND circuit input changeover switch 800 sets the reset potential 2 (Terminal i and terminal h are connected). The write signal line W, the read signal line R, the column selection signal line CS1, and the row selection signal line RS1 are low (hereinafter, also simply referred to as L). Therefore, the AND circuit 61 sets the column reset line to H,
Since the reset transistor 311 is turned on and the row reset signal line RR1 is at H, the reset transistor 411 is turned on.
11 is turned on, and the N-type region of the photodiode 711 is reset by the reference voltage supply line Vdd. When the reset is performed, the column reset signal line CR1 and the row reset signal line RR1 become L, the AND circuit input changeover switch 800 connects the terminals i and g, the memory column reset line WCR becomes H, and the column reset signal is reset. Transistors 71, 8
1 turns on, the column reset line A1 and the memory signal line B1
Becomes L (ground potential), and the charge accumulation of the photodiode 711 is started.

At a certain time before the next normal reading (see FIG. 2A), the row selection shift register 300 sets the row selection signal line RS1 to H and turns on the row selection transistor 611. The charge accumulated in the photodiode 711 appears at the drain of the column signal selection switching transistor 41 as a signal voltage converted by the amplification transistor 511 because the amplification transistor 511 performs a source follower operation.

Here, when the column selection shift register 100 sets the column selection signal line CS1 to H and turns on the column signal selection switching transistor 41, the signal voltage appears on the signal output line SL. At this time, the reset transistor 31 is also turned on, but since the read signal line R is L, the memory read switching transistor 21 is off,
The memory information of the memory unit 11M (that is, the memory capacity 2
11) is not output to the address output line AL.

The signal voltage appearing on the signal output line SL is input to one input terminal c 'of the voltage comparison circuit 500 because the terminals b and c are connected in the signal changeover switch 700, where the other is input. Is compared with a reference voltage Vref set to a predetermined value which is input to the input terminal a ′. When the signal voltage is equal to or larger than the reference voltage Vref,
The voltage at the output terminal e of the voltage comparison circuit 500 becomes H. A
In the ND circuit input changeover switch 800, since the terminal i and the terminal g are connected, H is input to the input terminal m of the AND circuit 61.

At this time, the column reset shift register 200
As a result, the column reset signal line CR1 goes high, the input terminal 1 of the AND circuit 61 goes high, the output terminal n of the AND circuit 61 goes high, and the column reset line A1 goes high. In this state, when the write signal line W is set to H, the memory write switching transistor 101 is kept on, and the row reset signal line RR1 is set to H by the row reset shift register 400, the memory switching transistor 111 is turned on. H is recorded (stored) in the capacity 211.

At this time, since the reset signal line RR1 is at H, the reset transistor 411 is on, and the column reset line A1 is also at H, so that the reset transistor 311 is also on. Therefore,
The photodiode 711 is reset to the reference voltage Vdd.

That is, in reading a signal from a non-destructive pixel before normal reading, if the signal is equal to or larger than the reference signal, H is written to the memory unit 11M,
The photodiode 711 will be reset.
The AND circuit input changeover switch 800 connects the terminal i to the terminal h at the time of normal reading and at the time of resetting immediately thereafter. In other cases, the terminal i is connected to the terminal g.

On the other hand, when the signal voltage input to the voltage comparison circuit 500 is lower than the reference voltage Vref, the voltage at the output terminal e of the voltage comparison circuit 500 becomes L. AND
In the circuit input changeover switch 800, the terminal i is the terminal g
, L is input to the input terminal m of the AND circuit 61. At this time, the column reset shift register 2
H output to the column reset signal line CR1 by A
The signal is input to the input terminal 1 of the ND circuit 61 and the AND circuit 61
, That is, the column reset line A1 becomes L.

The write signal line W is set to H to turn on the memory writing switching transistor 101, and the row reset signal line RR 1 is turned on by the row reset shift register 400.
Is set to H, and the memory switching transistor 111 is turned on.
Is recorded (in the reset state, L is recorded). On the other hand, since the column reset line A1 is at L, the reset transistor 311 is turned off.
Although the row reset signal line RR1 is H and the reset transistor 411 is on, the photodiode 711
Is not reset.

That is, in reading a signal from a non-destructive pixel before normal reading, if the signal is smaller than the reference signal, L is written in the memory unit 11M and the photodiode 711 is not reset.

Next, the normal signal reading from the pixel will be described. Write signal line W is L, read signal line R is H
To In the signal changeover switch 700, the terminal b is connected to the terminal d which is one input of the output switching circuit / voltage adding circuit 600. In the AND circuit input changeover switch 800, the terminal i is connected to the terminal h.

The row selection shift register 300 sets the row selection signal line RS1 to H, and at the next clock, the column selection shift register 100 sets the column selection signal line CS1 to H, and the column reset shift register 200 sets the column reset signal line C to H.
When R1 is L, the row selection transistor 611 and the column signal selection switching transistor 41 are on, so that the electric charge accumulated in the photodiode 711 is converted by the amplification transistor 511 and is converted into a signal voltage to be a signal voltage. The signal is input to one input terminal d ′ of the output switching circuit / voltage adding circuit 600 through the selection switching transistor 41, the signal output line SL, and the terminal d. The column reset line A1 is at L.

On the other hand, the read signal line R is H,
Since the memory read switching transistor 21 is on, the voltage stored in the memory capacity 211 is the memory switching transistor 111, amplifier 51, and memory read that are on because the row reset signal line RR1 is H. Switching transistor 2
1. Memory reading column switching transistor 31
(It is turned on because the column signal selection line CS1 is H) and is input to the other input terminal u ′ of the output switching circuit / voltage adding circuit 600 through the address output line AL.

When the memory capacity 211 is H, the output switching circuit / voltage adding circuit 600 converts the signal voltage input to the input terminal d 'to the reference voltage Vre input from the input terminal v'.
The voltage to which f has been added is output to the output terminal f. If the memory capacity 211 is L, the output switching circuit / voltage adding circuit 60
0 outputs the signal voltage input to the input terminal d 'to the output terminal f as it is.

At the next clock, the read signal line R is set to L, the row reset signal line RR1 is set to H by the row reset shift register 400, and the column reset signal line CR1 is set.
Is set to H and the column reset line A1 is set to H, the reset transistor 41
Since 1 is turned on, the photodiode 711 is reset to the reference voltage Vdd.

In this way, in a high-speed nondestructive read operation, a photodiode that outputs a voltage higher than a predetermined signal voltage can be reset, and a predetermined voltage can be added to a normal read operation to obtain an output voltage. , The dynamic range can be expanded. Note that, apart from the method of adding a voltage as described above, a method of amplifying a voltage in a predetermined relationship may be employed. As described above, one pixel has been described. However, nondestructive readout, normal readout, and reset may be sequentially performed on pixels in all rows and all columns.

In this embodiment, since the pixels comprising the memory section and the sensor section are realized on the same chip, the dynamic range can be expanded in a solid-state imaging device which can be reduced in size with a simple configuration. There are advantages.

The case where the memory capacity is used for the memory section has been described above. Instead of the memory capacity, a rewritable nonvolatile memory (flash memory, one-time R
If OM or the like is used as a memory element, position information of a pixel that causes a white defect can be stored in the memory element and read. That is, in the dark (when there is no light incident),
A signal having a large output may be detected, and the memory element adjacent to the photodiode of the corresponding pixel may be stored as a white defect. Each time reading is performed, the H signal is output from the memory element adjacent to the photodiode that causes white flaws, so that white flaws can be removed on the screen by interpolating the signal with an external circuit.

[0049]

As described above, the solid-state imaging device according to the present invention has the memory section which is arranged in the pixel and in which the first information is written every charge accumulation period, and reaches the charge accumulation period. Previously, when the signal voltage of the pixel exceeds the magnitude of the reference voltage, the second information is written to the memory unit and the photodiode of the pixel is reset, and after the charge accumulation period, the memory When the first information is recorded in the section, the signal voltage is output as a signal of the pixel, and when the second information is recorded in the memory section, the signal voltage is outputted. By outputting a signal obtained by adding the reference voltage as a signal of the pixel,
There is an effect that a memory for storing pixel information is provided in each pixel so that the dynamic range can be expanded, and a solid-state imaging device having a small and simple configuration can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 shows operation timing in the solid-state imaging device;
(A) shows a timing of a charge accumulation period, and (b) shows an operation timing chart of a part in non-destructive readout of all pixels.

FIG. 3 shows a block diagram of a conventional solid-state imaging device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 1A ... Amplification type solid-state imaging device, 2
... Reset potential, 3A ... Current-voltage conversion circuit, 4A ... Sample hold circuit, 5A ... Reference voltage input terminal, 6A ...
Voltage comparison circuit, 7A switch, 8A reset potential,
9A: Signal processing circuit, 10A: Amplifier circuit, 11A: Register, 11M: Memory unit, 11P: Pixel, 11S: Sensor unit, 12: Switching transistor for writing memory, 12A: Switch, 13A charge accumulation period, 14A:
Non-destructive reading and selective reset of all pixels, 15A: one pixel period (with reset), 16A: output signal during reading, 17A: output signal during reset, 18A: one pixel period (no reset), 19A: all pixels Non-destructive read, 2
1,22 ... switching transistor for memory reading,
31, 32: column switching transistors for memory reading, 41, 42: switching transistors for column signal selection, 51, 52: amplifiers, 61, 62: AND circuit, 7
1, 72 ... column reset transistor, 81, 82 ... column reset transistor, 100 ... column selection shift register,
101, 102: Switching transistor for memory writing, 111, 112, 121: Memory switching transistor, 200: Column reset shift register, 21
1, 212, 221: memory capacity, 300: row selection shift register, 311, 312, 321: reset transistor, 400: row reset shift register, 411,
412, 421 reset transistor, 500 voltage comparison circuit, 511, 512, 521 amplification transistor, 600 output switching circuit, 611, 612, 621
Row selection transistor, 700 ... signal changeover switch, 71
1,712,721 ... photodiode, 800 ... AN
D circuit input switch, A1, A2 ... column reset line,
AL: address output line, B1, B2: memory signal line, C
R1, CR2: column reset signal line, CS1, CS2: column selection signal line, MCR: memory column reset line, RR1, R
R2: row reset signal line; RS1, RS2: row selection signal line; SL, SL1, SL2: signal output line; Vdd: reference voltage supply line.

Claims (1)

[Claims] 1. A pixel having a photodiode and an amplifying transistor for amplifying a charge generated by photoelectric conversion during a charge accumulation period in the photodiode and converting the charge into a signal voltage, wherein the pixels are arranged in a matrix. A solid-state imaging device that sequentially reads the signal voltage from the pixel after the charge accumulation period to generate an image signal, the memory device having a memory unit that is disposed in the pixel and in which first information is written for each charge accumulation period. If the signal voltage of the pixel exceeds a reference voltage before reaching the charge accumulation period, second information is written to the memory unit and the photodiode of the pixel is reset. When the first information is recorded in the memory unit after the charge accumulation period, the signal voltage is output as a signal of the pixel, and When the second information is recorded in a memory portion, a signal obtained by adding the reference voltage to the signal voltage is output as a signal of the pixel, and the solid-state imaging device is characterized in that: