JP2002158450A - Wiring board - Google Patents

Abstract

(57) [Summary] [Purpose] In a wiring board in which electronic components are embedded, the adhesiveness of a wiring layer formed on an embedding resin is high, and defects due to poor adhesiveness such as plating blisters do not occur.
To provide a wiring board that can achieve high reliability in reliability tests such as a thermal shock test and a water resistance test. [Constitution] In a wiring board in which electronic components are embedded using an embedded resin inside the wiring board, the embedded resin and the wiring are provided. 10-point average roughness Rz of irregularities formed at the interface with the layer is 2 to 6
Prepare to be μm. The filling resin contains at least one kind of inorganic filler, and by adjusting the content of the inorganic filler in the range of 35 to 65% by volume, the adhesion of the wiring layer can be more effectively improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board in which electronic components such as a chip capacitor, a chip inductor and a chip resistor are embedded in an insulating substrate by using an embedded resin. In particular, it is suitable for a multilayer wiring board, a package for housing a semiconductor element, and the like.

[0002]

2. Description of the Related Art Recently, a multi-chip module (MCM) in which a large number of semiconductor elements are mounted on a build-up wiring board.
Is being considered. When electronic components such as a chip capacitor, a chip inductor, and a chip resistor are mounted, they are generally surface-mounted using solder on a mounting wiring layer formed on the surface of a wiring board.

However, when electronic components are surface-mounted on the surface of the build-up wiring board, a predetermined mounting area corresponding to each electronic component is required, so that there is naturally a limit to miniaturization. In addition, there is a problem in that the routing of the wiring at the time of surface mounting increases the parasitic inductance, which is unfavorable in characteristics, and makes it difficult to cope with a higher frequency of the electronic device.

In order to solve these problems, various methods for embedding electronic components in an insulating substrate have been studied.
Japanese Patent Application Laid-Open No. H11-126978 discloses a method of transferring an electronic component by soldering it to a wiring board with a transfer sheet made of a metal foil in advance and then transferring the electronic component. Japanese Patent Application Laid-Open No. 2000-124352 discloses a multilayer wiring board in which an insulating layer is built up on an electronic component embedded in a core substrate.

[0005]

In a method of embedding an electronic component in a core substrate, a gap between the core substrate and the electronic component is filled with a resin, and electrodes of the electronic component and wiring formed on an insulating layer are electrolessly plated. Need to be connected. In this case, the usual embedding resin cannot sufficiently secure the adhesion to the plating layer to be the wiring, and causes plating blisters or the like in a reliability test. This is because the composition of ordinary embedded resin is determined only for embedding semiconductor elements and electronic components, and it is completely considered that a wiring layer with adhesiveness is formed by plating on the surface of this embedded resin. It is not. Therefore, the adhesion to the wiring layer due to plating is poor, and defects due to poor adhesion such as plating blisters are likely to occur. But,
A wiring board using an embedded resin that focuses on improving the adhesion of plating has not yet been studied.

According to the present invention, in a wiring board in which an electronic component is embedded, a wiring layer formed on an embedding resin has high adhesiveness, does not cause a defect due to poor adhesion such as plating blister, and has a thermal shock resistance test. It is an object of the present invention to provide a wiring board that can obtain high reliability in a reliability test such as a water resistance test.

[0007]

SUMMARY OF THE INVENTION The present invention provides a wiring board in which electronic components are embedded, wherein the ten-point average roughness Rz of the irregularities formed at the interface between the embedded resin and the wiring layer is 2 to 6 μm. And The reason for adjusting the interface shape between the embedded resin and the wiring layer so that the ten-point average roughness Rz is 2 to 6 μm is that the unevenness of the embedded resin surface becomes an anchor of the wiring layer formed by plating, and the adhesion is improved. This is because it is possible (anchor effect) and the flatness of the build-up layer formed subsequently can be maintained. Also,
The ten-point average roughness R
When z is adjusted to be 2 to 6 μm, the shape of the wiring layer is not largely disturbed by the unevenness of the interface, so that there is an advantage that electrical characteristics corresponding to the simulation result at the design stage can be obtained.

If the ten-point average roughness Rz exceeds 6 μm, the shape of the wiring layer is greatly disturbed by the unevenness of the interface, and it is difficult to obtain electrical characteristics corresponding to the simulation results at the design stage. On the other hand, this ten-point average roughness Rz
Is less than 2 μm, it is difficult to obtain the above-described anchor effect, the adhesion between the wiring layer formed by plating and the embedded resin is reduced, and defects such as blisters and the like are likely to occur. The preferred range of the ten-point average roughness Rz is 2.5
５5 μm. This is because a wiring board having both the adhesion strength of the wiring layer, the flatness of the build-up layer, and high reliability can be obtained.

The unevenness of the embedded resin surface itself can be formed by roughening at least the embedded resin surface at a portion where the wiring layer is to be formed with an oxidizing agent such as potassium permanganate or chromic acid. In this roughening treatment, the resin component is oxidized and dissolved and removed, and furthermore, the inorganic filler as an additive is degranulated to form irregularities on the surface of the embedded resin. The unevenness serves as an anchor of the wiring layer by plating, and the adhesion to the wiring layer can be improved. As a result, the adhesion to the metal wiring on the embedded resin is improved, and defects such as blisters do not occur, thereby reducing defects.

What is important in the present invention is not to define the unevenness of the roughened surface of the embedded resin before forming the wiring layer by plating, but to define the unevenness of the embedded resin and the wiring layer after forming the wiring layer by plating. Is to define the ten-point average roughness Rz of the unevenness formed by the interface. The parameter directly representing the anchor effect described above is not the unevenness of the roughened surface of the embedded resin before forming the wiring layer by plating,
This is because the interface between the embedded resin showing the state where the wiring layer has actually penetrated and the wiring layer is formed and uneven. If only the irregularities on the roughened surface of the embedded resin before the formation of the wiring layer by plating are specified, another factor such as a hydrophilic treatment is involved in the adhesion of the wiring layer, so the anchor effect is directly reduced. It is not suitable as a parameter to represent. In addition, the use of the ten-point average roughness Rz as a parameter for evaluating the unevenness formed at the interface between the embedded resin and the wiring layer can be easily calculated from an enlarged photograph such as a SEM image of a cut surface of a product. Because you can. That is, the ten-point average roughness Rz is used because it is a parameter that can directly evaluate the state of unevenness formed at the interface between the embedded resin and the wiring layer in the product state. The ten-point average roughness Rz is specified in JIS B0601 3.5.1.

The embedding resin contains at least a resin component and at least one kind of inorganic filler. In addition to adjusting the coefficient of thermal expansion, the inorganic filler needs to have a three-dimensional structure skeleton after curing of the resin and the shape of the embedded resin after roughening treatment due to the effect of the inorganic filler as an aggregate. This is because there is no further collapse. Furthermore, in order to adjust the surface shape (irregularity) after the roughening, the content of the inorganic filler is in the range of 35 to 65% by volume (preferably 40 to 65% by volume).
(60% by volume, more preferably 40 to 50% by volume). The ten-point average roughness Rz of the unevenness formed at the interface between the embedded resin and the wiring layer is adjusted to 2 to 6 μm, and the adhesion of the wiring layer is obtained by regulating the content of the inorganic filler within a predetermined range. The anchoring effect required for this purpose can be obtained more effectively, and the shape of the embedded resin after the roughening treatment is maintained to suppress the generation of potential defects such as excessively large holes under the wiring layer. There are advantages that can be done.

The inorganic filler used is not particularly limited, but is preferably crystalline silica, fused silica, alumina, silicon nitride, or the like. The thermal expansion coefficient of the embedded resin can be effectively reduced. Thereby, an improvement in reliability against heat is obtained.

The filler diameter of the inorganic filler is preferably in the range of 0.1 to 50 μm because the embedded resin must easily flow into the gap between the electrodes of the electronic component. If the filler diameter of the inorganic filler exceeds 50 μm, the gap between the electrodes of the electronic component is likely to be clogged with the filler, and a portion having an extremely different coefficient of thermal expansion locally occurs due to insufficient filling of the embedded resin. On the other hand, the filler diameter of the inorganic filler is 0.
When the thickness is less than 1 μm, it becomes difficult to secure the fluidity of the embedded resin. The range is preferably 0.3 to 30 μm, and more preferably 0.5 to 20 μm. In order to achieve low viscosity and high filling of the embedded resin, it is preferable to widen the particle size distribution of the filler diameter of the inorganic filler. The shape of the inorganic filler is preferably substantially spherical in order to increase the fluidity and the filling rate of the embedded resin. In particular, a silica-based inorganic filler is preferable because a spherical one can be easily obtained.

The surface of the inorganic filler may be treated with a coupling agent, if necessary. This is because the wettability of the inorganic filler with the resin component is improved, and the fluidity of the embedded resin can be improved. As the type of the coupling agent, a silane type, a titanate type, an aluminate type or the like is used.

In consideration of the fluidity of the embedding resin, it is preferable to use at least one of a liquid epoxy resin, a bisphenol epoxy resin, a naphthalene type epoxy resin, and a phenol novolak resin, as an essential additive. If the fluidity of the embedded resin is poor, poor filling is likely to occur in the gap between the electrodes of the electronic component, and a portion having an extremely different coefficient of thermal expansion locally occurs. Naphthalene-type epoxy resins are particularly excellent when adhesion strength, heat resistance and moisture resistance are comprehensively considered.

An acid anhydride is preferably used as a curing agent. This is because the viscosity of the liquid epoxy resin can be further reduced. Because of its low viscosity, a filler component such as an inorganic filler necessary for lowering the thermal expansion coefficient of the embedded resin can be added so as to have a high filling rate. Further, the fluidity is improved, and the filling property of the gap between the electrodes of the electronic component is also improved. Preferably, a curing accelerator such as an imidazole-based curing accelerator is added. This is because improvement in heat resistance and the like can be expected.

The present invention particularly comprises a thermosetting resin, a curing agent thereof and at least one kind of inorganic filler, and the thermosetting resin is selected from bisphenol epoxy resin, naphthalene type epoxy resin and phenol novolak resin. At least one kind, and the content of the inorganic filler is 3
It is preferable to set the content to 5 to 65% by volume, and to use a wiring substrate using an embedding resin using an acid anhydride as a curing agent. This is because the adhesive strength of the wiring layer to the embedded resin can be improved, and high reliability can be obtained in reliability tests such as a thermal shock test and a water resistance test.

The substrate used in the present invention is FR-4,
It is preferable to use a so-called core substrate such as FR-5 or BT, but use a core substrate in which an opening is formed by sandwiching a thick copper foil having a thickness of about 35 μm between thermoplastic resin sheets such as PTFE. You may. As the opening, a through hole formed by punching a substrate, a cavity formed by a multilayer technique, or the like may be used. In addition, a structure may be used in which a build-up layer in which insulating layers and wiring layers are alternately laminated is formed on at least one surface of the core substrate, and an opening is formed to penetrate the core substrate and the build-up layer. In this case, even with a multilayer wiring board with a built-in capacitor as shown in FIG. 11, the thickness of the so-called glass-epoxy composite material (insulating board) is reduced to about 400 μm, which is half of 800 μm of a normal product. There is an advantage that the height can be reduced. As another example, a wiring board (for example, FIG. 1) in which an electronic component is embedded inside a core substrate or a wiring board (for example, FIG. 10) in which an electronic component is embedded inside a build-up layer can be formed.

The wiring board of the present invention may be manufactured, for example, as follows (FIGS. 1 to 9). FIG. 1 shows an example in which the wiring board of the present invention is used for a BGA board. First, the core substrate (1) is punched by a die press to form an opening (2) having a predetermined shape. As shown in FIG. 2, after the back tape (3) is attached to one surface of the core substrate so as to prevent the embedded resin from leaking, the surface on which the back tape is attached is placed on the lower side. As shown in FIG. 3, the electronic component (4) is arranged at a predetermined position on the adhesive surface of the pack tape in the opening from the other surface using a chip mounter.

As shown in FIG. 4, a filling resin (6) having a composition ratio suitable for the present invention is filled using a dispenser so as to fill a gap in the opening with the electronic component disposed in the opening. When using epoxy resin, the substrate
Heat to 10 to 180 ° C. to thermally cure the embedded resin. The conditions of the thermosetting may be preferably divided into two stages: a primary heating process performed at a temperature of 80 ° C. or more and less than 120 ° C., and a secondary heating process performed at a temperature of 120 ° C. or more and 180 ° C. or less. 1
In the next heating step, bubbles that are trapped between the electronic component and the gap in the opening or between the electrodes and cannot be removed in normal room temperature standing are effectively removed, and then the bubbles are removed in the second heating step. This is because the curing can be performed in a good condition without intrusion. In addition, the primary heating step and the secondary heating step
The temperature may be changed in multiple stages within each temperature range. For example, the primary heating step is performed at 100 ° C. × 1/80, and the secondary heating step is performed at 120 ° C. × 60 minutes, 160 steps.
It is good also as two steps of ° C x 10 minutes.

As shown in FIG. 5, the surface of the hardened embedded resin is flattened by rough polishing by a belt sander and finish polishing by lap polishing (60).
Is formed, as shown in FIG.
The embedded resin is partially removed by irradiating an AG laser, and a via hole (7) for conduction is formed so that the electrode of the embedded electronic component is exposed. This is for drawing out the wiring from the electrode of the electronic component.

The roughening process of the flattened surface (60) of the embedded resin is performed by a roughening process using an oxidizing agent. As the oxidizing agent used in the roughening step, permanganate (KMnO ₄ ,
HMnO ₄ etc.), chromic acid type (CrO ₃ , K ₂ Cr ₂ O ₇ ,
_{K 2 CrO 4, KCrO 3 Cl} , CrO 2 Cl 2 , etc.), nitric acid _{(HNO 3, N 2 O 4} , N 2 O 3, N 2 O, Cu (N
O ₃ ) ₂ , Pb (NO ₃ ) ₂ , AgNO ₃ , K, NH ₄ NO ₃
Etc.), halogen type (F ₂ , Cl ₂ , Br ₂ , I ₂ etc.), peroxide type (H ₂ O ₂ , Na ₂ O ₂ , BaO ₂ , (C ₆ H ₅ CO) ₂
O ₂ ), etc.), peracids (Na ₂ S ₂ O ₈ , Na ₂ SO ₅ , K ₂ S ₂₎
O ₈ , K ₂ SO ₅ , HCO ₃ H, CH ₃ CO ₃ H, C ₆ H ₅ CO
₃ H, C ₆ H ₄ (COOH) CO ₃ H, CF ₃ CO ₃ H, etc.),
Sulfuric acid type (hot concentrated sulfuric acid, fuming sulfuric acid + concentrated nitric acid, etc.), oxygen acid type (KClO, NaClO, KBrO, NaBrO, KI
O, NaIO, KClO ₃ , NaClO ₃ , KBrO ₃ ,
NaBrO ₃ , KIO ₃ , NaIO ₃ , KClO ₄ , NaC
10 ₄ , KBrO ₄ , NaBrO ₄ , KIO ₄ , NaI
O ₄ , HIO ₄ , Na ₃ H ₂ IO _6, etc.), metal salt-based (FeC
l ₃ , CuSO ₄ , Cu (CH ₃ COO) ₂ , CuCl ₂ ,
Hg (CH ₃ COO) ₂ , Bi (CH ₃ COO) ₃ , Pb
(CH ₃ COO) ₄ etc.), oxygen type (air, oxygen, ozone etc.), oxide type (CeO ₂ , Ag ₂ O, CuO, HgO,
PbO ₂ , Bi ₂ O ₃ , OsO ₄ , RuO ₄ , SeO ₂ , Mn
Known oxidizing agents such as O ₂ and As ₂ O ₅ can be used. In particular, alkali-permanganic acid-based, chromic acid-sulfuric acid-based, chromic acid-sulfuric acid-sodium fluoride-based, borofluoric acid-bichromic acid-based mixed resin, etc. Good roughening property for

The oxidizing agent dissolves components dissolved by the oxidizing agent contained in the embedding resin to form an elution portion, thereby forming a roughened surface composed of minute irregularities on the surface of the embedding resin.
Due to the anchor effect caused by the unevenness, it is possible to secure the adhesion between the wiring layer formed by the subsequent electroless plating or electrolytic plating and the embedded resin.

After the roughened surface is activated with a chemical solution containing a palladium chloride solution, electroless copper plating is performed (not shown).
Next, electrolytic copper plating is performed to form a panel plating layer (9) as shown in FIG. In addition, via hole (7)
As shown in FIG. 7, as shown in FIG. 7, copper is filled in the plating step to form the via conductor (8), so that it is possible to make an electrical connection with the electrode of the electronic component.

A dry film is stuck on the panel plating layer (9), and a predetermined wiring pattern is formed by exposing and developing (not shown). An unnecessary portion of the panel plating layer (9) for the wiring is removed by using an etching solution containing Na ₂ S ₂ O ₈ / H ₂ SO ₄ , as shown in FIG.
A predetermined wiring (90) is formed. After that, as shown in FIG. 9, a known build-up technique may be used to form multiple layers as needed. FIG. 1 shows an example in which the wiring board of the present invention is used for a BGA board. PCB on land pad (11)
A solder ball (17) for mounting is formed. Solder bumps (17) are formed on the mounting pads (13) by solder reflow after printing a solder paste in advance. A solder resist (12) is formed on the mounting surface of the semiconductor element of the wiring board so that the terminal electrodes of the semiconductor element are not short-circuited by the leaked solder. The semiconductor element (18) is connected to the solder bump (17) by a terminal electrode (20) provided on the mounting surface of the semiconductor (18). The mounting portion is filled with an underfill material (21) for stress relaxation.

A multilayer wiring using a substrate having a build-up layer formed by alternately laminating insulating layers and wiring layers on at least one surface of a core substrate and having an opening formed to penetrate the core substrate and the build-up layer. The substrate may be manufactured, for example, as follows (FIGS. 11 to 25). Here, a description will be given below using an embodiment of a so-called “FC-PGA” structure shown in FIG.

As shown in FIG. 12, an FR-5 double-sided copper-clad core substrate in which a copper foil (200) having a thickness of 18 μm is adhered to an insulating substrate (100) having a thickness of 0.4 mm is prepared. The characteristics of the core substrate used here are as follows: Tg (glass transition point) by TMA is 175 ° C., CTE (coefficient of thermal expansion) in the direction of the substrate surface is 16 ppm / ° C., CTE (coefficient of thermal expansion) in the direction perpendicular to the substrate surface is 50 ppm / ° C, dielectric constant ε at 1MHz
Is 4.7 and tan δ at 1 MHz is 0.018.

A photoresist film is attached to the core substrate and exposed and developed to provide an opening having a diameter of 600 μm and an opening (not shown) corresponding to a predetermined wiring shape. The copper foil exposed at the opening of the photoresist film is removed by etching using an etching solution containing sodium sulfite and sulfuric acid. The photoresist film is peeled off to obtain a core substrate having an exposed portion (300) as shown in FIG. 13 and an exposed portion (not shown) corresponding to a predetermined wiring shape.

A commercially available etching apparatus (manufactured by MEC)
After the surface of the copper foil is roughened by performing an etching process using a CZ processing device), a thickness of 35 mainly composed of epoxy resin is obtained.
A μm insulating film is attached to both sides of the core substrate. Then, curing is performed under the condition of 170 ° C. × 1.5 hours to form an insulating layer. The properties of the insulating layer after this curing are TMA
(Glass transition point) by DMA is 155 ° C., Tg (glass transition point) by DMA is 204 ° C., CTE (thermal expansion coefficient) is 66 ppm / ° C., dielectric constant ε at 1 MHz is 3.7, and tan δ at 1 MHz is 0.1. 033, 30
Weight loss at 0 ° C. is −0.1%, water absorption is 0.8%, moisture absorption is 1%, Young's modulus is 3 GHz, and tensile strength is 63M.
Pa and the elongation are 4.6%.

As shown in FIG. 14, via holes (50) for interlayer connection are formed in the insulating layer (400) using a carbon dioxide gas laser.
0) is formed. The form of the via hole is in the shape of a horn having a surface layer portion diameter of 120 μm and a bottom portion diameter of 60 μm. Further, by increasing the output of the carbon dioxide laser, a through hole (600) having a diameter of 300 μm is formed so as to penetrate the insulating layer and the core substrate. The inner wall surface of the through hole has undulations (not shown) peculiar to laser processing. And
After the substrate is immersed in a catalyst activation solution containing palladium chloride, electroless copper plating is applied to the entire surface (not shown).

Next, an 18 μm thick copper panel plating (700) is applied to the entire surface of the substrate. Here, a via hole conductor (800) for electrically connecting the layers is provided in the via hole.
Is formed. In the through hole, a through hole conductor (900) for electrically connecting the front and back surfaces of the substrate is formed. An etching treatment is performed by a commercially available etching treatment device (CZ treatment device manufactured by MEC) to roughen the surface of the copper plating. Thereafter, a rust preventive treatment (trade name: CZ treatment) is performed with a rust preventive agent of the company to form a hydrophobic surface, and the hydrophobic treatment is completed. The contact angle 2θ of water on the surface of the conductor layer subjected to the hydrophobic treatment was measured using a contact angle measuring device (trade name: CA
-A, manufactured by Kyowa Kagaku Co., Ltd.), and the contact angle 2θ was 101 degrees.

The nonwoven paper is placed on a pedestal with a vacuum suction device, and the substrate is placed on the pedestal. A stainless steel filling mask having a through hole is provided thereon so as to correspond to the position of the through hole. Next, a paste for filling through holes containing a copper filler is placed, and filling and filling are performed while pressing a roller squeegee.

As shown in FIG. 15, the paste (1000) for filling the through holes filled in the through holes was
Temporarily cure under the condition of 20 ° C. × 20 minutes. Next, as shown in FIG. 16, after polishing the surface of the core substrate using a belt sander (rough polishing), the core substrate is buff-polished (finished polishing) and flattened (not shown), and 150 ° C. × 5 hours. And the filling process is completed. A part of the substrate which has completed the filling process is used for an evaluation test for filling properties.

As shown in FIG. 17, a mold (not shown).
Is used to form a through hole (110) of 8 mm. FIG.
As shown in FIG. 8, a masking tape (12
Paste 0). Then, as shown in FIG. 19, a multilayer chip capacitor (130) is mounted on the masking tape exposed in the through hole (110) by using a chip mounter.
Place them. This multilayer chip capacitor is 1.2 mm
It consists of a laminate (150) of × 0.6 mm × 0.4 mm, with the electrodes (140) protruding 70 μm from the laminate.

As shown in FIG. 20, the embedded resin (1) of the present invention is inserted into a through hole in which a multilayer chip capacitor is arranged.
60) is filled using a dispenser (not shown). The embedded resin is subjected to a primary heating step of 80 ° C. × 3 hours,
In the secondary heating step, defoaming and thermal curing are performed at 170 ° C. for 6 hours.

As shown in FIG. 21, the surface of the cured embedded resin is roughly polished using a belt sander, and then finish polished by lap polishing. The end surface of the electrode of the chip capacitor is exposed on the polished surface. Next, the temporarily cured filling resin is cured at 150 ° C. for 5 hours.

Thereafter, the polished surface of the embedded resin is roughened using a swelling solution and a KMnO ₄ solution. After activating the roughened surface with a Pd catalyst, copper plating is performed in the order of electroless plating and electrolytic plating. As shown in FIG. 22, the plating layer formed on the embedded resin is electrically connected to the end surfaces of the electrodes of the chip capacitor. A resist is formed on the plating surface, and a predetermined wiring pattern is patterned. Unnecessary copper is removed by etching using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is peeled off to complete the formation of the wiring as shown in FIG. An etching treatment is performed by a commercially available etching treatment device (CZ treatment device manufactured by MEC Corporation) to roughen the surface of the copper plating of the wiring.

A film (190) serving as an insulating layer thereon
Is laminated and thermally cured, and then irradiated with a carbon dioxide laser to form via holes for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent as described above, and a predetermined wiring (201) is formed in the same manner. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and the mounting pattern of the semiconductor element is formed by exposing and developing, thereby completing the formation of the solder resist layer (210).
A predetermined wiring (230) and a solder resist layer (24)
0) to form a multilayer printed wiring board before pinning as shown in FIG.

Terminal electrode (201) for mounting a semiconductor element
Is plated in the order of Ni plating and Au plating (not shown). After printing a solder paste made of low melting point solder thereon, a solder bump (220) for mounting a semiconductor element is formed through a solder reflow furnace.

On the other hand, a solder bump (260) for pinning through a solder reflow furnace is formed after printing a solder paste made of high melting point solder on the side opposite to the semiconductor element mounting surface. Fix the pin (2) on the jig (not shown).
In the state where the substrate is placed on top of setting the 50), pinning is performed through a solder reflow furnace (not shown), and as shown in FIG. 25, the FC-P before mounting the semiconductor element is mounted.
A GA type multilayer printed wiring board is obtained. When the amount of displacement of the tip of the pin attached to the area corresponding to the opening embedded with the embedding resin from a predetermined position was measured using a projector, a favorable result of 0.1 mm or less was obtained.

The semiconductor device (27) is mounted on the semiconductor device mounting surface.
The semiconductor element is mounted through a solder reflow furnace under a temperature condition in which only the low-melting-point solder is melted by disposing 0) at a mountable position. After the mounting portion is filled with an underfill material with a dispenser, it is thermally cured to obtain a semiconductor device using an FC-PGA type multilayer printed wiring board on which a semiconductor element as shown in FIG. 11 is mounted.

Examples of the electronic component include a chip resistor, a chip capacitor, a chip inductor and the like.
Since the electronic component is small and has a sufficient capacity, it is preferable to use a ceramic laminated type. The amount of protrusion of the electrodes of the embedded electronic component from the surface of the ceramic body to the surface of the embedded resin is preferably 20 to 150 μm at least on the mounting surface side of the semiconductor element.
Preferably, 20 to 15 electrodes on both sides of the electronic component are used.
It is good to protrude 0 μm. This is because the embedded resin flows well between the electrodes on both surfaces of the electronic component. If the protruding amount of this electrode is smaller than this range, the filler of the embedding resin is caught in the gap and it is difficult to sufficiently fill the gap. Conversely, if the protruding amount of this electrode is larger than this range, the electrode itself tends to peel off due to stress. Is not preferable in terms of reliability.

The preferable range of the protrusion amount of the electrode is preferably 30 to 100 μm, and more preferably 50 to 80 μm. This is because a filler having a relatively large particle size can be added, and the fluidity of the embedded resin itself can be improved, so that the embedded resin flows very well into the gap between the opening and the electronic component.

The surface of the electrode of the electronic component has a ten-point average roughness R
z is 0.3 to 20 μm, preferably 0.5 to 10 μm,
More preferably, the thickness is 0.5 to 5 μm. This is because the embedded resin penetrates into the irregularities on the electrode surface and has an anchor effect of improving the adhesion. The control of the ten-point average roughness Rz is not particularly limited, and may be performed by a known method such as a micro-etching method or a blackening process.

In the wiring board of the present invention, the mounting position of the semiconductor element can be mounted almost directly above the electronic component, so that the area of the board can be reduced. For example, by embedding a chip capacitor and incorporating a capacitor to form a decoupling capacitor, the wiring length from the power supply layer and the ground layer to the decoupling capacitor is reduced to reduce extra inductance, thereby reducing switching noise. Can be effectively reduced.

The term “substantially directly above” includes not only the case where the semiconductor element is located directly above the electronic component but also the case where the electronic component is located directly above only the periphery of the electrode connected to the semiconductor element. It is a concept. This is because if the electrode of the semiconductor element and the electrode of the potential component are in a positional relationship that can be connected substantially vertically through the via conductor, the effects described in the preceding paragraph can be obtained.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. The embedding resin is prepared by weighing and mixing each component so as to have the composition shown in Table 1, and kneading the mixture with a three-roll mill. Here, the details of the items described in Table 1 are as follows.

Epoxy resin: "HP-4032D": high-purity naphthalene-type epoxy resin (manufactured by Dainippon Ink) "E-807": bisphenol F-type epoxy resin (manufactured by Yuka Shell) "YL-980": Bisphenol A type epoxy resin (made by Yuka Shell)-"E-152": Cresol novolak epoxy resin (made by Yuka Shell)

Curing agent: "QH-200": acid anhydride curing agent (manufactured by Zeon Corporation) "B-570": acid anhydride curing agent (manufactured by DIC) "B-650": acid anhydride -Based curing agent (manufactured by DIC)-"YH-306": acid anhydride-based curing agent (manufactured by oil-based shell epoxy)-"YH-307": acid anhydride-based curing agent (manufactured by oil-based shell epoxy)-" LX1N ": Modified amine-based curing agent (manufactured by Yuka Shell Epoxy)

Curing accelerator: The curing accelerator is used in an amount of 0.1% by weight based on the total of 100% by mass of the epoxy resin, the inorganic filler and the curing agent.
5% by mass is added. -"2P4MHZ": imidazole-based curing agent (manufactured by Shikoku Chemicals)

Inorganic filler "TSS-6": Silane filler treated with silane coupling (Tatsumori: maximum particle diameter 24 μm based on particle size distribution)

[0052]

[Table 1]

Using these compositions, test samples are prepared as follows, and the evaluation tests shown below are performed. As the core substrate, a 0.8 mm thick FR-5 substrate is used.
The core substrate is provided with a through hole of a predetermined size using a mold. After attaching the back tape to one side of the core board,
Place the tape with the back tape on the bottom. A chip capacitor is arranged at a predetermined position on the adhesive surface of the pack tape in the opening from the other surface using a chip mounter. The resin shown in Table 1 is poured into the gap between the chip capacitor disposed in the opening and the opening using a dispenser.

The embedding resin was heated at 100 ° C. for 80 minutes for 12 minutes.
The thermosetting is performed under three-stage conditions of 0 ° C. × 60 minutes and 160 ° C. × 10 minutes. The surface of the hardened embedded resin is roughly polished by using a belt sander, and then finish-polished by lap polishing. Then, a via hole is formed by using a carbon dioxide gas laser to expose the electrode of the chip capacitor.

Thereafter, the exposed surface of the embedded resin is roughened by using a swelling solution and a KMnO ₄ solution. After activating the roughened surface with a Pd catalyst, electroless plating is performed, followed by electrolytic plating, followed by copper plating in a thickness of 35 μm. A resist is formed on the plating surface, and a predetermined wiring pattern including a wiring pattern for measuring adhesion strength having a width of 10 mm is patterned. Unnecessary copper is removed by etching using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is stripped to complete the formation of the wiring layer. The test sample on which the formation of the wiring layer is completed is used for measuring the adhesion strength of the wiring layer.

Next, a test sample for reliability evaluation is prepared. After laminating a film to be an insulating layer on the test sample on which the formation of the wiring layer has been completed and thermosetting, a laser is irradiated to form a via hole for interlayer connection.
The surface of the insulating layer is roughened using the same oxidizing agent, and a predetermined wiring pattern is formed by the same method. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and the mounting pattern of the semiconductor element is formed by exposing and developing, thereby completing the formation of the solder resist layer. The terminal electrodes for mounting the semiconductor elements are plated in the order of Ni plating and Au plating. After that, the semiconductor element is mounted through a solder reflow furnace. After the mounting portion is filled with an underfill material with a dispenser, it is thermally cured to complete the preparation of a test sample for reliability evaluation.

[0057] Ten-point average roughness (Rz) evaluation A cross section of the interface between the embedded resin and the wiring layer was observed with a scanning microscope (SEM), and a photograph at a magnification of 500 was taken.
In addition, the photograph is enlarged to four times the size. From the magnified photographic image, the shape of the interface between the embedded resin and the wiring layer is defined as a cross-sectional curve, and the ten-point average roughness (Rz) is determined in accordance with 3.5.1 of JIS B0601. However, reference length (L)
Is set to 0.16 mm.

[0058] Adhesion Evaluation A 10 mm wide wiring pattern for adhesion evaluation is peeled off while being pulled in a direction perpendicular to the substrate, and the strength at this time is defined as the adhesion strength. Adhesion strength is 0.4kg / cm
It is determined that the above is preferable, but 0.6 kg / cm
It is more preferable to have the above. Table 2 shows the measurement results.

[0059] Reliability Evaluation The obtained evaluation sample was subjected to a heat cycle test (−55 ° C.).
＋ １ + 125 ° C .: 1000 cycles) and PCT (pressure cooker) test (121 ° C. × 2 atm: 168 hours). By observing the surface of the evaluation sample after the test and observing the cut surface, the presence or absence of resin cracks and resin peeling near the chip capacitor and the presence of other problems were confirmed.
Evaluate the effectiveness of the embedding resin. Those with a pass rate of 85% or more are judged to be good. Table 2 shows the results.

[0060]

[Table 2]

The results show that the ten-point average roughness Rz is 2 to 6 μm.
It can be seen that good adhesion strength can be obtained in the range. Also, it can be seen that good reliability can be obtained when the amount of the inorganic filler is in the range of 35 to 65% by volume.

A comparison between Sample No. 4 using the naphthalene type epoxy resin and Sample No. 6 using the bisphenol A type epoxy resin shows that Sample No. 4 using the naphthalene type epoxy resin has a smaller ten-point average roughness. Even so, it can be seen that the same adhesion strength is obtained and the reliability test pass rate is high. Also, comparing Sample No. 5 using the naphthalene type epoxy resin with Sample No. 7 using the bisphenol F type epoxy resin, Sample No. 5 using the naphthalene type epoxy resin has the same ten point average roughness. Nevertheless, it can be seen that higher adhesion strength is obtained and the reliability test pass rate is high. This also indicates that it is better to use a naphthalene type epoxy resin.

A comparison between Sample No. 2 using the acid anhydride-based curing agent and Sample No. 3 using the modified amine-based curing agent shows that
It can be seen that Sample No. 2 using an acid anhydride as the curing agent can have higher adhesion strength and reliability test pass rate even with the same composition ratio.

[0064]

According to the present invention, it is possible to obtain an electronic component embedded type wiring board using an embedded resin having good adhesion between a wiring layer such as copper plating and the embedded resin. By regulating the irregularities at the interface between the wiring layer and the embedded resin to a predetermined ten-point average roughness, the adhesion of the wiring layer due to the anchor effect can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example in which a wiring board of the present invention is applied to a BGA board.

FIG. 2 is an explanatory view showing one embodiment of a method of manufacturing a wiring board according to the present invention.

FIG. 3 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 4 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 5 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 6 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 7 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 8 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 9 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 10 is an explanatory diagram showing an example in which the wiring board of the present invention is applied to a BGA board.

FIG. 11 is an explanatory diagram of a semiconductor device using an FC-PGA type multilayer printed wiring board which is one embodiment of the present invention.

FIG. 12 is a schematic view of a copper-clad core substrate having a thickness of 400 μm.

FIG. 13 is an explanatory view showing a state after patterning of a copper-clad core substrate having a thickness of 400 μm.

FIG. 14 is an explanatory diagram showing a state in which via holes and through holes are formed in a substrate in which insulating layers are formed on both surfaces of a core substrate.

FIG. 15 is an explanatory diagram showing a state after panel plating is applied to a substrate having an insulating layer formed on both surfaces of a core substrate.

FIG. 16 is an explanatory view of a substrate in which through holes are filled and filled.

FIG. 17 is an explanatory view showing a substrate formed by punching through holes.

FIG. 18 is an explanatory view showing a state in which a masking tape is attached to one surface of a substrate on which a through hole is punched and formed.

FIG. 19 is an explanatory view showing a state in which a multilayer chip capacitor is arranged on a masking tape exposed in a through hole.

FIG. 20 is an explanatory view showing a state in which a filling resin is filled in a through hole.

FIG. 21 is an explanatory view showing a state where a substrate surface is polished and flattened.

FIG. 22 is an explanatory view showing a state where a polished surface of a substrate is subjected to panel plating.

FIG. 23 is an explanatory diagram showing a state in which wiring is hatched.

FIG. 24 is an explanatory view showing a state in which a build-up layer and a solder resist layer are formed on a substrate.

FIG. 25 is an explanatory diagram of an FC-PGA type multilayer printed wiring board which is one embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 core substrate 2 through hole 3 back tape 4 electronic component 5 electrode of electronic component 6 embedded resin 60 flat surface 61 rough surface

Continued on the front page F-term (reference) 4J002 CD041 CD051 CD061 DJ006 DJ016 EL137 FD016 FD147 GQ05 5E346 AA02 AA06 AA12 AA43 CC04 CC09 CC32 CC58 DD02 DD25 DD32 DD44 DD48 EE08 EE19 FF04 FF07 FF15 GG15 GG17 GG18 GG22 GG17 GG24GG

Claims (4)

[Claims] In a wiring board in which an electronic component is embedded by using an embedded resin inside the substrate, a ten-point average roughness Rz of irregularities formed at an interface between the embedded resin and the wiring layer is 2 to 2.
A wiring board having a thickness of 6 μm. 2. The wiring according to claim 1, wherein the embedding resin contains at least one kind of inorganic filler, and the content of the inorganic filler is 35 to 65% by volume. substrate. 3. A thermosetting resin comprising a thermosetting resin, a curing agent thereof, and at least one kind of inorganic filler, wherein the thermosetting resin is at least one selected from a bisphenol epoxy resin, a naphthalene type epoxy resin and a phenol novolak resin. 3. The method according to claim 1, wherein the content of the inorganic filler is 35 to 65% by volume, and the curing agent is an embedding resin which is an acid anhydride-based curing agent.
The wiring board according to claim 1. 4. A build-up layer in which insulating layers and wiring layers are alternately laminated on at least one surface of a core substrate as the substrate, and the opening penetrates the core substrate and the build-up layer. The wiring substrate according to claim 1, wherein the wiring substrate is formed using a wiring substrate.