JP2002156961A - Display circuit - Google Patents

Abstract

(57) [Summary] [Purpose] In a display circuit that displays bitmap image data drawn on an image memory on a display device, the contents of the display memory are not rewritten and synchronized with dots, lines, and frames. Provided is a circuit for performing rotation, enlargement, and reduction display. An address counter output and a timing signal are input, multiplication is performed in a horizontal or vertical retrace period or the like, and an address of a display memory is calculated by cumulative addition for each dot and line. [Effect] A smooth rotation moving image can be displayed by performing multiplication once for one display frame or one display line and accumulative addition once for each dot or one display line without performing high-speed multiplication for each dot clock. Can be. The multiplier may operate at a low speed, and the multiplier can perform a time-division operation, so that the circuit scale can be reduced and the multiplier can be manufactured at low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display circuit for rotating, enlarging and reducing bitmap image data drawn on an image memory on a display device. Is related to an address operation circuit that calculates

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional display circuit supplies the output of a horizontal and vertical display address counter to a display memory, and performs display on a display device using the output of the display memory. Therefore, when performing rotation, enlargement, or reduction display, the central processing unit 14 (hereinafter referred to as CPU) performs data processing, or performs arithmetic processing of data in the arithmetic circuit 8 and performs rotation, enlargement, or reduction processing on the display memory. Later data was being written.

[0003]

The above-mentioned prior art has the following problems.

That is, the rotation, enlargement and reduction of the display data is performed by the CPU by directly rewriting the contents of the display memory directly or through an arithmetic circuit.
Processing takes time, and it is not possible to control the rotation angle, enlargement, and reduction ratio accurately in synchronization with the display timing in pixel units, raster units, and frame units. Therefore, a smooth rotating moving image in which the rotation angle is changed for each frame, and a display with a perspective with different magnifications in units of pixels and rasters cannot be obtained.

[0005]

A display circuit according to the present invention comprises:
(1) The output of the address counter is a data input, and a vertical synchronization signal or a signal synchronized with a frame, a horizontal synchronization signal or a signal synchronized with a line, a dot clock or a signal synchronized with a pixel, and rotation, enlargement or reduction display. Having an arithmetic circuit that outputs an address of display data drawn on the display memory,
It is characterized by having means for reading out the data at the address and displaying the data. The arithmetic circuit includes (2) means for multiplying the address, rotation, enlargement, and reduction parameters during the vertical flyback period, and the result of the multiplication and rotation, enlargement, and reduction at a dot clock rate or a clock rate that is an integral multiple of the dot clock.
Means for performing cumulative addition of reduction parameters, means for performing a horizontal synchronization signal or a signal synchronized therewith as a clock, and performing cumulative addition of rotation, enlargement, and reduction parameters; or Means for multiplying rotation, enlargement, and reduction parameters; means for performing cumulative addition of the result of the multiplication and rotation, enlargement, and reduction parameters at a dot clock rate or a clock rate that is an integer multiple of the same, or a horizontal synchronization signal or Means for cumulatively adding the result of the multiplication and rotation, enlargement, and reduction parameters using the synchronized signal as a clock; or (4) means for multiplying the address, rotation, enlargement, and reduction parameters during one frame period; Means for latching the result of the synchronization with a vertical synchronization signal or a signal synchronized with one frame; Means for performing cumulative addition of output, rotation, enlargement, and reduction parameters of the latch at a clock rate or a clock rate that is an integral multiple of the clock, or the result of the multiplication, rotation, and enlargement using a horizontal synchronization signal or a signal synchronized therewith as a clock. Means for performing cumulative addition of reduction parameters or (5) means for multiplying address, rotation, enlargement and reduction parameters during one line period, and latching the result of the multiplication with a horizontal synchronization signal or a signal synchronized with one line Means for outputting, rotating, enlarging, and outputting the latch at a rate of a dot clock or a clock of an integer multiple thereof.
The present invention is characterized in that it has means for cumulatively adding reduction parameters or means for cumulatively adding the result of the above multiplication and rotation, enlargement, and reduction parameters using a horizontal synchronization signal or a signal synchronized therewith as a clock. Further (6)
The arithmetic circuit inputs a timing signal synchronized with a display frame or a display line and operates in a time-division manner by a multiplexer. (7) A means for operating a multiplication of an address and rotation, enlargement and reduction parameters in a time-division manner by a multiplexer, and a dot clock. Or a means for performing cumulative addition of the result of the multiplication and rotation, enlargement, and reduction parameters at a clock rate that is an integral multiple of the clock, or a result of the multiplication and rotation, enlargement, It is characterized by having means for performing cumulative addition of reduction parameters.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a display circuit according to the present invention, wherein 1 is an arithmetic circuit for performing rotation, enlargement, and reduction display. The display memory 2 is an example of a case where the display memory 2 is constituted by a read / write memory (hereinafter referred to as a RAM). In the RAM, data of an original image that has not been subjected to a process such as rotation is written from the CPU 7. The horizontal display address counter 4 and the vertical address counter 5 count addresses corresponding to the display positions of the display device 3, and the position in the horizontal direction is a dot clock DC.
LK and the position in the vertical direction are counted using the horizontal synchronization signal HSYNC as a clock.

When processing such as rotation is not performed, the outputs of these address counters 4 and 5 are given to the display memory as addresses as they are, and the corresponding data is sent to the display device. On the other hand, when performing rotation, enlargement, or reduction display, the arithmetic circuit 1 performs arithmetic processing on the output of the address counter, converts the output, and gives the display address to the display memory 2. Data corresponding to the converted display address is read from the display memory, and as a result, the display device is rotated, enlarged, or reduced in size.

Here, an arithmetic expression for performing rotation, enlargement or reduction display performed by the arithmetic circuit 1 will be briefly described. The parameter register 6 provides parameters for determining a rotation angle, a rotation center, and a ratio of enlargement and reduction. The arithmetic circuit 1 performs the operation of the following arithmetic expression called affine transformation.

[0010]

(Equation 1)

The matrix is expanded and expressed as follows.

X2 = A (X1-X0) + B (Y1-Y0) + X0 Expression (2) Y2 = C (X1-X0) + D (Y1-Y0) + Y0 Expression (3) In the above expression, X0 and Y0 are the centers of rotation, X1 and Y1 are output address values from the address counter, X2 and Y2 are address values on the memory after processing such as rotation, and A, B,
C and D are parameters corresponding to the rotation angle, the enlargement and the reduction ratio. If the rotation angle is θ and the enlargement and reduction ratio in the X direction and the enlargement and reduction ratio in the Y direction are α and β, respectively, they are expressed as follows. It is.

A = α cos θ Expression (4) B = −β sin θ Expression (5) C = α sin θ Expression (6) D = β cos θ Expression (7) Output X1, Y of address counter
It is sufficient to input 1 and calculate the address on the memory according to the above-mentioned arithmetic expression.

FIGS. 3 and 4 are circuit diagrams of the arithmetic circuit of the display circuit according to the present invention. FIG. 3 embodies the equation (2), and FIG. 4 embodies the equation (3). The addresses X2 and Y2 after the operation are output from the respective circuits. In the drawing, the case where the address values X and Y are both 8 bits, that is, the case where the display resolution is 256 dots for both X and Y is used as an example. Also, the case of 8-bit precision as an example of the rotation, enlargement, and reduction parameters has been described.

In FIG. 3, center coordinates X0 and Y0 of rotation are shown.
Are inverted for each bit by bit inversion circuits 15 and 19, respectively, and 1 is added by +1 circuits 16 and 20 to become a negative number represented by 2's complement. Next, the output X of the address counter
1, Y1 and these results are added to adders 17, 21 respectively.
Is added. The addition result is multiplied by the parameters A and B relating to the rotation angle, the enlargement and the reduction ratio by the multipliers 18 and 22, and the result and X0 are added by the adder 23 to obtain the address of the memory after the rotation, enlargement and reduction processing. X
It becomes 2. As is clear from the comparison between the above equation (2) and the operation of FIG. 3, FIG. 3 is a circuit obtained by converting equation (2) as it is. The equation (3) for determining Y2 can be implemented in the same manner as in FIG. In this embodiment, Y2 is shifted by 8 bits and added to X2 to become the address of the display memory in FIG.

Since FIGS. 3 and 4 have almost the same circuit configuration, a high-speed operating multiplier or adder is used.
In a low-resolution display device, a circuit can be shared and used in a time-sharing manner, and the circuit scale can be reduced. FIG. 5 is an example of this circuit. Reference numerals 33, 34, and 35 denote multiplexers for setting rotation, enlargement, and reduction parameters corresponding to the "H" or "L" period of the dot clock to A, B, X0, or C, D, or X for X2, respectively. Switch to Y0. The output of the operation result is taken into DFFs 45 and 46 at the falling and rising edges of DCLK, respectively. FIG. 6 shows this situation in a timing chart.

As described above, according to the present invention, the CP
U does not need to rewrite the display memory 2 for rotation, enlargement, and reduction. So, for example, when we look at rotation,
By simply rewriting only four parameters A, B, C, and D, for example, during the vertical blanking period, a smooth rotating moving image can be performed. Also, as is clear from FIG. 1, the horizontal display address counter 4 uses the dot clock DCL.
K, the vertical display address counter 5 outputs the horizontal synchronization signal HS.
Operates at YNC. Therefore, the four parameters are DCL
If the timing is changed by K or HSYNC, various shapes of perspective display can be realized without changing the original image data.

Next, another embodiment will be described. In the above-described embodiment, the display address after the rotation processing can be obtained instantaneously irrespective of the scanning order of the horizontal and vertical display address counters 4 and 5, but there are still points to be improved. Was.

That is, in the embodiments of FIGS. 3 and 4, four multipliers operating at the dot clock cycle are required, and in the example of FIG. 5, two multipliers operating at a half cycle of the dot clock are required. there were. Every year, display devices tend to have high resolution and multi-color display, and there are devices that display 1 million pixels in full color of 24 bits, and the display circuits are also required to have performance corresponding to this. In the above embodiment, 8
The case of low resolution of bit address was explained as an example,
In order to obtain an accurate operation result in such a high-resolution display, it is necessary to perform multiplication and addition of 10 to 20 bits. On the other hand, assuming that the time required for display is 60 to 70 Hz for one display frame, the dot clock is 60 to 70 MHz, and the time allotted to one pixel is about 15 ns. In such a short time, in order to operate at high speed even for carry in the above calculation, especially multiplication, it is necessary to form a circuit using elements that operate at high speed or to form a large-scale carry circuit, This leads to an increase in manufacturing cost and an increase in power consumption. Therefore, there remains a problem that hinders the manufacture of a display device capable of rotating, enlarging, and reducing display with high resolution and multicolor display.

A description will now be given of another example of the arithmetic circuit of the display device according to the present invention, which can obtain the same operation result even with a low-speed multiplier.

The above affine transformation equation (2),
The modification of (3) is as follows.

X2 = AX1 + BY1 + Xi Expression (8) Y2 = CX1 + DY1 + Yi Expression (9) Here, Xi and Yi are initial values, and Xi = (1-A) X0-BY0 expression ( 10) Yi = −CX0 + (1-D) Y0 Expression (11)

Dot sequential display devices such as CRT display devices,
In the case of a line sequential display device such as an LCD display device, the display address counter is counted up from zero sequentially. The output values X1 and Y1 of the counter are zero at the beginning of each frame, X1 is incremented by one for each dot clock, and Y1 is incremented by one for each horizontal synchronization signal. Therefore, the initial value X is calculated in advance according to equations (10) and (11).
If i and Yi are obtained, the addresses to be obtained after the operation can be obtained as X2 and Y2 as follows. That is, for the horizontal address X2, the initial value X
i is A for each dot clock, and B is for each horizontal synchronization signal.
By adding the vertical address Y2
As for the initial value Yi, C is set for each dot clock,
It is obtained by adding D for each horizontal synchronization signal. The actual memory address is obtained by bit shifting Y2 and X
2 is added to it. Therefore, the operation for each dot clock is processed only by addition, and there is no need for multiplication.

In the case of a dot-sequential display device such as a CRT display device and a line-sequential display device such as an LCD display device, if the display address counter counts up from zero sequentially, the arithmetic circuit The scale can be small. Another embodiment of the present invention will be described with reference to FIG. In addition to the above-described effects of the present invention, there is an advantage that it is not necessary to use a high-speed multiplier that requires a large-scale circuit and a device that operates at a high speed, thereby realizing low power consumption and low cost. It is.

Hereinafter, an example of an actual circuit will be described in more detail with reference to a block diagram, a timing chart, and the like.

First, a circuit for calculating the initial values Xi and Yi will be described. As described above, the initial values Xi and Yi are determined by the equations (1)
0) and (11). FIGS. 7 and 8 each embody these, and show a case where both the address and the parameter have an 8-bit precision as in the above-described embodiment.

In FIG. 7, parameters A and B for rotation, enlargement, and reduction are inverted for each bit by bit inversion circuits 47 and 51, respectively, and one is added by +1 circuits 48 and 52, and a negative value of two's complement expression is added. It becomes a number. Next, for A expressed as a negative number, 1 is added, and the center coordinates X0 and Y0 of the rotation and their results are multiplied by multipliers 50 and 53, respectively, and these results are added by an adder 54 to be added to an initial value Xi. Becomes The same applies to Yi in FIG.
The circuit can be formed as follows.

Next, a circuit for performing addition at the rates of the dot clock DCLK and the horizontal synchronizing signal HSYNC to calculate the target addresses X2 and Y2 will be described.

FIGS. 9 and 10 are circuit diagrams of equations (8) and (9), respectively, and have exactly the same circuit configuration.
The initial value Xi calculated by the circuit of FIG. 7 is input to the multiplexer 65, becomes the data input of the DFF 66 during the vertical flyback period, and the rising edge of the vertical synchronization signal VSYNC is taken in as a clock. In the vertical display period, at the timing of the horizontal display period, the output of the DFF 66 and the parameters A for rotation, enlargement, and reduction are selected, added by the adder 64 and given to the data input, and the DFF 66 is supplied by the rising edge of the dot clock DCLK.
It is taken in. This is a circuit operation corresponding to the operation of the first term in Expression (8). In the vertical display period, B is selected and added by the multiplexer 63 during the horizontal flyback period.
It is inputted and taken into the DFF 66 at the rising edge of the horizontal synchronization signal HSYNC. This is a circuit operation corresponding to the operation of the second term in Expression (8). In this way, the rotation, enlargement, and reduction parameters A or B are cumulatively added to the initial value Xi to obtain the address X2 to be obtained. FIG. 11 is a timing chart showing the operation of the circuit of FIG.

The circuit operation principle shown in FIG. 10 is exactly the same except that the initial value of the given address and the rotation, enlargement and reduction parameters are different, and the address Y2 can be calculated by cumulative addition.

As described above, the calculation result of the address at a specific display timing can be obtained by multiplying and adding the initial values of Expressions (10) and (11) in advance.
The initial value can be obtained by cumulatively adding the corresponding rotation, enlargement, and reduction parameters using the dot clock and the horizontal synchronization signal as clocks in synchronization with the count of the address counter. As is clear from FIGS. 9 and 10, this circuit is composed of a flip-flop for latching data, a multiplexer and an adder, so that the circuit scale can be small. In addition, since only the addition operation is performed with the dot clock, it is possible to cope with a high-speed dot clock in high-resolution display.

Next, a description will be given of the operation timing of the operation circuit of the initial value which requires the multiplication operation.

As an example, when a smooth rotating moving image is displayed, the CPU 7 writes the display data of the rotating object in the display memory 2 in advance and sets the rotation angle for each display frame, that is, rotation, enlargement, and reduction. This can be realized by changing the parameters A, B, C, and D. 9 and 10 of the above-described embodiment, the vertical synchronizing signal VSYN is used.
At the rising edge of C, the initial values Xi and Yi are D
These are taken into the FFs 65 and 73. Therefore, parameter rewriting may be performed during the vertical blanking period in which the corresponding display frame period has ended.

FIG. 12 shows this simply. 77 is a rotation, enlargement, reduction parameter A, B, C, D and X0,
This is a parameter register that latches Y0. The CPU detects the beginning of the vertical blanking period by interrupt or polling, generates a write signal, and rewrites the parameter set for the next frame. The arithmetic circuit 78 for the initial values Xi and Yi inputs a new parameter set and calculates an initial value for the next frame. It is sufficient that the calculation result is determined before the rise of the vertical synchronization signal VSYNC.
It is provided to the accumulator circuit of FIG. 9 or FIG.

In the example of FIG. 12, the CPU has to detect the beginning of the vertical blanking period in some way. FIG.
Reference numeral 3 denotes another example, in which the parameter register is in the form of a double buffer register by a latch 80. Therefore, the CPU does not need to detect the beginning of the vertical blanking period, and can rewrite the value of the parameter register at an arbitrary timing. Since the clock of the latch 80 operates at the rising edge of the vertical synchronization signal VSYNC, if the CPU detects this and rewrites the value of the parameter register, the arithmetic circuit 8 for the initial values Xi and Yi
Since 1 has a maximum calculation time of about 16 ms, which is one frame time, the operation speed is not required for the circuit, which is advantageous in terms of configuration.

Next, as another display example, consider a case where the rotation, enlargement, and reduction parameters A, B, C, and D are rewritten for each display line. An image of the object viewed from the front is stored as data in the display memory 2. If the parameter corresponding to the magnification in the X direction is rewritten for each display line, and the magnification is set higher in the upper part of the display and lower in the lower part, the display becomes a display in which the object is leaning forward, and the ratio of the difference between the magnifications Is increased for each frame, a display in which an object falls down without rewriting the display memory can be realized.

In this case, since it is necessary to rewrite the rotation, enlargement, and reduction parameters A, B, C, and D for each display line, the added value obtained by performing the cumulative addition up to the previous line is used for the address calculation. Can not do. It is necessary to set an initial value anew when the parameter is rewritten. As an example, consider a case in which cumulative addition is performed in accordance with parameters set at the start of a frame up to the nth line and parameters are rewritten from the (n + 1) th line. Assuming that the rewritten parameters are A ', B', C ', D' and X0 ', Y0', the affine transformation expression is: X2 = A'X1 + B'Y1 + Xi Expression (12) Y2 = C 'X1 + D'Y1 + Yi Expression (13) Here, Xi and Yi are expressed by Expressions (14) and (15).
, Which is the value when assuming that it is set at the beginning of the frame.

Xi = (1−A ′) X0′−B′Y0 ′ Expression (14) Yi = −C′X0 ′ + (1-D ′) Y0 ′ Expression (15) Actually Is set after the nth line, so that B ′ is n times and A ′ is n × w
The value obtained by cumulative addition is used as an initial value from the (n + 1) th line. Here, w is the number of horizontal dots in one line. Therefore, assuming that the initial values from the (n + 1) th line are Xj and Yj, respectively, Xj = (1−A ′) X0′−B′Y0 ′ + nwA ′ + nB ′ Equation (14) Yj = −C′X0 '+ (1-D') Y0 '+ nwC' + nD 'Expression (15)

The circuit for obtaining the initial value is slightly more complicated than the case of rewriting once for each frame, as shown in FIGS. 14 and 15, respectively. These are obtained by adding arithmetic circuits corresponding to the third and fourth terms of Expressions (14) and (15) to FIGS. 7 and 8.

The circuit of the cumulative addition after calculating the initial value is exactly the same as in FIGS. 9 and 10 described above. 9 and 10, an initial value is set in the vertical retrace period by the multiplexers 65 and 72, except that the initial value is set in the horizontal retrace period. Further, as described with reference to FIG. 13, if the circuit is of a double buffer system and the parameters are latched by the horizontal synchronization signal HSYNC, the calculations in FIGS. 14 and 15 need only calculate the initial value during about 63 μs in one horizontal scanning period. In particular, it is not necessary to form a circuit using high-speed elements. Next, the configuration of an initial value arithmetic circuit that requires a multiplication operation will be further described.

As apparent from the above description, since the multiplication for obtaining the initial value does not need to be performed at the dot clock rate, low-speed elements and circuits may be used. However, for example, when the initial value arithmetic circuits of FIGS. 7 and 8 are provided in parallel, four multipliers are required, and the circuit scale becomes large. Therefore, focusing on the fact that these circuits have exactly the same circuit configuration, it is conceivable to use them in a time-division manner.
FIG. 16 shows an example of the circuit. FRAME in the figure is a signal synchronized with the display frame, and is shown in the present embodiment in the case of a duty of 50%. Multiplexers 102, 1
06, 108 and 112 are “H” or “H” of FRAME.
A or D, X0 or Y0, B or C, Y0 or X0 are respectively selected in accordance with the level of L ". Therefore, the adder 113 outputs Xi in the first half of the display frame and Yi in the second half. , 115 latch these signals and provide them as initial values to the accumulative addition circuits of Fig. 9 and Fig. 10. Even if the circuits are operated in a time-sharing manner, one frame time of display is sufficiently long, so that high-speed operation is required. And the circuit scale can be reduced.

[0042]

As described above, according to the present invention, (1) the rotation, enlargement, and reduction display can be performed on the display device without the CPU rewriting the display memory.

(2) Smooth display of moving images and the like is achieved by multiplication once for one display frame or one display line and cumulative addition once for each dot or one display line without performing high-speed multiplication for each dot clock. Can be realized.

(3) The multiplier may operate at a low speed, and the multiplier can perform a time-division operation. Therefore, the circuit scale can be reduced and the multiplier can be manufactured at low cost.

This has the following effects.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display circuit of the present invention.

FIG. 2 is a block diagram of a conventional display circuit.

FIG. 3 is an arithmetic circuit diagram of the present invention for calculating a horizontal display address on a display memory.

FIG. 4 is an arithmetic circuit diagram of the present invention for calculating a vertical display address on a display memory.

FIG. 5 is an arithmetic circuit diagram of the present invention for calculating horizontal and vertical display addresses on a display memory by a time division operation.

FIG. 6 is a timing chart showing the operation of the circuit of FIG.

FIG. 7 is an arithmetic circuit diagram of the present invention for calculating an initial value of a horizontal display address on a display memory.

FIG. 8 is an arithmetic circuit diagram of the present invention for calculating an initial value of a vertical display address on a display memory.

FIG. 9 is an arithmetic circuit diagram of the present invention for calculating a horizontal display address on a display memory by cumulative addition.

FIG. 10 is an arithmetic circuit diagram of the present invention for calculating a vertical display address on a display memory by cumulative addition.

FIG. 11 is a timing chart showing the operation of the circuit in FIG. 9;

FIG. 12 is a block diagram for giving parameters to the initial value arithmetic circuits in FIGS. 7 and 8;

FIG. 13 is a block diagram in which parameters are assigned to the initial value arithmetic circuits in FIGS. 7 and 8 by a double buffer circuit.

FIG. 14 is an arithmetic circuit diagram of the present invention for calculating the initial value of the n-th line of the horizontal display address on the display memory.

FIG. 15 shows an arithmetic circuit according to the present invention which calculates an initial value of an n-th line of a vertical display address on a display memory.

FIG. 16 is an arithmetic circuit diagram of the present invention for calculating the initial value of the nth line of the horizontal and vertical display addresses on the display memory by a time division operation.

17 is a timing chart showing the operation of the circuit in FIG.

[Explanation of symbols]

1,8 arithmetic circuit 2,9 display memory 3,10 display device 4,11 horizontal display address counter 5,12 vertical display address counter 6,13 parameter register 7,14 central processing unit 15,19,24,28,36, 40, 47, 51, 5
5, 59, 82, 86, 92, 96, 103, 109
Bit inversion circuits 16, 20, 25, 29, 37, 41, 48, 52, 5
6, 60, 83, 87, 93, 97, 104, 110
+1 adder 17, 21, 23, 26, 30, 32, 38, 42, 4
4, 49, 54, 57, 62, 64, 71, 84, 9
1, 94, 101, 105, 113 Adders 18, 22, 27, 31, 39, 43, 50, 53, 5
8, 61, 85, 88, 89, 90, 95, 98, 9
9, 100, 107, 111 multipliers 33, 34, 35, 63, 65, 70, 72, 102,
106, 108, 112 Multiplexer 45, 46, 66, 73, 114, 115 D flip-flop 67, 68, 74, 75 AND gate 69, 76 OR gate 77, 79 Parameter register 78, 81 Initial value operation circuit 80 Latch

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[Procedure amendment]

[Submission date] September 10, 2001 (2001.9.1)
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

(Equation 1) The rotation, enlargement or reduction operation parameters are defined by

(Equation 2) And the center of rotation is

(Equation 3) It is given as is the second address

(Equation 4) Is the first address

(Equation 5) Is defined by affine transformation of
3. The display circuit according to 2.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

Display circuit of the present invention According to an aspect of the table
A display circuit for displaying an image on a display device, comprising:
A display memory in which pixel data of
Read pixel data of the image from the display memory
The first image is displayed on the display device when the
Synchronizes the first generated address string for display
An address counter sequentially generated based on a signal;
Calculation parameters when rotating, enlarging or reducing the first image
A parameter register for storing data, and the first address string sent from the address counter is converted into a second address string based on the operation parameters supplied from the parameter register. sequentially reading out the pixel data from said display memory based on the second address sequence, a display control means for outputting the pixel data read out to the display device, the
It is characterized by having.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

FIG. 1 shows a display circuit according to the present invention, wherein 1 is an arithmetic circuit for performing rotation, enlargement, and reduction display. The display memory 2 is an example of a case where the display memory 2 is configured by a read / write memory (hereinafter, referred to as a RAM ) , and data (pixel data ) of an original image (first image) that has not been subjected to processing such as rotation is stored in the RAM.
Data) is written from the CPU 7. The horizontal display address counter 4 and the vertical address counter 5 count addresses corresponding to the display positions of the display device 3, and the horizontal position is a dot clock DCLK, and the vertical position is a horizontal synchronization signal HSYNC. The counting operation is performed.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

[0008] The display control means may control, when the processing such as rotation is not performed is applied to the display memory as the output as the address of the address counter 4 and 5 (the first address column), the corresponding data display device Sent to
On the other hand, when performing rotation, enlargement, or reduction display, the arithmetic circuit 1
Computes and converts the output of the address counter and gives the display address (second address string) to the display memory 2. Data corresponding to the converted display address is read from the display memory, and as a result, the display device is rotated, enlarged, or reduced in size.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

[0010]

(6)

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Claims (7)

[Claims] A display memory for storing image display data, a raster scan or line sequential scan type display device,
In a display circuit having an address counter for counting addresses on a display device, and performing display such as rotation, enlargement or reduction of display, an output of the address counter is used as a data input, and a signal synchronized with a vertical synchronization signal or a frame. The control input is a horizontal synchronization signal or a signal synchronized with a line, a signal synchronized with a dot clock or a pixel, and parameters of rotation, enlargement or reduction, and outputs an address of display data drawn on the display memory. A display circuit having an arithmetic circuit and having means for reading data at the address and displaying the data. 2. The arithmetic circuit according to claim 1, further comprising means for multiplying an address by a rotation, enlargement, or reduction parameter during a vertical blanking period, and a result of said multiplication at a dot clock rate or a clock rate of an integer multiple of the dot clock rate. And means for performing cumulative addition of rotation, enlargement, and reduction parameters, or means for performing cumulative addition of the result of the multiplication and rotation, enlargement, and reduction parameters using a horizontal synchronization signal or a signal synchronized therewith as a clock. Display circuit. 3. The arithmetic circuit according to claim 1, further comprising: means for multiplying an address and a rotation, enlargement, or reduction parameter during a horizontal flyback period, and a result of said multiplication at a dot clock rate or a clock rate of an integer multiple thereof. And means for performing cumulative addition of rotation, enlargement, and reduction parameters, or means for performing cumulative addition of the result of the multiplication and rotation, enlargement, and reduction parameters using a horizontal synchronization signal or a signal synchronized therewith as a clock. Display circuit. 4. An arithmetic circuit according to claim 1, wherein said means multiplies an address by a rotation, enlargement, or reduction parameter in one frame period, and a result of said multiplication is a vertical synchronization signal or a signal synchronized with one frame. Means for latching, means for performing the output of the latch and accumulative addition of rotation, enlargement, and reduction parameters at a dot clock rate or a clock rate that is an integral multiple of the dot clock, or the above-described multiplication using a horizontal synchronization signal or a signal synchronized therewith as a clock Result and rotation, enlargement,
A display circuit comprising means for performing cumulative addition of reduction parameters. 5. The arithmetic circuit according to claim 1, wherein means for multiplying an address and rotation, enlargement, and reduction parameters in one line period, and a result of the multiplication is a horizontal synchronization signal or a signal synchronized with one line. Means for latching, means for performing the output of the latch and accumulative addition of rotation, enlargement, and reduction parameters at a dot clock rate or a clock rate that is an integral multiple of the dot clock; or A display circuit comprising means for cumulatively adding a result, rotation, enlargement, and reduction parameters. 6. The display circuit according to claim 1, further comprising means for inputting a timing signal synchronized with a display frame or a display line and operating in a time division manner by a multiplexer. 7. The arithmetic circuit according to claim 1, wherein the multiplication of the address and the rotation, enlargement, and reduction parameters is time-divisionally operated by a multiplexer, and the multiplication of the multiplication is performed at a dot clock rate or a clock rate that is an integral multiple of the dot clock rate. Means for performing cumulative addition of the result and rotation, enlargement, and reduction parameters, or means for performing cumulative addition of the result of the multiplication and rotation, enlargement, and reduction parameters using a horizontal synchronization signal or a signal synchronized with the horizontal synchronization signal as a clock. Display circuit.