JP2002152017A - Hysteresis comparator circuit - Google Patents

Abstract

(57) Abstract: In a hysteresis comparator circuit having a high input impedance, the output is stabilized even if noise is mixed in the input potential. SOLUTION: A differential pair including a first transistor QN1 and a second transistor QN2, a third transistor QP5 for amplifying a drain potential of the first or second transistor, and a drain potential of the third transistor Amplifying means 20, a means QP1 and QP2 for applying a positive feedback to the drain of the second transistor based on the drain current of the first transistor, and a first means based on the drain current of the second transistor. Means QP3 and QP4 for applying a positive feedback to the drain of the transistor of
Means for applying a positive feedback to the drain of the third transistor based on the output of the inverting amplifying means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to a hysteresis comparator circuit, and more particularly to a hysteresis comparator circuit having a high input impedance and comparing an input potential with a reference potential.

[0002]

2. Description of the Related Art A comparator circuit compares an input potential applied to one input terminal with a reference potential applied to the other input terminal, and generates an output according to the comparison result. In a normal comparator circuit, if noise is mixed in the input potential, a phenomenon occurs in which the output frequently changes when the input potential approaches the reference potential. In order to avoid such a phenomenon, a hysteresis comparator circuit having a hysteresis characteristic in the comparator circuit is used.

FIG. 6 shows a configuration of a conventional hysteresis comparator circuit. This hysteresis comparator circuit includes an N-channel transistor QN1 connected to one input terminal to which the input potential _VA is applied, and a reference potential V
_And an N-channel transistor QN2 connected to the other input terminal to which _B is applied.

This differential amplifier includes a first current mirror circuit composed of P-channel transistors QP1 and QP2, and a second current mirror circuit composed of P-channel transistors QP3 and QP4. . The first current mirror circuit supplies a part of the drain current flowing from the transistor QN1 to the drain of the transistor QN2.
A part of the drain current flowing from N2 is supplied to the drain of transistor QN1. Thereby, the transistor QN2
And a positive feedback is applied to the drain potential of QN1 to give a hysteresis characteristic to the differential amplifier. The output potential V _C of the differential amplifier is inverted by a P-channel transistor QP5 forming a current mirror circuit together with the transistor QP4, and further output via an inverter circuit 20.

Here, the gate potential (equal to the drain potential) of the N-channel transistor QN3 to which the current source 10 is connected is supplied to the gates of the N-channel transistors QN4 and QN5, and the N-channel transistor QN
4 and QN5 supply current to the circuit connected to each.

[0006]

The above-mentioned hysteresis comparator circuit has a feature that the input impedance is high because the resistance dividing circuit does not exist at the input.
However, the positive feedback amount is not sufficient, in particular due to the slow change in the output voltage V _C of the differential amplifier when smaller than the input voltage V _A is the reference potential V _B, the noise in the input potential is or are mixed Also, the output of the inverter circuit 20 frequently changes.

In view of the above, it is an object of the present invention to stabilize the output of a hysteresis comparator circuit having a high input impedance even if noise is mixed in the input potential.

[0008]

In order to solve the above problems, a hysteresis comparator circuit according to a first aspect of the present invention comprises a first transistor having an input potential applied to a gate and a reference potential applied to a gate. A differential pair including a second transistor, a third transistor for amplifying a drain potential of the first or second transistor, an inverting amplifier for amplifying a drain potential of the third transistor, Based on the drain current of the transistor
Means for applying a positive feedback to the drain of the first transistor, and the first means based on the drain current of the second transistor.
Means for applying positive feedback to the drain of the third transistor, and means for applying positive feedback to the drain of the third transistor based on the output of the inverting amplifier.

A hysteresis comparator circuit according to a second aspect of the present invention is a differential pair including a first transistor whose gate is supplied with an input potential and a second transistor whose gate is supplied with a reference potential. Amplifying means for amplifying the drain potential of the first or second transistor; and amplifying means for a drain of the second or first transistor based on a drain current of the first or second transistor and an output potential of the amplifying means. Means for applying positive feedback.

Further, a hysteresis comparator circuit according to a third aspect of the present invention is a differential pair including a first transistor having a gate to which an input potential is applied and a second transistor having a gate to which a reference potential is applied. And the first or second
Amplifying means for amplifying the drain potential of the transistor of
Means for applying a positive feedback to the drain of the first or second transistor based on the input potential or the reference potential and the output potential of the amplifying means.

According to the present invention constructed as described above, in the hysteresis comparator circuit having a high input impedance, positive feedback is applied by utilizing the output of the amplifying means connected to the subsequent stage of the transistors forming the differential pair. Therefore, the output can be stabilized even if noise is mixed in the input potential.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. The same components are denoted by the same reference numerals, and description thereof will be omitted. FIG.
FIG. 2 is a circuit diagram illustrating a configuration of a hysteresis comparator circuit according to the first embodiment of the present invention.

As shown in FIG. 1, this hysteresis comparator circuit includes an N-channel transistor QN1 connected to one input terminal to which an input potential _VA is applied.
When, and a differential amplifier and an N-channel transistor QN2 reference potential V _B is connected to the other input terminal being applied.

This differential amplifier includes a first current mirror circuit composed of P-channel transistors QP1 and QP2, and a second current mirror circuit composed of P-channel transistors QP3 and QP4. . The first current mirror circuit supplies a part of the drain current flowing from the transistor QN1 to the drain of the transistor QN2.
A part of the drain current flowing from N2 is supplied to the drain of transistor QN1. Thereby, the transistor QN2
And a positive feedback is applied to the drain potential of QN1 to give a hysteresis characteristic to the differential amplifier. The output potential V _C of the differential amplifier is inverted by a P-channel transistor QP5 forming a current mirror circuit together with the transistor QP4, and further output via an inverter circuit 20.

The output of inverter circuit 20 is connected to the gate of N-channel transistor QN7. When the output potential of the inverter circuit 20 is at a low level,
No drain current flows through the transistor QN7. on the other hand,
When the output potential of the inverter circuit 20 is at a high level, a drain current flows through the transistor QN7, and the input potential of the inverter circuit 20 is further lowered. That is, the transistor QN7 performs a positive feedback operation, and reinforces the hysteresis characteristic of the differential amplifier. Thus, when the input potential is substantially equal to the reference potential, the output can be stabilized even if noise is mixed in the input potential.

Here, the gate potential (equal to the drain potential) of the N-channel transistor QN3 to which the current source 10 is connected is changed to the N-channel transistors QN4, QN5, QN
N6 is supplied to the gate of N6 and the N-channel transistor QN
4 and QN5 supply current to the circuit connected to each.

According to the above configuration, since the input potential and the reference potential are not divided by resistance but are directly received by the differential amplifier, a hysteresis comparator circuit having a high input impedance can be realized. Therefore, even if a high impedance voltage source is connected to the input terminal of the hysteresis comparator circuit, there is almost no voltage drop, and one voltage source can be connected to a plurality of hysteresis comparator circuits.

Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a second embodiment of the present invention. As shown in FIG. 2, the hysteresis comparator circuit includes an N-channel transistor QN1 connected to one input terminal to which an input potential _VA is applied, and a reference potential V
_And an N-channel transistor QN2 connected to the other input terminal to which _B is applied. The output potential V _C of the differential amplifier, the transistor QP4
At the same time, the signal is inverted by a P-channel transistor QP5 forming a current mirror circuit, and further output through an inverter circuit 20.

This differential amplifier includes a current mirror circuit composed of P-channel transistors QP1 and QP2. Further, in series with the transistor QP2,
P-channel transistor QP6 is connected. This current mirror circuit supplies the drain current flowing from the transistor QN1 to the source of the transistor QP6. The gate of the transistor QP6 has a transistor Q
The drain potential of P5 is fed back. As a result, positive feedback is applied to the drain potential of the transistor QN2, and the differential amplifier has hysteresis characteristics. As described above, since the hysteresis characteristic of the differential amplifier is reinforced by the positive feedback operation of the transistor QP6, the output can be stabilized even when noise is mixed in the input potential when the input potential is substantially equal to the reference potential. it can.

Next, a third embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to the third embodiment of the present invention. As shown in FIG. 3, the hysteresis comparator circuit includes an N-channel transistor QN1 connected to one input terminal to which an input potential _VA is applied, and a reference potential VN.
_And an N-channel transistor QN2 connected to the other input terminal to which _B is applied. The output potential V _C of the differential amplifier, the transistor QP4
At the same time, the signal is inverted by a P-channel transistor QP5 forming a current mirror circuit, and further output through an inverter circuit 20.

This differential amplifier includes a current mirror circuit composed of P-channel transistors QP3 and QP4. Further, in series with the transistor QP3,
P-channel transistor QP7 is connected. This current mirror circuit supplies a drain current flowing from the transistor QN2 to a source of the transistor QP7. The output potential of the inverter circuit 20 is fed back to the gate of the transistor QP7. As a result, positive feedback is applied to the drain potential of the transistor QN1 to give a hysteresis characteristic to the differential amplifier. As described above, since the hysteresis characteristic of the differential amplifier is reinforced by the positive feedback operation of the transistor QP7, the output can be stabilized even when noise is mixed in the input potential when the input potential is substantially equal to the reference potential. it can.

Next, a fourth embodiment of the present invention will be described.
I will tell. FIG. 4 shows a hysteresis according to a fourth embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a lysis comparator circuit. Figure
As shown in FIG. 4, this hysteresis comparator circuit
Is the input potential V_AIs connected to one input terminal to which
Continued N-channel transistors QN1 and QN8;
Reference potential V_BIs connected to the other input terminal to which
Differential amplifier including an N-channel transistor QN2
have. Output potential V of differential amplifier _CThe transi
P channel which forms a current mirror circuit together with the star QP4
Inverted by the flannel transistor QP5,
Output via the circuit 20.

Further, in series with the transistor QN8, N
The channel transistor QN9 is connected. The output potential of the inverter circuit 20 is fed back to the gate of the transistor QN9. Thus, since strong positive feedback is applied to the drain potential of the transistor QN1, the output can be stabilized even when noise is mixed in the input potential when the input potential is substantially equal to the reference potential.

Next, a fifth embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of a hysteresis comparator circuit according to a fifth embodiment of the present invention. As shown in FIG. 5, the hysteresis comparator circuit includes an N-channel transistor QN1 connected to one input terminal to which an input potential _VA is applied, and a reference potential VN.
_It has a differential amplifier including N-channel transistors QN2 and QN10 connected to the other input terminal to which _B is applied. The output potential V _C of the differential amplifier is inverted by a P-channel transistor QP5 forming a current mirror circuit together with the transistor QP4, and further output via an inverter circuit 20.

Further, in series with the transistor QN10,
N-channel transistor QN11 is connected. The gate of the transistor QN11 has a transistor QP5
Is fed back. Thus, since strong positive feedback is applied to the drain potential of the transistor QN2, the output can be stabilized even when noise is mixed in the input potential when the input potential is substantially equal to the reference potential.

[0026]

As described above, according to the present invention, in a hysteresis comparator circuit having a high input impedance, a strong output can be obtained by utilizing the output of the amplifying means connected to the subsequent stage of the transistors forming the differential pair. Since the positive feedback is applied, the output can be stabilized even if noise is mixed in the input potential.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a hysteresis comparator circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a hysteresis comparator circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a hysteresis comparator circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a hysteresis comparator circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a hysteresis comparator circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional hysteresis comparator circuit.

[Explanation of symbols]

 Reference Signs List 10 current source 20 inverter circuit 7 N-type impurity diffusion region 9 first wiring layer QP1-QP5 P-channel transistor QN1-QN11 N-channel transistor

Claims (3)

[Claims] A differential transistor including a first transistor having a gate to which an input potential is applied and a second transistor having a gate to which a reference potential is applied; and a drain potential of the first or second transistor. A third transistor for amplifying, an inverting amplifier for amplifying a drain potential of the third transistor, and a unit for applying a positive feedback to a drain of the second transistor based on a drain current of the first transistor Means for applying positive feedback to the drain of the first transistor based on the drain current of the second transistor; and means for applying positive feedback to the drain of the third transistor based on the output of the inverting amplifier. Means for applying feedback. 2. A differential pair including a first transistor having a gate to which an input potential is applied and a second transistor having a gate to which a reference potential is applied, and a drain potential of the first or second transistor. Amplifying means for amplifying; means for applying positive feedback to a drain of the second or first transistor based on a drain current of the first or second transistor and an output potential of the amplifying means;
A hysteresis comparator circuit comprising: 3. A differential pair including a first transistor having a gate to which an input potential is applied and a second transistor having a gate to which a reference potential is applied, and a drain potential of the first or second transistor. A hysteresis comparator circuit comprising: amplifying means for amplifying; and means for applying a positive feedback to a drain of the first or second transistor based on an input potential or a reference potential and an output potential of the amplifying means.