JP2002151984A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier that ensures a wide variable gain range and realizes a low consumed current while ensuring high linearity. SOLUTION: A gain control circuit 11 controls a current of current sources 11, 12 of an input stage circuit 1 and a current of current sources 13, 14 of an output stage circuit 2 on the basis of a gain control signal to control the entire gain of the amplifier. An input amplitude detection control circuit 12 detects a differential input voltage given to MOS transistors(TRs) Q1, Q2 to control the current of current sources IA, IB depending on the detected voltage. Furthermore, an output amplitude detection control circuit 13 detects the differential output voltage outputted from output terminals 9, 10 of the output stage circuit 2 to control the current of current sources IC, ID depending on the detected voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier which is applied to, for example, automatic gain control (AGC) for mobile communication and the like, and in which the gain of the amplifier can be varied by external control, in particular, a dynamic range and a linear gain. The present invention relates to a variable gain amplifier with optimized performance.

[0002]

2. Description of the Related Art Conventionally, as a variable gain amplifier of this type, "IEEE JSCC, Vol 33, No. 11, N
ov, 1998, pp1851-1857. "An E
PR4Read / Write Channel wit
The one shown in FIG. 3 described in "h Digital""is known.

As shown in FIG. 3, this variable gain amplifier includes an input stage circuit 1 and an output stage circuit 2, and a gain control circuit 11 controls the current sources I 1, 12 of the input stage circuit 1 and the output stage circuit 2. The currents of the current sources I3 and I4 are controlled so that the overall gain can be controlled. The input stage circuit 1 includes a pair of N-type MOSs for inputting a differential voltage signal.
Transistors Q1 and Q2 are provided, and their gates are connected to input terminals 3 and 4, respectively. The source of MOS transistor Q1 is connected to the drain of N-type MOS transistor Q3, and the source of MOS transistor Q2 is
Connected to the drain of S transistor Q4 and
The sources of the S transistors Q3 and Q4 are connected to a reference voltage (ground voltage) VSS.

The source of the MOS transistor Q1 and the MOS
A resistor R1 is connected between the source of the transistor Q2. The drains of the MOS transistors Q1 and Q2 are connected to one ends of constant current sources I1 and I2 for determining the bias points of the MOS transistors Q1 and Q2, and the other ends are supplied with a power supply voltage VDD. The current values of the constant current sources I1 and I2 can be varied by the gain control circuit 11. MOS transistor Q
1, the drains of Q2 are connected to output terminals 5 and 6, respectively.

[0005] The gate of the MOS transistor Q3 is connected to the gate of the MOS transistor Q5 via an N-type MOS transistor Q5 for level shift.
It is connected to the drain of the OS transistor Q1. The gate of the MOS transistor Q4 is connected to the drain of the MOS transistor Q2 via an N-type MOS transistor Q6 for level shift. That is,
MOS transistor Q5 has a power supply voltage V
DD is supplied, and the gate of the
Connected to the drain of S transistor Q1, the source of which is connected to the gate of MOS transistor Q3 and the N-type MOS
It is connected to the drain of transistor Q8.

The MOS transistor Q6 has a drain to which the power supply voltage VDD is supplied, a gate connected to the drain of the MOS transistor Q2, a source connected to the gate of the MOS transistor Q4 and an N-type transistor. It is connected to the drain of MOS transistor Q9. A bias circuit is formed by the constant current source I0 and the N-type MOS transistors Q7 to Q10. The MOS transistors Q7 to Q10 form a current mirror circuit, and the current flowing through the MOS transistor Q7 is current mirrored so that the MOS transistors Q8, Q8,
The same current flows through Q9 and Q10, whereby the MOS transistors Q5, Q6 and Q15 are biased. Therefore, the MOS transistors Q8, Q9,
Q10 forms a constant current source.

Next, the output stage circuit 2 will be described in detail with reference to FIG. The output stage circuit 2 has a pair of N for input processing of differential signals from the output terminals 5 and 6 of the input stage circuit 1.
Type MOS transistors Q11 and Q12, each gate of which is connected to input terminals 7 and 8. The sources of the MOS transistors Q11 and Q12 are connected to each other to form a common source circuit.

The source of the MOS transistor Q11 is connected to the drain of an N-type MOS transistor Q13.
The source of the OS transistor Q12 is connected to the drain of the N-type MOS transistor Q14, and the sources of the MOS transistors Q13 and Q14 are connected to a reference voltage (ground voltage) VSS. The drains of the MOS transistors Q11 and Q12 are connected to a constant current source I that determines a bias point of the MOS transistors Q11 and Q12.
3 and one end of I4 are connected, and the other end is connected to the power supply voltage VD.
D is supplied. Constant current sources I3, I4
The current value can be varied by the gain control circuit 11. The drains of the MOS transistors Q11 and Q12 are connected to output terminals 9 and 10, respectively.
A resistor R2 is connected between the two drains.

The gates of the MOS transistors Q13 and Q14 are N-type MOS transistors Q for level shifting.
15 is connected to the middle point of the resistor R2. That is, the MOS transistor Q15 has a drain supplied with the power supply voltage VDD, a gate connected to the middle point of the resistor R2, a source connected to the gates of the MOS transistors Q13 and Q14 and the N-type MOS transistor. It is connected to the drain of transistor Q10.

Next, an outline of the operation of the conventional variable gain amplifier having such a configuration will be described with reference to FIG. If the differential input voltage is not applied to the gates of the MOS transistors Q1 and Q2, the currents flowing through the MOS transistors Q1 and Q3 are equal to I1,
The currents flowing through MOS transistors Q2 and Q4 are equal to I
2, and I1 = I2.

On the other hand, when a differential input voltage is applied to the gates of the MOS transistors Q1 and Q2,
It is assumed that the potential of the gate of the transistor Q1 has risen and the potential of the gate of the MOS transistor Q2 has dropped by the same amount. In this case, the source potential of MOS transistor Q1 rises accordingly, and the source potential of MOS transistor Q7 falls by the rise. As a result, the voltage across the resistor R1 is the same as the differential input voltage. Therefore, a current flows through the resistor R1, so that the drain current of the MOS transistor Q3 decreases and the drain current of the MOS transistor Q4 increases.

The change in the drain current is converted into the gate voltage by the mutual conductance of the MOS transistors Q3 and Q4.
This is converted into a change in the gate potential of Q6. As described above,
The potential of the gate of the MOS transistor Q1 rises,
When the potential of the gate of the S transistor Q2 drops by the same amount, the gate potential of the MOS transistor Q12 increases, and the gate potential of the MOS transistor Q11 decreases by the increased amount.

At this time, since the current supplied from the current sources I3 and I4 does not change, the increase in the drain current of Q12 is supplied from the current source I3 through the resistor R2, and the drain current of the MOS transistor Q11 decreases by the increase. I do. Since the current flows through the resistor R2 in this manner, a differential output voltage is output between the output terminals 9 and 10. By the way, it is known that the gain Av of the conventional variable gain amplifier operating as described above is expressed by the following equation (1).

Av = (R2 / R1) × (gm2 / gm1) (1) In the expression (1), gm1 is a mutual conductance value of the MOS transistors Q1 and Q2, and gm
2 is a mutual conductance value of the MOS transistors Q3 and Q4. In the equation (1), the transconductances gm1 and gm2 are current values I2 and I4 of the current sources I2 and I4, respectively.
I4 can be replaced with the following equation (2).

Av = (R2 / R1) × Sqrt (I4 / I2) (2) Here, Sqrt (I4 / I2) means the square root of (I4 / I2). Therefore, in the conventional variable gain amplifier, the gain control circuit 11 sets the current values of the current sources I1 to I4 to:
The gain Av of the variable gain amplifier is controlled by controlling as in the following equations (3) and (4).

Idc-Icon = I1 = I2 (3) Idc + Icon = I3 = I4 (4) where Icon is a variable current for changing the gain Av of the variable gain amplifier, and Idc is Icon = 0. , Ie, the lower limit (constant value) of the drain current of the MOS transistor.

Therefore, if the variable current Icon of the current sources I1 to I4 is increased by the gain control circuit 11, the gain Av
Can be increased, and conversely, the variable current Icon
Can be reduced to reduce the gain Av.

[0018]

By the way, in the conventional variable gain amplifier, when the gain Av increases, the current flowing through the MOS transistors Q1 and Q2 of the input stage circuit 1 decreases, and the variable gain amplifier operates with a small DC bias. Therefore, the operation is not performed in the saturation region, the distortion of the output signal increases, and the linearity is impaired.

That is, when the linearity of the conventional variable gain amplifier is increased, the variable range of the gain is reduced. This is because the linearity of the transconductance gm1 or gm2 of the gain Av increases as the drain current flowing through the MOS transistor increases. In view of the above, an object of the present invention is to provide a variable gain amplifier capable of securing a wide variable gain range and realizing low current consumption while securing high linearization. .

[0020]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, each of the inventions according to claims 1 to 6 is configured as follows. That is, claim 1
According to the invention described in (1), a pair of first and second MOS transistors for inputting and processing a differential input signal, and a first resistor connected between both sources of the first and second MOS transistors And third and fourth MOS transistors connected in series between respective sources of the first and second MOS transistors and a reference potential, respectively, and drains of the first and second MOS transistors, respectively. First and second current sources connected to each other,
An input stage for connecting each gate of the third and fourth MOS transistors to a corresponding drain of the first and second MOS transistors via a level shifter or directly; A pair of fifth and sixth MOS transistors for receiving a differential output signal output from the third MOS transistor;
A second resistor connected between both drains of the first and sixth MOS transistors, and third and fourth current sources respectively connected to respective drains of the fifth and sixth MOS transistors; An output stage for extracting a differential output signal from both ends of the second resistor, and control means for controlling the first constant current source and the second constant current source based on the amplitude of the differential input signal; , Are provided.

According to a second aspect of the present invention, there is provided a pair of first and second MOS transistors for inputting and processing a differential input signal.
A transistor; a first resistor connected between both sources of the first and second MOS transistors;
Third and fourth MOs connected in series between the respective sources of the first and second MOS transistors and the reference potential, respectively.
An S transistor, and first and second current sources respectively connected to the drains of the first and second MOS transistors, wherein each of the gates of the third and fourth MOS transistors includes a level shifter. Via an input stage connected to the respective drains of the first and second MOS transistors, or directly, via a pair of differential input signals output from the first and second MOS transistors. Fifth and sixth MOS transistors, a second resistor connected between both drains of the fifth and sixth MOS transistors, and a drain connected to each of the fifth and sixth MOS transistors. An output stage for extracting a differential output signal from both ends of the second resistor, and a differential output from the output stage. Is characterized in further comprising control means for controlling said fourth constant current source and the third constant current source based on the amplitude of the force signals.

According to a third aspect of the present invention, in the variable gain amplifier according to the first or second aspect, current sources are respectively connected between the gates of the third and fourth MOS transistors and the reference voltage. It is characterized by having. According to a fourth aspect of the present invention, in the variable gain amplifier according to any one of the first to third aspects, the input stage is controlled by controlling the first, second, third, and fourth current sources. And a gain control means for varying the gain of the output stage.

According to a fifth aspect of the present invention, in the variable gain amplifier according to the first, second, or fourth aspect, the first and second current sources are provided with an amplitude of the differential input signal. And a current source for varying the gain is connected in parallel with each other. According to a sixth aspect of the present invention, in the variable gain amplifier according to the first, second, or fourth aspect, the third and fourth current sources are configured to output differential output signals from the output means. A current source controlled based on the amplitude and a current source for controlling the gain are connected in parallel with each other.

As described above, according to the present invention, the first constant current source and the second constant current source are controlled based on the amplitude of the differential input signal input to the input stage.
Or the currents of the third and fourth constant current sources are controlled based on the amplitude of the differential output signal output from the output means. For this reason, according to the present invention, the bias becomes appropriate and high linearization can be ensured. Also, it is possible to secure a wide variable gain range. In addition, low current consumption can be realized.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of an embodiment of the variable gain amplifier of the present invention will be described with reference to FIG. As shown in FIG. 1, the variable gain amplifier according to this embodiment includes at least an input stage circuit 1A, an output stage circuit 2A, an input amplitude detection control circuit 12, and an output amplitude detection control circuit 13.

The basic configuration of the input stage circuit 1A is the same as that of the input stage circuit 1 shown in FIG. 3, except that the current source IA is connected in parallel with the current source I1 as shown in FIG. In addition to the addition, a current source IB is added in parallel with the current source I2. The current sources IA and IB are configured so that the current value can be varied by a control signal from an input amplitude detection control circuit 12 described later.

Since the configuration of the other parts of the input stage circuit 1A is the same as that of the input stage circuit 1 of FIG. 3, the same components are denoted by the same reference numerals and description of the configuration is omitted. . The basic configuration of the output stage circuit 2A is the same as that of the output stage circuit 2 shown in FIG. 3 except that the current source IC is added in parallel with the current source I3 as shown in FIG. And a current source ID is added in parallel with the current source I4. The current sources IC and ID are configured so that the current value can be varied by a control signal from an output amplitude detection control circuit 13 described later.

The configuration of the other parts of the output stage circuit 2A is the same as the configuration of the output stage circuit 2 of FIG. 3, so that the same components are denoted by the same reference numerals and description of the configuration will be omitted. . The input amplitude detection control circuit 12 controls the differential input signal input to the input stage circuit 1, that is, the MOS transistor Q
1, the magnitude of the amplitude of the differential input voltage input to Q2 is detected, and the current values of current sources IA and IB are controlled in accordance with this detection.

The output amplitude detection control circuit 13 outputs a differential output signal output from the output stage circuit 2, that is, the output terminal 9,
The magnitude of the amplitude of the differential output voltage output from 10 is detected, and the current values of the current sources IC and IB are controlled in accordance with the detection. The gain control circuit 11 in FIG. 1 controls the currents of the current sources I1 and I2 of the input stage circuit 1 and the current sources I3 and I4 of the output stage circuit 2 based on the gain control signal to control the gain of the whole amplifier. This is equivalent to the gain control circuit 11 of FIG.

Next, an example of the operation of the variable gain amplifier according to the embodiment having such a configuration will be described. The variable gain amplifier according to this embodiment operates in the same manner as the conventional variable gain amplifier of FIG. 1, and the gain control circuit 11 uses the current sources I1, 12 of the input stage circuit 1 and the output stage based on the gain control signal. The current of the current sources I3 and I4 of the circuit 2 is controlled to control the gain of the whole amplifier.

Further, the input amplitude detection control circuit 12
The differential input voltage input to the OS transistors Q1 and Q2 is detected, and if the amplitude of the differential input voltage is larger than a predetermined value, the current values of the current sources IA and IB are increased. If the amplitude of the voltage is smaller than the predetermined value, the current sources IA, IB are reduced so that the current values of the current sources IA, IB are reduced.
Controls IB.

On the other hand, the output amplitude detection control circuit 13 detects the differential output voltage output from the output terminals 9 and 10 of the output stage circuit 2, and if the amplitude of the differential output voltage is larger than a predetermined value, the current Increase the current values of source IC and ID, and conversely,
If the amplitude of the differential output voltage is smaller than a predetermined value, the current sources I and
C, control ID.

As described above, in the variable gain amplifier according to this embodiment, in addition to controlling the gain by controlling the current values of the current sources I1 to I4, in addition to the conventional technique, the variable gain amplifier of the input stage circuit 1A When the input is large, the current source I
The current values of A and IB are increased, and when the output of the output stage circuit 2A is large, the current values of the current sources IC and ID are increased.

For this reason, in the variable gain amplifier according to this embodiment, the bias is appropriate, high linearity is ensured, a wide variable gain range can be ensured, and low current consumption can be realized. Further, according to the variable gain amplifier according to this embodiment, when a standard dynamic range cannot be obtained unless a plurality of variable gain amplifiers are stacked, such as AGC in mobile communication,
It can be expected to reduce the number of variable gain amplifiers and current consumption.

Further, according to the variable gain amplifier according to this embodiment, since the linearity can be improved, it can be applied as an amplifier in a field where high linearity is required. Next, a control example when the variable gain amplifiers of the embodiment shown in FIG. 1 are cascaded will be described with reference to FIG. FIG. 2 shows an example in which two variable gain amplifiers 21 and 22 are cascaded. In this case, the variable gain amplifier 2
1 and the input of the variable gain amplifier 22 are the same, so that the input amplitude detection control circuit 12 of the variable gain amplifier 22 can be omitted. In this case, as shown
The current sources IA and IB of the variable gain amplifier 22 have their current values controlled by the output amplitude detection control circuit 13 of the variable gain amplifier 21.

Note that, instead of omitting the input amplitude control circuit 12 of the variable gain amplifier 22, the output amplitude control circuit 13 of the variable gain amplifier 21 is omitted, and the current sources IC and ID of the variable gain amplifier 21 are changed to variable gain amplifiers. 22 may be controlled by the input amplitude control circuit 12 (not shown).
By the way, in the embodiment of FIG. 1 described above, the current source I
Although the other current sources IA to ID are provided in parallel to 1 to I4, the current sources IA to ID may be included in the current sources I1 to I4.

That is, the MOS transistors Q1, Q
2, the currents flowing in Q11 and Q12 (the currents of the current sources I1 to I4) may be controlled so as to satisfy the following equations (5) and (6). Idc-Icon (Igain) + Irange (Iin (Linearity)) = I1 = I2 (5) Idc + Icon (Igain) + Irange (Iout (Linearity)) = I3 = I4 ... (6) where Irange (Irange)
y)) = IA = IB, and Irrange (Iout
(Linearity)) = IC = ID.

In the above embodiment, the current sources I1 to I1
Although I4 is controlled by the gain control circuit 11, this control may be fixed and only the current sources IA to IB may be controlled. In this case, although gain control by the gain control circuit 11 cannot be performed, high linearity can be obtained.

[0039]

As described above, according to the present invention, the currents of the first and second constant current sources are controlled based on the amplitude of the differential input signal input to the input stage. Alternatively, the currents of the third constant current source and the fourth constant current source are controlled based on the amplitude of the differential output signal output from the output means.

For this reason, according to the present invention, the bias becomes appropriate and a high linearity can be ensured. Also, it is possible to secure a wide variable gain range. In addition, low current consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a variable gain amplifier according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a cascade connection of the embodiment.

FIG. 3 is a circuit diagram of a conventional variable gain amplifier.

[Explanation of symbols]

1A Input stage circuit 2A Output stage circuit 11 Gain control circuit 12 Input amplitude detection control circuit 13 Output amplitude detection control circuit I1 to I4 Current sources IA to IB Current sources Q1, Q2 MOS transistors (first and second MOs)
S transistors) Q3, Q4 MOS transistors (third and fourth MOs)
S transistor) Q11, Q12 MOS transistor (fifth and sixth MOS transistors)

Claims (6)

[Claims] A pair of first and second MOS transistors for receiving and processing a differential input signal; a first resistor connected between both sources of the first and second MOS transistors; A third and a fourth MOS transistor respectively connected in series between a source of each of the first and second MOS transistors and a reference potential, and a drain connected to each of the first and second MOS transistors. A first current source and a second current source, wherein each gate of the third and fourth MOS transistors is connected to a corresponding one of the first and second MOS transistors via a level shifter or directly. An input stage connected to each drain; and a fifth and sixth pair of inputting differential output signals output from the first and second MOS transistors.
A MOS transistor, a second resistor connected between both drains of the fifth and sixth MOS transistors, and a third and fourth MOS transistor connected to respective drains of the fifth and sixth MOS transistors, respectively. An output stage for extracting a differential output signal from both ends of the second resistor; and a first constant current source and a second constant current based on the amplitude of the differential input signal. Control means for controlling the source and the variable gain amplifier. A pair of first and second MOS transistors for inputting and processing a differential input signal; a first resistor connected between both sources of the first and second MOS transistors; A third and a fourth MOS transistor respectively connected in series between a source of each of the first and second MOS transistors and a reference potential, and a drain connected to each of the first and second MOS transistors. A first current source and a second current source, wherein each gate of the third and fourth MOS transistors is connected to a corresponding one of the first and second MOS transistors via a level shifter or directly. An input stage connected to each drain; and a fifth and sixth pair of inputting differential output signals output from the first and second MOS transistors.
A MOS transistor, a second resistor connected between both drains of the fifth and sixth MOS transistors, and a third and fourth MOS transistor connected to respective drains of the fifth and sixth MOS transistors, respectively. An output stage for extracting a differential output signal from both ends of the second resistor; a third constant current source based on an amplitude of the differential output signal from the output stage; And control means for controlling the constant current source according to claim 4. 3. The variable gain amplifier according to claim 1, wherein current sources are respectively connected between gates of said third and fourth MOS transistors and said reference voltage. 4. The apparatus according to claim 1, further comprising gain control means for controlling said first, second, third, and fourth current sources to vary gains of said input stage and said output stage. The variable gain amplifier according to claim 1. 5. A current source controlled based on an amplitude of the differential input signal and a current source for varying the gain are connected in parallel to the first and second current sources, respectively. Claim 1, Claim 3, Claim 3,
Alternatively, the variable gain amplifier according to claim 4. 6. A current source controlled based on an amplitude of a differential output signal from said output means, and a current source for controlling said gain, wherein said third and fourth current sources are in parallel with each other. 5. The variable gain amplifier according to claim 1, wherein the variable gain amplifier is connected to the variable gain amplifier.