JP2002150800A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a semiconductor integrated circuit which can identify a cause of a failure and thereby easily specify a cause of the failure. [MEANS FOR SOLVING PROBLEMS]
The memory cell array 10 is provided with a cell node stage potential setting circuit 121 constituting an extended cell array. The cell node stage potential setting circuit 121 controls the extension word line WLHLD <
0>, <1> and the bit lines BL controlled by the
It comprises NMOS transistors QN21 and QN22 for fixing t and BLc to VSS. In the test mode, the expanded word lines WLHLD <0> and <1> are selected to connect the cell nodes, that is, the bit lines BLt and BLc to VSS.
By performing the data reading fixed to the above, it is possible to narrow down the cause of the defect by comparing the expected value data with the actual data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit including a memory, such as a system LSI, and more particularly to a semiconductor integrated circuit having a test mode.

[0002]

2. Description of the Related Art In general, a system LSI is a highly functional LSI which realizes various functions by integrating a logic block for performing a logical operation and a memory block for storing data. Each logic block and each memory block are connected to a main logic that controls the entire operation of the LSI via a data bus and a control bus, and the main logic is connected to a data input / output terminal (I / O pad).

[0003] In such a highly functionalized system LSI, it is an important problem how to efficiently perform a test. In general, a test mode can be set for each logic block or memory block in order to facilitate failure analysis in the test mode. The test I / O pad is prepared in common for a plurality of logic blocks and memory blocks. A multiplexer for extracting a test signal is provided for each logic block or memory block, and a test I / O common to all blocks is provided.
An / O multiplexer is provided so that a test signal for each block can be output to a common test I / O pad. In order to reduce the number of I / O pads, a normal operation I / O pad may be used for testing without providing a testing I / O pad.

[0004]

However, the system LS
In many cases, I uses different design methods for logic blocks and memory blocks, and also different designers. Therefore, even if a test LSI finds a defect, it is necessary to identify the defective part in a system LSI integrating them. Is not easy. Conventionally, if a test finds a defect, by repeating the test while changing the conditions little by little,
Although the cause was identified, this method is not always possible.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor integrated circuit which can identify a cause of a defect and facilitates identification of a defective portion.

[0006]

SUMMARY OF THE INVENTION The present invention has a plurality of data transfer stages for sequentially transferring read / write data between a memory cell and a data input / output terminal, and has a normal operation mode and a test mode. In a semiconductor integrated circuit having at least one of the plurality of data transfer stages, a test potential setting circuit for outputting a predetermined potential in a test mode is provided.

Specifically, the test potential setting circuit includes an extended signal selection circuit that selects and outputs the predetermined potential in the test mode, in contrast to a signal selection circuit that outputs a selected signal in the normal operation mode according to the selection signal. It is configured with.
In this case, the test mode by the test potential setting circuit is executed by allocating an address to an address space for accessing the memory cell array so as to select the extension signal selection circuit instead of the signal selection circuit at a predetermined address. Is done.

According to the present invention, in the test mode, the read / write data transfer stage for the memory cell array is caused to output a predetermined potential irrespective of the data at the preceding stage, thereby determining whether or not the subsequent stage is normal. can do. In other words, according to the present invention, a defect cause candidate can be separated for a data transfer path at a plurality of transfer stages, and a defective portion can be easily specified.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. Prior to describing a specific embodiment, a system LSI targeted by the embodiment
Will be described. FIG. 1 shows the overall configuration of a system LSI. This system LSI has a plurality of (N) memories 1 for storing data and a logic 2 for performing a logical operation. The memory 1 and the logic 2 are connected to a main logic 3 which controls the whole via a data bus and a control bus. Main logic 3
Are connected to the data I / O pad 4.

The system LSI has a normal operation mode and a test mode. FIG. 2 shows a portion related to the test mode. However, the main logic 3 is ignored. The test command is input from the test command pad 7 and decoded by the command decoder 8. The decoded command is sent to the memory 1 or the logic 2 according to the content, and a test is performed. The data input / output terminals of the memory 1 and the logic 2
Each of the multiplexers MUX is connected to test I / O lines having fewer data input / output terminals. Each test I / O line is further selected by a test I / O multiplexer 5 by a selection signal SEL output from a command decoder 8 and connected to a test I / O pad 6.

As described above, a multiplexer is provided inside each of the memories 1 and the logic 2 to reduce the number of test data input / output lines I / O of each block and further reduce the number of test data input / output lines I / O of each block. A test I / O pad 6 is provided for each memory 1
In addition, the test can be performed with a small number of terminals by sharing the logic with the logic 2. In order to further reduce the number of terminals, the test I / O pad may be shared with a normal I / O pad, and the test command pad may be shared with a normal command pad.

FIG. 3 shows a configuration of the memory 1 and shows a case of a DRAM adopting a redundancy circuit system. The memory cell array 10 includes a memory cell array main body 11 in which bit lines BL and word lines WL are arranged so as to intersect with each other, and a memory cell MC is arranged at each intersection, a bit line sense amplifier 12 for detecting and amplifying bit line data, and It has a column gate 13 for selecting a bit line. The bit line selected by the column gate 13 is connected to the data line DQ provided with the data line sense amplifier 50.
The data line DQ is further connected to an input / output line I / O via a column replacement switch 60 for replacing a defective column with a spare data line, and is connected to a data I / O pad.

The row decoder / row redundancy controller 20 selects a word line WL of the memory cell array 10 and controls replacement of a defective word line with a spare word line according to a row address RA. The column decoder 30
Activate the column selection line CSL selected based on the column address CA. The column redundancy controller 40 controls the column replacement switch 60 based on the column address CA.

Addresses and commands input from the outside are interpreted by an address buffer (register) / command decoder 50, and are used to select an internal row address RA, an internal column address CA, and a spare word line or a spare data line during a test. Selection signals RAX, CAX, etc. are issued.

FIG. 4 shows a more specific configuration of the memory cell array 10. For example, 128 data lines DQ
For each of <0> to <127> (each data line DQ is actually formed of a data line pair as described later), eight column selection lines CSL <0> to 8 are provided for each row.
Eight memory cells selected by <7> are connected via a sense amplifier S / A and a column gate.

For replacement of a defective column, for example, n spare data lines SDQ <0> to <n-1> are prepared. Memory cell array 10 includes a redundant column cell array corresponding to each spare data line.
8 selected by the column selection lines CSL <0>-<7>
The memory cells are connected to each spare data line. The defective column replacement is performed by replacing the defective normal data line DQ with the spare data line SDQ by the column replacement switch 60 as shown in FIG.

The configuration shown in FIG. 4 is further added to a pair of data lines DQ.
Focusing on (DQt, DQc), the result is as shown in FIG. A bit line pair BLt, BLc selected by eight column gates 13 <0> to <7> into which column selection lines CSL <0> to <7> respectively enter is a pair of data lines DQ.
t and DQc are shared.

FIG. 6 further shows a pair of bit lines BL (BL
(t, BLc). The memory cell MC includes a cell transistor driven by a word line WL and a cell capacitor. To replace a defective word line, for example, m spare word lines SW
A redundant row cell array having L <0> to <m-1> is arranged. The sense amplifier 12 includes a flip-flop including PMOS transistors QP1 and QP2 and an NMOS.
It is configured using a flip-flop including transistors QN1 and QN2. The column gate 13 is driven by a column selection line CSL and includes NMOS transistors QN3 and QN4 that connect between the bit lines BLt and BLc and the data lines DQt and DQc.

The portion of the row decoder / row redundancy controller 20 shown in FIG. 3 is configured as shown in FIG. The internal row address RA <0: 7> issued from the address buffer / command register 50 is
To select the word line WL <0: 511>. The address of the word line (defective row address) is written in, for example, a fuse circuit, read out when the power is turned on, and held in the latch circuit 22, and is held in the latch circuit 22 and the row address RA. The comparison circuit 25 detects the coincidence with the defective row address RA = 0 to m-1.

When a match with a defective address is not detected and all outputs of the comparison circuit 25 are at "H", the NAND gate G
1 output REDENn is “L”. At this time, the output of the row decoder 21 passes through the NOR gate G2 to drive the selected word line WL. When a match between the supplied row address and the defective row address is detected, the output of the corresponding comparison circuit 25 is inverted, the output of the NAND gate G1 becomes REDENn = "L", and the output transfer of the row decoder 21 is performed. It is forbidden. Instead, one of spare word lines SWL <0> to <m-1> is activated.

In the test mode, a test is also performed to determine whether or not a memory cell connected to spare word lines SWL <0> to <m-1> has a defect. Therefore, each latch circuit 22 of the row redundancy controller section includes:
A dummy latch circuit 23 is provided. The dummy latch circuits 23 have row addresses RA = 0 to m, respectively.
Pseudo defective address data indicating that -1 is defective is stored.

When the selection signal RAX is issued from the address buffer / command decoder 50 in the test mode, the selector 24 is switched. As a result, the dummy latch circuit 2 replaces the latch circuit 22.
As in the case where the output of No. 3 is selected and there is a defect, the spare word line SWL is selected by detecting the coincidence with the row address supplied from the outside.

FIG. 8 shows the configuration of the column redundancy controller 40. The column redundancy controller 40 has a latch circuit 41 for storing a defective column address, as in the case of the row redundancy controller. As shown in FIG. 4, spare data line SDQ is n
In the case where this is prepared, n sets of the latch circuits 41 are prepared, each set including eight sets. These latch circuits 41 store the positions of defective data lines when the column selection signal CSL takes a value of 0 to 7.

Therefore, when the column selection signal CSL output from the column decoder 30 corresponds to a data line defect, the selector 43 is controlled by this, and the replacement signals Z <0> to <n-1> Is output. The replacement signal Z is supplied to the column replacement switch 60, and the defective data line is switched to the spare data line. Since n sets of the latch circuits 41 are prepared, the replacement control of n or less defective data lines can be performed in all the column selection signals CSL.

The cell array connected to spare data line SDQ is a redundant column cell array. In the test mode, a test is also performed to determine whether a memory cell connected to spare data line SDQ has a defect. In this test mode, the spare data line SDQ can be accessed regardless of the column selection signal CSL. Therefore, a total of n dummy latch circuits 42 are provided for each set of the latch circuits 41 of the column redundancy controller 40. The dummy latch circuit 42 has a column selection signal C
Pseudo defective address data indicating that the data line of SL = 0 to n-1 is defective is stored. As a result, in the test mode, when the column address signal CSL = 0 to n-1 enters the selector 43 together with the selection signal CAX, the dummy latch circuit 42 is selected regardless of the defective data line information of the latch circuit 41, and the replacement signal Output Z.

The column permutation switch 60 controlled by the permutation signal Z is specifically constituted by the permutation system shown in FIG. 9 or the data line shift system shown in FIG. In the switch system of FIG. 9, the data lines DQ <0: 1
27> are replaced with spare data lines <0: n−1>, and are configured by switches SW0 to SW127 which are connected to the data input / output terminals I / O <0: 127>.

When the replacement signals Z <0: n-1> are all inactive, the data lines DQ <0: 127> are connected to the data input / output terminals I / O <0: 127>, respectively. At this time, the spare data line SDQ <0: n−1> is connected to the memory cell of the redundant column cell array corresponding to the selected column address, but has the input / output terminal I / O.
<0: 127> is not connected. When replacement signal Z <0> includes defective data information, data line DQ indicated thereby is disconnected from input / output terminal I / O, and spare data line SDQ <0> is replaced with input / output terminal I / O. Connected to. The same applies to other replacement signals Z <1: n-1>.

In the data line shift system shown in FIG. 10, the column replacement switch 60 has a data input / output terminal I /
The connection of the O to the data line DQ is constituted by a shift switch circuit for sequentially shifting one by one while avoiding a defective data line position. When the replacement signals Z <0: n−1> are all inactive, the data lines DQ <0: 127>
Connected to data input / output terminals I / O <0: 127>. At this time, spare data line SDQ <0: n−1>
Are connected to the memory cells of the redundant column cell array corresponding to the selected column address, but are not connected to the input / output terminals I / O <0: 127>.

When the replacement signal Z <0> includes defective data information, for example, when the data line DQ <1> is defective, as shown by the crosses in FIG. 10, the data input / output terminal I / O <1>
Is shifted to the data line DQ <2> as shown by the broken line, and then the connection destination of the input / output terminal I / O is shifted in sequence to change the last data input / output terminal I / O <127>. The connection to spare data line SDQ <0> is controlled. The same applies to other replacement signals Z <1: n-1>.

The test I / O multiplexer 5 shown in FIG.
Is configured as shown in FIG. That is, the test of the 128 data input / output terminals I / O <0: 127> is 1
Six test data input / output pads 6 (test I / O <
0:15>), a multiplexer MUX for inputting eight data input / output lines at a time every 16 lines is arranged. In the test mode, 16 data input / output lines are controlled by the selection signal SEL, and the
/ O <0:15>.

In the configuration of the system LSI described so far, when performing a failure analysis, as a typical example, writing / reading of data in a memory cell is performed. Consider the case of analysis. Possible causes of this defect include, for example, a defect in the memory cell, a defect in the sense amplifier that performs data read / write of the memory cell, and a defect in the data line sense amplifier on the main data transfer path. Can be Although there is no problem with the main data transfer path, it is also considered that the word line selection circuit system and the bit line selection circuit system for selecting memory cells are defective, the redundancy controller is defective, or the timing is incorrect. Can be Further, in the measurement environment, there are causes such as incorrect wiring, incorrect tester program, and no power supply.

In order to identify these various causes, as described above, conventionally, a test in which conditions are changed is repeated. However, the recent increase in memory capacity,
The read / write operation of a memory cell is becoming more complicated with the sophistication and speeding up.
The difficulty in identifying the cause is increasing. In addition, not only identification of a defective part but also identification of a part that limits the performance is important when performing performance evaluation, but this is also difficult.

In particular, a system LSI with advanced functions
In, the number of blocks in the LSI increases. In this case, as described above, a test mode can be set for each block in order to easily understand the causal relationship between the test result and the failure. Since the number of interposed circuit stages increases and the number of circuits for driving those circuits also increases, it is not easy to identify the cause.

Therefore, the present invention relates to the system LS described above.
I, in a memory having a normal operation mode and a test mode, at least one of a plurality of data transfer stages for sequentially transferring read / write data from the memory cell array to the data input / output terminal includes a test mode. The provision of a test potential setting circuit for providing a predetermined potential that invalidates data at the preceding stage sometimes makes it easy to specify a defective portion. In the case of a DRAM, locations where the potential can be fixed in the data transfer path include a memory cell node, a bit line BL, a data line DQ, and a data input / output line I / O. These are selected by the word line WL, the column selection line CSL, the selection signals Z and SEL, etc. By devising these signals, it is possible to fix the potential of each section. Hereinafter, a specific configuration method of the test potential setting circuit will be described. It is effective to use any one of the test potential setting circuits described below.
It is preferable to combine a plurality of test potential setting circuits simultaneously.

[Fixed Potential Output at Cell Node Stage] Of the plurality of data transfer stages described above, the cell node in the memory cell array is located at the end as viewed from the data input / output pad. FIG. 12 shows the memory cell array 1 shown in FIG.
This is an example in which a cell node stage potential setting circuit 121 is provided at the end of the bit lines BLt and BLc based on 0. The cell node stage potential setting circuit 121 is configured as an extension of the memory cell array 10. That is, the signal line WLHLD <0 that controls the cell node stage potential setting circuit 121
> And <1> represent the word line WL and the spare word line SWL.
These are made simultaneously with the same rules (same pitch, same process), and are referred to as extended word lines below.

These extended word lines WLHLD <0
And NMOS transistors QN21 and QN connecting bit lines BLt and BLc to VSS under the control of
Reference numeral 22 denotes the same rule as that of the memory cell MC, except that there is no cell capacitor from the memory cell. That is, these NMOS transistors QN
The memory cell array 10 can be called an expanded memory cell array including the memory cell array 21, the QN 22, and the expanded word lines for driving these. In FIG. 12, only one bit line pair BLt, BLc is representatively shown, but preferably all bit line pairs are extended word line WLHL.
A similar cell node stage potential setting circuit driven commonly by D <0> and <1> is provided.

Such a cell node stage potential setting circuit 121
To fix one of the bit lines BLt and BLc to the ground potential VSS (the read bit line potential when data is "0") in the test mode. Specifically, in the data read operation, for example, after the bit line precharge and before the sense amplifier is activated, for example, the extended word line WLHLD
By selectively driving <0>, the bit line BLt is fixed at VSS. At this time, if the read data transfer path after the bit line is normal, when the row address is switched and the data read is repeated, the read data on the bit line BLt side is always "0". Assuming that such an expected value is normally read out, the bit line sense amplifier 12, the column gate 13, the data line sense amplifier 50, the column redundancy controller, and the test I / O multiplexer 5 are all normal after the bit line. Is confirmed.

When the above-described read operation is performed by operating the cell node stage potential setting circuit 121, "0" is always obtained.
If the test operation in the state where the cell node stage potential setting circuit 121 is not operated in spite of the fact that the cell node stage potential It is presumed that the defect or the defect of the memory cell MC itself has not been properly replaced by the redundancy. Conversely, if the read data is not always "0" despite the fact that the bit line is fixed at VSS by operating the cell node stage potential setting circuit 121, the bit line sense amplifier 12 and the column Gate 13, data line sense amplifier 50, test I / O multiplexer 5
It is presumed that one of the above has a cause of failure or that the address control system has a failure.

It is possible to control the extended word lines WLHLD <0>, <1> of the cell node stage potential setting circuit 121 by supplying a signal from the outside, but preferably,
Extended word line W of this cell node stage potential setting circuit 121
A control drive circuit for selecting and driving LHLD <0>, <1> is a row decoder / row redundancy controller 2
It is configured as an extension circuit of 0. FIG. 13 shows a configuration based on the row decoder / row redundancy controller 20 shown in FIG. 7 and a control drive circuit 131 for extended word lines WLHLD <0> and <1> added thereto.

The control drive circuit 131 has an extended word line WLHLD, which is an extension of the same configuration as the dummy latch 23, selector 24 and comparator 25 of the row redundancy controller which enables the selection of the spare word line SWL during a test.
And the number of dummy latches 23a, selectors 24a and comparators 25a. Here, there is no need for a latch circuit for defective replacement.

In such a configuration, the dummy latch circuit 2
In the test mode 3a, data is stored in advance so that the expanded word lines WLHLD <0> and <1> are selected instead of the two word lines in the test mode. This is possible by programming the fuse circuit, as well as storing the defective address.

In the test mode, as in the case of the word line WL and the spare word line SWL, if the extension word line WLHLD of the cell node stage potential setting circuit 121 is selected and driven, according to the selected extension word line WLHLD. , The cell node, that is, the bit line potential is fixed at VSS. Therefore, by comparing the read data with the expected value data, it is possible to narrow down the cause of the failure.

[Fixed Potential Output at Bit Line Stage] In the cell array configuration shown in FIG. 4, a bit line selected by eight column selection lines CSL <0> to <7> is connected to a pair of data lines DQ. . On the other hand, as shown in FIG. 14, extended column select lines CSL <8> and <9> are provided, and column gates <8> and <9> selected by the extended column select lines and extended bit lines having a fixed potential. Prepare

More specifically, as shown in FIG. 15, two extended bit lines BLHLDt and BLHLDc connected to data lines DQt and DQc, respectively, are prepared. The extension bit lines BLHLDt and BLHLDc selected by the extension column selection line CSL <8> are VCC and VS, respectively.
Fixed to S. Extension bit lines BLHLDt, BLHLD selected by extension column selection line CSL <9>
c is fixed to VSS and VCC, respectively. No memory cells are connected to these extended bit lines BLHLDt and BLHLDc.

With such an extended column configuration, when data is read from the extended column in the test mode, if the data transfer system after the bit line is normal, the column selection line CSL <8> regardless of the row address. By BLHL
The data of Dt = VCC, BLHLD = VSS, and BLHLDt = VSS by the column selection line CSL <9>.
The expected value data of S, BLHLD = VCC is read. If such expected value data is not read from the extension column, the data line sense amplifier after the data line,
It is assumed that there is a defect in the column redundancy, the data I / O multiplexer, the row address system, and the like. If normal test data cannot be read from another normal column, despite the fact that the expected value data of the above-mentioned extended column can be obtained normally, the defective part may be a column gate, a bit line sense amplifier, a memory cell, or the like. It is assumed that the defect is not normally replaced by the redundancy.

[Fixed potential output at data line stage] FIG.
Is an example in which an extended data line DQHLD whose potential is fixed is provided for a data line DQ on the data input / output pad side of the bit line BL in the data transfer stage. That is, based on the configuration of the memory cell array 10 of FIG. 4, an extended data line DQHLD whose potential is fixed thereto is arranged. The extended data line DQHLD is not connected to a memory cell, but the potential is controlled by a word line WL or a spare word line SWL. This extended data line DQH
The column replacement switch 60 shown in FIG.
Is provided with a selection switch for selecting the extended data line DQHLD.

FIG. 17 specifically shows the extended data line DQHL.
Data line stage potential setting circuit 17 for fixing the potential of D
1 shows a configuration example. The extension data line DQHLD is
Like other data lines DQ, a pair of data lines DQHLD
t, DQHLDc. In the example of the figure, the extended data line DQHLD is connected to the word lines WL <0>, <1>,.
NMOS to fix to ground potential VSS by control of
The transistors QN31, QN32,... Are provided. Further, NM for fixing to power supply potential VCC is controlled by spare word lines SWL <0>, <1>,.
OS transistors QN33, QN34,... Are provided.

With such a configuration, in the test mode,
Data reading is performed by incrementing the row address. When the word lines WL are sequentially selected, the data whose extension data lines DQHLDt and DQHLDc are sequentially fixed to VSS are read out to the test I / O. When the defective address is replaced, the extended data lines DQHLDt and DQHLDc selected by the spare word line SWL are set to VCC.
Is read out. Therefore, by reading the data in a timely manner, it is possible to verify how the row replacement is performed on the assumption that the test I / O multiplexer 5 is normal. Further, it can be confirmed whether or not the test I / O multiplexer 5 is normal by comparing with the expected value at the time of performing the same reading.

The access to the extended data line DQHLD is
By expanding the test mode to select the spare data line,
That is, it can be easily realized by expanding the column redundancy controller 40. FIG. 18 shows a configuration based on the column redundancy controller 40 shown in FIG. 8, with the addition of a selection circuit 181 for selecting the extended data line DQHLD.

The selection circuit 181 is a replacement signal Z <n> for selecting the extended data line DQHLD, which is obtained by expanding the same configuration as the dummy latch 42 and the selector 43 of the column redundancy controller that enables the selection of the spare data line SDQ during the test. And a selector 43a. Here, there is no need for a latch circuit for defective replacement.

In the test mode for accessing the spare data line SDQ, as described above, when the selection signal CAX is supplied, the spare data line S is supplied from the column redundancy controller 40 regardless of the value of the column selection signal CSL.
Replacement signals Z <0> to <n-1> for controlling column replacement switch 60 are output so that DQ is selected. The dummy latch circuit 42a of the selection circuit 181 outputs data such that a replacement signal Z <n> is output when the selection signal CAX is issued, for example, so that the data line DQ <n> is replaced with the extension data line DQHLD. Shall be retained.

When such a test operation of data line replacement is performed, as described above, not only the contents of the row redundancy can be verified by monitoring the data of the extended data line when the row address is incremented, but also the column gate 13 can be verified.
Verification is also possible. That is, a change in the read output of the data line DQ <n> connected to the column gate 13,
Extended data line D not connected to column gate 13
By comparing changes in the read output of the QHLD, the data transfer capability of the column gate 13 can be checked.

[Fixed potential output at data line stage] FIG.
Is an example in which a data line stage potential setting circuit 191 for fixing the potential is provided for a normal data line DQ and a spare data line SDQ for repairing a defective column, instead of an extended data line. In the example of FIG. 19, the control signal line COLRDp <
0>, which controls the data line DQ and the spare data line SDQ one by one alternately at VCC and VSS.
A case is shown in which an NMOS transistor transistor group 191b that is controlled by the control signal line COLRDp <1> and alternately fixes the potential of the data line DQ and the spare data line SDQ to VCC and VSS by two is provided.

In FIG. 19, to simplify the explanation,
Although shown in a simplified manner, the data line DQ and the spare data line SDQ are arranged in pairs. Therefore, in practice, the data line potential fixing transistor groups 191a and 191b shown in FIG.
It is prepared so that one of t and DQc is set to VCC and the other is set to VSS. Control signal lines COLRDp <0>, <1
>, A control signal is externally supplied.

In such a configuration, in the test mode, the control signal line COLRDp <0> or <1> is applied to fix the potentials of the data line DQ and the spare data line SDQ.
Read data. Thereby, expected value data determined by the fixed potentials of the data line DQ and the spare data line SDQ is read. That is, the control signal line COLRDp <
When “H” is given to 0>, the expected value data repeats “H”, “L”, “H”, and “L” with respect to the data line array, and the control signal line COLRDp < When “H” is given to 1>, the expected value data repeats “H”, “H”, “L”, and “L” with respect to the data line array.

Therefore, if the data is read out by incrementing the column address, it is possible to verify what kind of column replacement is performed by the column replacement switch 60 by comparing with the expected value data. If normal expected value data cannot be obtained, the column selection switch 60, the column redundancy controller,
A defect such as a test I / O multiplexer is assumed.

However, in the above test operation, preferably, the control signal lines COLRDp <0>, <1> simultaneously deactivate the column gates so that the bit lines are not connected to the data lines. Thus, the expected value data determined by fixing the data line potential can be read while the bit line is disconnected from the data line. Alternatively, the driving capability of the data line stage potential setting circuit 191 is set sufficiently large so that even when bit line data is transferred to the data line, the data line potential can be fixed regardless of the bit line data. In this case, the column gate need not be deactivated.

In FIG. 19, data line DQ and spare data line SDQ are connected to data line stage potential setting circuit 19 such that one of them is at VCC and the other is at VSS.
1 may be configured. As a result, similarly to the verification of the row replacement in the case of FIG. 17, the verification of the column replacement can be easily performed.

[Fixed potential output at data line stage] FIG. 20
Is an example in which a data line stage potential setting circuit 201 similar to that in FIG. 19 is provided. In this case, the data line stage potential setting circuit 201
Is controlled by a control signal line DQHLDp <0>,
NMOS transistor transistor group 20 for fixing all potentials of data line DQ and spare data line SDQ to VCC
1a and the control signal line DQHLDp <1>, and all data lines DQ and spare data lines SDQ are set to V
An NMOS transistor, which is fixed at the potential SS, is constituted by a transistor group 191b. Control signal line DQH
A control signal is externally supplied to LDp <0> and <1>.

With such a configuration, in the test mode, a control signal is externally supplied to the control signal line DQHLDp <0> or <1>, and data is written to the memory cell with the fixed data line potential. After that, the data line stage potential setting circuit 201 is deactivated, that is, the test mode is canceled to read data. Therefore, in this case, FIG.
Unlike the example, the test mode and the normal operation mode can be switched back and forth without damaging the memory cell data without suppressing the issuance of the column selection signal.
This makes it possible to verify a defect in the data transfer path on the memory cell side from the data line. Further, the following cause of failure can be estimated in relation to a failure generated as a result of a normal test by writing and reading test data from the I / O pad prior to the test by fixing the data line potential. That is, if the expected value data is normally read in the test with the data line potential fixed, it is assumed that the cause of the failure in the normal test is a write system on the I / O pad side from the data line.

[Fixed potential output at data input / output line stage] FIG. 2
In the system LSI configuration shown in FIG. 21, an extended data input / output line 211 is added to the test I / O multiplexer 5 for inputting / outputting test data, as shown in FIG. As the extension data input / output line 211, a fixed VCC and a fixed VSS are prepared.

Alternatively, as shown in FIG.
Test I / O pad in I / O multiplexer 5 <
0:15>, an extended data input / output line 212 is added for each multiplexer MUX. These extended data input / output lines 212 also have a fixed VCC and a fixed VSS.

These potential-fixed extended data input / output lines 2
11 or 212 can be selected by expanding the command decoder 8. With such a configuration, in the test mode, the extended data line input / output 211 or 212 is selected and read. At this time, if the read data is not the expected value, it is understood that there is a problem in the test multiplexer 5, the command decoder 8, or the test circuit system outside the input / output pad.

In the above embodiment, the system LSI is targeted, and the memory therein, particularly the DRAM, is focused on.
Although the case where the test potential setting circuit for facilitating the failure analysis is provided has been described, a similar method is used for an SRAM or an EEPROM.
The present invention can be applied not only to a system LSI equipped with another memory such as M, but also to a semiconductor memory alone.

[0065]

As described above, according to the present invention, the data access is performed by setting any part of the data transfer path from the memory cell to the data input / output pad to a predetermined potential, thereby causing a failure. The location can be easily specified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a system LSI according to the present invention.

FIG. 2 is a diagram showing a configuration of a test circuit system of the system LSI.

FIG. 3 is a diagram showing a configuration of a DRAM of the system LSI.

FIG. 4 is a diagram showing a configuration of a cell array of the DRAM.

FIG. 5 is a diagram showing a relationship between data lines and bit lines of the DRAM.

FIG. 6 is a diagram showing a specific configuration of a cell array of the DRAM.

FIG. 7 is a diagram showing a configuration of a row decoder / row redundancy controller of the DRAM.

FIG. 8 is a diagram showing a configuration of a column redundancy controller of the DRAM.

FIG. 9 is a diagram showing a configuration example of a column replacement switch of the DRAM.

FIG. 10 is a diagram showing another configuration example of the column replacement switch of the DRAM.

FIG. 11 is a diagram showing a configuration of a test multiplexer of the DRAM.

12 is a diagram showing an example in which a cell node stage potential setting circuit is provided for the cell array configuration of FIG. 6;

13 is a diagram showing an extension circuit of a row redundancy controller for selecting an extension word line of the cell node stage potential setting circuit of FIG. 12;

14 is an example in which an extended bit line and a bit line stage potential setting circuit are provided for the cell array configuration of FIG. 4;

15 is a diagram showing a specific circuit configuration of an extended bit line unit of FIG.

FIG. 16 is a diagram showing a configuration in which extended data lines are arranged in the cell array configuration of FIG. 4;

17 is a diagram showing a data line stage potential setting circuit for fixing the potential of the extended data line of FIG. 16;

18 is a diagram showing an extension circuit of a column redundancy controller for selecting an extension data line in FIG.

FIG. 19 is a diagram showing a configuration of another data line stage potential setting circuit.

FIG. 20 is a diagram showing a configuration of another data line stage potential setting circuit.

FIG. 21 is a diagram showing an example in which a data input / output line stage potential setting circuit is provided for a test I / O multiplexer.

FIG. 22 is a diagram showing another example in which a data input / output line stage potential setting circuit is provided for a test I / O multiplexer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory, 2 ... Logic, 5 ... Test I / O multiplexer, 10 ... Memory cell array, 12 ... Sense amplifier, 13 ... Column gate, 20 ... Row decoder / row redundancy controller, 30 ... Column decoder, 40
... column redundancy controller, 50 ... address buffer / command decoder, 60 ... column replacement switch, 121 ... cell node stage potential setting circuit, BLHLD
(BLHLDt, BLHLDc) ... extended bit line, DQ
HLD (DQHLDt, DQHLDc): extended data line; 171, 191, 201: data line stage potential setting circuit; 211, 212: extended data input / output line.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 12/16 330 G01R 31/28 B G11C 11/401 G11C 11/34 371A 371D F-term (reference) 2G032 AA03 AA07 AB20 AC03 AD05 AG02 AH04 AK14 5B018 GA03 HA21 JA12 MA40 QA13 5B024 AA15 BA05 BA13 BA15 BA18 BA29 CA07 CA17 CA27 EA04 5L106 AA01 CC17 DD12 EE03 GG05 GG07

Claims (16)

[Claims] 1. A semiconductor integrated circuit having a plurality of data transfer stages for sequentially transferring read / write data between a memory cell and a data input / output terminal and having a normal operation mode and a test mode, A test potential setting circuit for outputting a predetermined potential in a test mode in at least one of the data transfer stages. 2. The test potential setting circuit according to claim 1, further comprising: a signal selection circuit that outputs a selected signal in a normal operation mode according to a selection signal, and an extended signal selection circuit that selects and outputs the predetermined potential in a test mode. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 3. A test mode by the test potential setting circuit assigns an address to an address space for accessing a memory cell array so that a predetermined address selects the extension signal selection circuit instead of the signal selection circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is executed by: 4. The test potential setting circuit according to claim 1, wherein said test potential setting circuit is a cell node stage potential setting circuit that outputs a predetermined potential to a stage subsequent to a cell node of a memory cell array.
Or the semiconductor integrated circuit according to 2. 5. The cell node stage potential setting circuit is configured as an extended cell array of the memory cell array,
5. The semiconductor device according to claim 4, further comprising: an expanded word line obtained by expanding a word line of the memory cell array; and a transistor driven by the expanded word line, one end of which is connected to a bit line and the other end of which is connected to a predetermined potential. Semiconductor integrated circuit. 6. An address storage circuit storing a row address assigned to the extended word line, and detecting a coincidence between a row address input in a test mode and an address of the address storage circuit to perform a corresponding extended word line. 6. The semiconductor integrated circuit according to claim 5, further comprising an extended word line selection circuit including a match detection circuit for selecting a word line. 7. A redundant row cell array including a spare word line for replacing a defective word line, and a row redundancy controller for controlling replacement of the defective word line by the spare word line in response to input of a defective row address. 7. The semiconductor integrated circuit according to claim 6, wherein the extension word line selection circuit is configured as an extension circuit of the row redundancy controller. 8. The semiconductor integrated circuit according to claim 1, wherein the test potential setting circuit is a bit line potential setting circuit that outputs a predetermined potential to a stage subsequent to a bit line of a memory cell array. 9. The bit line stage potential setting circuit includes an extension bit line to which a memory cell configured as an extension cell array of a memory cell array is not connected, and an extension column gate for connecting the extension bit line to a data line. 9. The semiconductor integrated circuit according to claim 8, wherein: 10. The test potential setting circuit includes: an extended data line that is provided separately from a data line connected to a bit line of a memory cell array via a column gate and is not connected to the memory cell array; and a word of the memory cell array. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an extended data line stage potential setting circuit having a transistor driven by a line to set the potential of the extended data line. 11. The extended data line stage potential setting circuit,
A first transistor driven by a word line to connect the extended data line to a first potential and a spare word line driven by a spare word line for replacing a defective word line to connect the extended data line to a second potential The semiconductor integrated circuit according to claim 10, further comprising a second transistor. 12. The semiconductor integrated circuit according to claim 10, further comprising: an extension data line selection circuit for outputting a replacement signal for selecting said extension data line in place of a predetermined data line in a test mode. . 13. A spare data line for replacing a defective data line, and a column redundancy controller for outputting a replacement signal for selecting the spare data line in place of the defective data line in accordance with a column address, 13. The semiconductor integrated circuit according to claim 12, wherein the extension data line selection circuit is configured as an extension circuit of the column redundancy controller. 14. The test potential setting circuit according to claim 1, wherein said test potential setting circuit sets a data line connected to a bit line of a memory cell array via a column gate to a predetermined potential. Or the semiconductor integrated circuit according to 2. 15. The data line stage potential setting circuit includes a transistor having one end connected to each data line and a predetermined potential applied to the other end, and a control for driving these transistors by an external control signal in a test mode. 15. The semiconductor integrated circuit according to claim 14, comprising a signal line. 16. The test potential setting circuit is configured by adding an extended data input / output line set to a predetermined potential to an input side of a test I / O multiplexer for inputting / outputting test data. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a data input / output line stage potential setting circuit.