JP2002141359A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A low-temperature process (350 ° C. or lower, preferably 300 ° C. or lower) is realized, and an inexpensive semiconductor device is provided. The present invention relates to a semiconductor layer having a crystal structure.
After the formation of No. 3, an impurity region 107 (a region having an amorphous structure) was formed by simultaneously adding a p-type impurity element and a hydrogen element to a part of the crystalline semiconductor layer 103 using an ion doping method. After that, a low-resistance and amorphous impurity region 108 is formed by performing a heat treatment at 100 to 300 ° C., and the amorphous region is used as a source region or a drain region of the TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their development is particularly urgent as switching elements for image display devices (liquid crystal display devices and EL display devices).

[0004] T used as a switching element
In the FT, an amorphous silicon film or a polysilicon film is used as a semiconductor layer. When a glass substrate is used, the processing temperature in the TFT manufacturing process is 4 ° C.
It was about 00 ° C to 600 ° C. The polysilicon film is formed by laser crystallization or solid-phase crystallization (600 to 10
00 ° C.).

At present, glass substrates and quartz substrates are often used, but have a drawback that they are easily broken and heavy. Further, in mass production, it is difficult to increase the size of a glass substrate or a quartz substrate, which is not suitable. Therefore, an attempt has been made to form a TFT element on a flexible substrate, typically a flexible plastic film.

In the process of manufacturing a TFT, doping of an impurity element is indispensable and occupies a very important position in order to form a source region and a drain region. Typical doping methods of the impurity element include an ion implantation method and an ion doping method.

After the impurity element for imparting the p-type is added to the semiconductor layer by these impurity element doping methods, heat treatment for activation or irradiation with strong light such as laser has been essential.

Generally, the activation of the impurity element is 1000
It is said that heat treatment at a high temperature near ℃ is required,
When a glass substrate is used, heat treatment at a temperature higher than the strain point of the substrate cannot be performed.
600 ° C.), and the throughput was degraded. TF activated by heat treatment when using a glass substrate
In the manufacturing process of T, the processing temperature (500 ° C.)
６００600 ° C.) was the highest process temperature.

In addition, when a plastic substrate is used, the maximum temperature of the process must be lowered due to lower heat resistance, and as a result, a TFT having better electric characteristics than when a TFT is formed on a glass substrate cannot be formed. Is the current situation. Therefore, high-performance liquid crystal display devices and light-emitting elements using a plastic film have not been realized.

In particular, when the ion doping method is used,
When an impurity element imparting p-type is added, the doped region of the crystalline semiconductor layer is damaged by the impurity element, becomes an amorphous region, and has a high resistance. Therefore, conventionally, a heat treatment at 500 ° C. to 600 ° C. or a laser irradiation treatment restores the crystallinity of the source region and the drain region to lower the resistance.

Further, when an ion implantation method utilizing ion mass separation is used, the impurity concentration and implantation depth can be accurately controlled, but the ion beam width of the ion implantation apparatus is very small, so that a large substrate is used. It was not suitable for mass production.

When a laser beam is used for the activation, the activation process can be performed at a low temperature, but the controllability is poor, and the throughput is poor because it is necessary to perform the process for each substrate. In addition, when laser treatment is performed on a doped substrate, chamber contamination may occur, and a dedicated laser device or a modification of the device is required for activation, which leads to an increase in equipment cost. Occurs.

[0013]

The above-mentioned prior art T
In the manufacturing process of the FT, the substrate must be heated to 400 ° C. or higher, so there is no problem when a glass substrate is used as the substrate, but when a low heat-resistant substrate such as a plastic substrate is used, There has been a problem that it cannot withstand the heating temperature.

The present invention relates to a further low temperature process (300
° C or lower, preferably 250 ° C or lower) to enable the use of a low heat-resistant plastic substrate as an element formation substrate, and to simplify the process and improve the throughput.

[0015]

Conventionally, the crystallinity of an amorphous portion of a source region and a drain region formed during doping is recovered by high-temperature heat treatment (500 to 600 ° C.) for several hours or laser treatment. Otherwise, it was difficult to lower the resistance. The present invention can reduce the resistance of a source region or a drain region without performing such high-temperature heat treatment or laser light irradiation.

According to the present invention, a p-type impurity element and a hydrogen element are added at a low accelerating voltage to a semiconductor layer having a crystal structure (crystalline semiconductor layer) using an ion doping method.
By performing heat treatment at a temperature of 300 to 300 ° C., preferably 150 to 250 ° C., low-resistance source and drain regions are formed. That is, according to the present invention, a source region and a drain region having a low resistance at a low temperature for a short time can be formed.

In the present invention, at the time of ion doping,
It is important that hydrogen added at the same time as the impurity element imparting the p-type is present at a high concentration in the source region and the drain region.
Preferably, a heat treatment at 150 to 250 ° C. is performed to diffuse hydrogen, so that the resistance of the source region or the drain region can be reduced. Immediately after ion doping, the concentration of hydrogen contained in the source region and the drain region was 1 ×
10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²¹
１1 × 10 ²² / cm ³ or more.

In the present invention, the heat treatment in the steps after the ion doping is 400 ° C. or less, preferably 35 ° C.
It is important to keep the temperature below 0 ° C. Because 400 ℃
This is because, when heat treatment is performed to a certain degree, hydrogen is desorbed from the semiconductor film and escapes. That is, in the steps after the ion doping, heat treatment for desorbing hydrogen from the film and laser light irradiation are not performed.

In the present invention, the source region and the drain region are made amorphous by ion doping, but preferably doping conditions are set so as not to be completely amorphous. For example, by doping at a low acceleration voltage of 10 kV or less, the source region and the drain region are totally damaged and become amorphous. Further, it can be assumed that a large amount of impurity element is added to the amorphous portion, and that a large amount of hydrogen element is added simultaneously with the impurity element. That is, in the present invention, it is desirable to dope hydrogen and the impurity element simultaneously. In the case of doping only with hydrogen, since the mass number and the ionic radius are small, the doping penetrates a thin semiconductor film, and it is very difficult to add only to the upper layer portion.

The heat treatment of the present invention (100 to 300)
C)), if a high-temperature heat treatment is not performed, a region which is doped with an impurity element and becomes amorphous (also referred to as an amorphous region) remains as it is when the TFT is manufactured. That is, in the present invention, at the time of completion of the manufacture of a TFT, a channel formation region to which an impurity element is not doped has a mainly crystal structure, and a source region and a drain region have mainly an amorphous structure. Conventionally, the source region and the drain region are not left in an amorphous state, but are recrystallized by heat treatment or laser light.

According to the structure of the invention disclosed in this specification, in an electro-optical device including a pixel portion and a driving circuit on the same insulating surface, the pixel portion and the driving circuit are p-channel TFTs.
Wherein the channel forming region of the p-channel TFT has a mainly crystalline structure, and the source region or the drain region of the TFT has a mainly amorphous structure. is there. Here "mainly" means 50
% Or more.

In the above structure, the insulating surface is a surface of an insulating film provided on a plastic substrate.

Further, the semiconductor layer of the p-channel TFT is formed by a sputtering method, a PCVD method, an LPCVD method, a vacuum evaporation method, or a photo CVD method.

Conventionally, since a plastic substrate has a limit in terms of heat resistance, TF having excellent properties is formed on a plastic substrate.
Making T was very difficult.

Also, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
The heat treatment may be performed at 0 ° C., and the order of the steps is not particularly limited.

If a hydrogenation treatment (hydrogen plasma treatment, heat treatment in a hydrogen atmosphere, or the like) is performed at 100 to 300 ° C., preferably 150 to 250 ° C. instead of the above heat treatment, a higher concentration of hydrogen can be added to the film. And a synergistic effect can be obtained. In this case, the number of heat treatment steps can be reduced, and the throughput is improved. In addition, a TFT manufacturing process other than the hydrogenation process,
The same effect (reducing the resistance of the source region and the drain region) can be obtained even at a temperature of about 300 ° C.

The structure of the TFT is not particularly limited, and may be a top gate type TFT or a bottom gate type TFT.

Further, if all the circuits on the same substrate, that is, the drive circuit and the pixel TFT are formed only by the P-channel TFT, the number of masks is reduced and the yield is improved.

Further, according to the structure of the invention for realizing the above structure, a first step of forming a semiconductor layer having a crystal structure on an insulating surface, and forming an insulating layer on the semiconductor layer having the crystal structure A second step, a third step of forming a conductive layer over the insulating layer, and simultaneous addition of an impurity element imparting a p-type to part of the semiconductor layer having a crystal structure and hydrogen by an ion doping method. A fourth step of forming an amorphous region by performing heat treatment, and a fifth step of performing a heat treatment to reduce the resistance value of the amorphous region so that the amorphous region becomes a source region or a drain region. A method for manufacturing a semiconductor device, comprising: Note that a top gate TFT is formed by these steps.

In the above structure, the conductive layer is a gate electrode, and when adding the impurity element imparting p-type and hydrogen, the impurity element is added to an upper layer portion of the semiconductor layer using the conductive layer as a mask. I have.

Further, according to another aspect of the present invention, there is provided a first step of forming a conductive layer on an insulating surface, a second step of forming an insulating layer on a conductive layer, and a step of forming a conductive layer on the insulating layer. A third step of forming a semiconductor layer having a crystal structure, and forming a part of the semiconductor layer having a crystal structure by p-type ion doping.
A fourth step of forming an amorphous region by adding an impurity element for imparting a mold and hydrogen to form an amorphous region, and performing a heat treatment to reduce the resistance value of the amorphous region. Or a fifth step of forming a drain region. Note that a bottom gate type TFT is formed by these steps.

In the above structure, the heat treatment is performed for 100 hours.
The heat treatment is performed at about 300 ° C. to reduce the resistance of the source region and the drain region. Further, the heat treatment may be a heat treatment in a hydrogen atmosphere.

Alternatively, in the above structure, the heat treatment may be performed by a hydrogen plasma treatment at 100 to 300 ° C. to lower the resistance of the source region and the drain region.

In each of the above structures, the insulating surface is a surface of an insulating film provided on a plastic substrate.

In each of the above structures, the manufacturing process temperature after the step of adding the impurity element imparting p-type and hydrogen is 350 ° C. or lower, preferably 300 ° C. or lower.

Each of the above structures is characterized in that the amorphous region is not recrystallized in a manufacturing process after the step of adding an impurity element imparting p-type and hydrogen.

The present invention is very suitable for a plastic substrate because it reduces the electric resistance of the source region and the drain region by heat treatment at a low temperature. It goes without saying that it can be applied. Even when applied to a glass substrate or a quartz substrate, effects such as reduction in cost and improvement in throughput due to reduction in process temperature can be obtained.

[0038]

Embodiments of the present invention will be described below. FIG. 1 shows an example of the TFT manufacturing method of the present invention.

First, a base insulating film 102 is formed on a substrate 101. As the substrate 101, a plastic substrate is used. For example, polyimide, acrylic, PET (polyethylene terephthalate), polycarbonate (PC), polyarylate (PAR), PEEK (polyetheretherketone), PES (polyethersulfone), PEN (polyether) Nitrile), nylon, polysulfone (PS
F), a plastic substrate made of polyetherimide (PEI), polybutylene terephthalate (PBT), or the like can be used. Here, an example is shown in which a substrate made of polyimide that can sufficiently withstand heat treatment at 350 ° C. is used.

The base insulating film 102 is formed by a sputtering method. In the case of using a plasma CVD method, the film may be formed at a substrate temperature of room temperature to 300 ° C.

Next, an amorphous semiconductor film is formed on the base insulating film 102 by a known technique (sputtering, PCVD, LPCV, etc.).
D method, vacuum evaporation method, photo-CVD method, etc.). Next, the amorphous semiconductor film is crystallized by a known technique,
A crystalline semiconductor film is formed. However, when a plastic substrate is used, it cannot withstand a heat treatment at over 400 ° C., and therefore it is preferable to crystallize by irradiation with laser light. Note that in the case of crystallization by laser light irradiation, before the irradiation, the hydrogen content of the amorphous semiconductor film is reduced to 5%.
Since the content needs to be atom% or less, a film formation method or a film formation condition in which the hydrogen concentration is low immediately after the film formation is preferable.

As the laser beam, a gas laser such as an excimer laser, a solid laser such as a YVO ₄ laser or a YAG laser, or a semiconductor laser may be used. Further, the form of laser oscillation may be any of continuous oscillation and pulse oscillation, and the shape of the laser beam may be any of linear, rectangular, circular, and elliptical. The wavelength used may be any of the fundamental wave, the second harmonic, and the third harmonic. Further, the scanning method may be any of a vertical direction, a horizontal direction, and an oblique direction, and may be reciprocated.

Next, the crystalline semiconductor film is patterned to form a semiconductor layer 103 serving as an active layer of the TFT. Next, a gate insulating film 104 which covers the semiconductor layer 103 is formed. (FIG. 1A) The gate insulating film 104 is formed by a sputtering method or a plasma CVD method.

Next, the gate electrode 10 is formed on the gate insulating film.
5 is formed. (FIG. 1B) The gate electrode 105 is formed by patterning a conductive film formed by a sputtering method into a desired shape.

Next, the insulating film is etched using the gate electrode 105 as a mask to form a gate insulating film 106. (Fig. 1 (C))

Next, an impurity element (boron) for imparting a p-type is doped in a self-aligned manner by using an ion doping method. (FIG. 1D) In this doping, it is important to add hydrogen simultaneously with boron, and the upper layer portion of the semiconductor region to which boron and hydrogen are added becomes amorphous. For example, doping is performed using BH and B ₂ H _X. At this time, the acceleration voltage is set to about 1 to 20 kV.
Note that it is preferable to appropriately adjust doping conditions (acceleration voltage and the like). In addition, it is preferable that doping conditions (such as the pressure in a doping chamber) be appropriately adjusted so that more hydrogen is added than boron.

Next, the resistance of the source region and the drain region is reduced by a heat treatment at 150 to 300 ° C. (Figure 1
(E) Hydrogen is diffused by the heat treatment at a low temperature to lower the resistance of the semiconductor region 107 to be a source or drain region. However, the region to which boron is added remains in an amorphous state. At the temperature of this heat treatment (300 ° C. or lower), the crystallinity of the region which has been made amorphous by doping does not recover.

Next, after forming an interlayer insulating film 110 and forming a contact hole reaching the source or drain region, a source wiring 111 electrically connected to the source region and a drain wiring 112 electrically connected to the drain region are formed. To form

Next, a hydrogenation process is performed to improve the TFT characteristics. As the hydrogenation, heat treatment in a hydrogen atmosphere or plasma hydrogenation at a low temperature is performed. Here, heat treatment is performed at 350 ° C. for one hour in a hydrogen atmosphere.

By the above manufacturing steps, a top gate type T is formed on a plastic substrate at a process temperature of 400 ° C. or less.
FT is completed. (FIG. 1F) If plasma hydrogenation is performed at a low temperature in the hydrogenation process, a TFT is completed on a plastic substrate at a process temperature of 300 ° C. or less.

The TFT thus obtained has a very low sheet resistance in the source region or the drain region despite its amorphous state. The sheet resistance immediately after the doping shows a value of about 2 kΩ / □, while the sheet resistance after heat treatment at a low temperature (250 ° C. to 350 ° C., 4 hours) shows a value of 900 Ω / □ or less. Showed a very low value of about 700Ω / □.

The following experiment was conducted.

First, an amorphous silicon film is formed on a substrate by a sputtering method and laser-processed (XeCl laser,
At 30 Hz, 1 mm / sec), phosphorus was added to the crystallized polysilicon film using an ion doping method. The sputtering condition for the amorphous silicon film is a substrate temperature of 150.
° C, deposition pressure 0.4 Pa, sputtering power 3 kW, A
The r flow rate was 50 sccm. Diborane gas diluted with hydrogen was used, and the doping dose was 5 × 10 ¹⁵ / cm ² , 1 × 10 ¹⁶ / cm ² , and 2 × 10 ¹⁶ / cm ² , respectively.
The conditions were varied as cm ² , 3 × 10 ¹⁶ / cm ² .

The substrate provided with the polysilicon film to which phosphorus was added at the respective dose amounts was placed at 150 ° C., 250 ° C.
The conditions were varied at 350 ° C., 450 ° C., and 550 ° C. (Comparative Example). In addition, heat treatment is performed for 4 hours at each temperature,
Thereafter, the respective electric resistance values, here, sheet resistance values were measured.

FIG. 7 shows the measurement result when the thickness of the polysilicon film is 50 nm, and the thickness of the polysilicon film is 70 nm.
FIG. 8 shows the measurement result of m.
FIG. 9 shows the measurement results at 00 nm.

As shown in the measurement results of FIG. 7, the resistance is greatly reduced after the heat treatment. When the heat treatment temperature is set to 150 ° C., the resistance of the semiconductor region to which the impurity is added rapidly decreases. When comparing before and after the heat treatment, the sheet resistance after the heat treatment was reduced to about half that before the heat treatment. This is considered to be due to the temperature at which hydrogen starts to diffuse freely in the film (equilibrium temperature of hydrogen glass (around 130 ° C.)). This diffusion of hydrogen occurs more easily as the dangling bond density is higher and the impurity element concentration (boron concentration) is higher.

FIG. 10 is a diagram showing a Raman scattering spectrum of a silicon film after doping a 50-nm-thick polysilicon film with phosphorus. This doped silicon film can be considered to be the same as a source region or a drain region when a TFT is manufactured. Wave number 500-520
/ Cm- ¹ has a maximum value regarding the scattering intensity. Heating at 550 ° C. or less indicates that most are amorphous. This indicates that when a TFT is manufactured, the heat treatment at 550 ° C. or lower does not recrystallize the source region and the drain region and mainly remains amorphous. As described above, according to the present invention, the sheet resistance value can be reduced even when the source region and the drain region are amorphous.

In this specification, the term “crystalline” refers to a wave number of 500 to 520 / cm in a Raman scattering spectrum of a silicon film.
-Refers to a crystal structure having a strong peak in the range of ¹ .

In a heat treatment at 150 ° C., a time dependency experiment was also conducted. As a result, it was found that the sheet resistance value was greatly reduced in the initial stage (several minutes). From the experimental results, the heat treatment of the present invention (100 to 300 ° C., preferably
A few minutes is sufficient for the time required for the temperature (50-250 ° C.).

When the heat treatment in a nitrogen atmosphere was compared with the heat treatment in a hydrogen atmosphere, the sheet resistance was lower in the hydrogen atmosphere. The sheet resistance of a sample obtained by performing a heat treatment at 350 ° C. for 4 hours under a nitrogen atmosphere is as follows:
In contrast to the value of 839 Ω / □, the sheet resistance of the sample which was heat-treated at 350 ° C. for 4 hours in a hydrogen atmosphere showed a very low value of 582 Ω / □.

Japanese Unexamined Patent Publication No. 6-104280 discloses a technique of injecting and activating protons simultaneously with the addition of an impurity element by an ion doping method. The formed region is finally crystallized into a polycrystalline state, which is different from the present invention. Further, in the publication, the sheet resistance is low immediately after doping, which is different from the present invention. In the present invention, the sheet resistance immediately after doping is as high as about 20 kΩ / □. In addition, this self-activation technique is not suitable for a plastic substrate because the semiconductor layer becomes extremely hot due to a high dose and a high acceleration voltage.

A technique of forming a silicide simultaneously with the addition of impurity atoms by a doping method to reduce the resistance of a source region and a drain region is disclosed in Japanese Patent Application Laid-Open No. Hei 8-181302.
As described in the above publication, the region to which the impurity element is similarly added is crystallized into a polycrystalline state, which is different from the present invention. In this publication, the sheet resistance is low immediately after doping, which is different from the present invention. In the present invention, the sheet resistance immediately after doping is as high as about 20 kΩ / □. Also,
Since silicide is formed, there is a concern that TFT characteristics may be deteriorated due to a metal element forming silicide.

Also, unlike conventional laser activation,
The heat treatment at a low temperature (350 ° C. or lower) of the present invention can process a large amount of substrates at one time, and thus improves the throughput.

The present invention is not limited to the structure shown in FIG.
If necessary, a lightly doped drain (LDD) structure having an LDD region between a channel formation region and a drain region (or a source region) may be employed. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. Furthermore, a so-called GOLD (Gate-drain Overlapped) in which an LDD region is arranged so as to overlap with a gate electrode via a gate insulating film.
(LDD) structure. Further, regions or layers containing a high concentration of hydrogen element may be formed in these LDD regions or GOLD regions.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0066]

[Embodiment 1] In the present invention, the pixel portion and the driving circuit are all p-channel T by a low temperature process of 350 ° C. or less.
It is characterized by being formed by FT. Therefore, in this embodiment, a manufacturing process for forming a pixel TFT on a plastic substrate will be described below.

First, a plastic substrate 2 made of an organic substance
01 is prepared. In this embodiment, a substrate 201 made of polyimide is used. The heat-resistant temperature of this polyimide substrate is about 399 ° C., and the color of the substrate itself is not transparent but brown. Next, the base insulating film 2 is formed on the substrate 201.
02 is formed. This base insulating film has a process temperature of 30.
There is no particular limitation as long as the film formation method does not exceed 0 ° C., and the film was formed by a sputtering method here.

Next, an amorphous semiconductor film is formed and crystallized by laser irradiation to form a crystalline semiconductor film.
The amorphous semiconductor film is not particularly limited as long as the process temperature does not exceed 300 ° C., and is formed here by a sputtering method. Next, the semiconductor layer 203 is formed by patterning the crystalline semiconductor film into a desired shape. Next, a gate insulating film 204 which covers the semiconductor layer 203 is formed. The gate insulating film is not particularly limited as long as the process temperature does not exceed 300 ° C., and is formed here by a sputtering method. (Fig. 2 (A))

Next, a gate electrode 205 is formed.
(FIG. 2B) As the gate electrode 205, Ta, W,
It may be formed of an element selected from Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.

Next, the gate insulating film is etched in a self-aligned manner using the gate electrode as a mask to form the gate insulating film 20.
6, an impurity region 207 is formed by exposing a part of the semiconductor layer and then adding (doping) an impurity element imparting p-type to the part of the semiconductor layer, here, boron. (Fig. 2 (C))

In this embodiment, the doping is performed after the etching of the gate insulating film. However, after the gate electrode is formed, the doping may be performed through the gate insulating film. In this case, the impurity element passes through the gate insulating film,
Doping is performed in a self-aligned manner using the gate electrode as a mask.

Next, a heat treatment is performed at 150 ° C. to 350 ° C. for at least 2 minutes, considering the margin, for 10 minutes or more to form an impurity region 208 having a low sheet resistance by the action of hydrogen contained in the semiconductor layer. (FIG. 2 (D))

Next, after forming an interlayer insulating film 210 and forming a contact hole reaching the source region or the drain region, the source wiring 211 electrically connected to the source region and the pixel electrode 21 electrically connected to the drain region are formed.
Form 2

Next, a hydrogenation process is performed to improve the TFT characteristics. As the hydrogenation, heat treatment in a hydrogen atmosphere (350 ° C., 1 hour) or plasma hydrogenation at a low temperature is performed.

By the above manufacturing steps, a top gate type T is formed on a plastic substrate at a process temperature of 400 ° C. or less.
FT is completed. (FIG. 2 (E)) Although the source region and the drain region of the TFT completed according to the present embodiment are mainly amorphous, the sheet resistance value is very low at about 680Ω. If necessary, a passivation film made of an inorganic insulating film may be formed.

The TFT (single) completed according to this embodiment
Rugated structure) showed good values. Figure
FIG. 18 shows the TFT characteristics (VI characteristics). Also, V
Indicates the voltage value at the rising point in the -I characteristic graph
The threshold value (Vth) is -2.644V.
The S value is 0.299 (V / dec), the mobility
(Μ _FE) Is 72.5 (cm)^Two/ Vs) and excellent
ing.

Thereafter, the reflective liquid crystal display device is completed through the steps of forming the alignment film 216a, rubbing, bonding the alignment film 216b and the counter substrate 214 having the counter electrode 215, and injecting the liquid crystal 213.

Here, as the pixel electrode 212, a metal material having reflectivity, for example, a material mainly containing Al, Ag, or the like was used. In this embodiment, an example of a reflection type liquid crystal display device is shown. However, a transparent conductive film such as ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), Zinc oxide (Zn
By using O) or the like, a transmission type liquid crystal display device can be formed.

A basic logic circuit can be formed by using the P-channel TFT shown in this embodiment, or a more complicated logic circuit (a signal dividing circuit, an operational amplifier, a gamma correction circuit, etc.) can be formed.

In the TFT shown in this embodiment, an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) is added to a semiconductor to be a channel formation region. Thereby, the enhancement type and the depression type can be separately formed.

When a PMOS circuit is formed by combining P-channel TFTs, the enhancement type TF
When formed by T (hereinafter referred to as EEMOS circuit)
And an enhancement type and a depletion type (hereinafter referred to as an EDMOS circuit). By combining these circuits, all the driving circuits of the liquid crystal display device can be constituted by P-channel TFTs.

[Embodiment 2] In this embodiment, an example in which the resistance of an impurity region is reduced at the same time as the heat treatment in hydrogenation is shown in FIG.
Shown in Since the steps up to the doping step are the same as those in the first embodiment, detailed description will be omitted.

First, according to the first embodiment, a base insulating film 302, a semiconductor layer 303, and a gate insulating film 30 are formed on a substrate 301.
4 is formed. (FIG. 3A) Next, a gate electrode 305 is formed as in the first embodiment. (FIG. 3 (B)). Next, as in the first embodiment, the gate insulating film 306 is formed by etching. (FIG. 3 (C)).

Then, as in the first embodiment, the gate electrode 3
Using the mask 05 as a mask, an impurity element is added in a self-aligned manner to form an impurity region. (FIG. 3 (D))

Next, the interlayer insulating film 31 is not heat-treated.
After forming 0 and forming a contact hole reaching a source region or a drain region, a source wiring 311 electrically connected to the source region and a drain electrode 312 electrically connected to the drain region are formed.

Next, a hydrogenation process is performed to improve the TFT characteristics. As this hydrogenation, a heat treatment (350 ° C., 1 to 4 hours) in a hydrogen atmosphere is performed. At the same time as the hydrogenation, the resistance of the source region and the drain region is reduced. The source region and the drain region of the TFT completed according to the present embodiment (heat treatment at 350 ° C. for 4 hours in a hydrogen atmosphere) are mainly amorphous, but have a sheet resistance of about 58%.
It was a very low value of 0 kΩ.

As described above, since the resistance of the source region and the drain region can be reduced by the heat treatment at a low temperature, the heat treatment process performed only for the activation is omitted, and the source region and the drain region are simultaneously formed with the hydrogenation. The resistance of the region could be reduced.

In this embodiment, an example is shown in which the resistance of the source region and the drain region is reduced at the same time as the hydrogenation. However, the present invention is not particularly limited. Is a process in which a heat treatment at 150 to 250 ° C. is applied (for example, formation of an interlayer insulating film,
The formation of a passivation film, etc.).

[Embodiment 3] In Embodiment 1, a TFT having a top gate structure (specifically, a planar type TF
Although T) has been exemplified, the present invention is not limited to the TFT structure, and can be applied to a TFT having a bottom gate structure.

In this embodiment, typically, an inverted staggered TFT is used.
FIG.

First, a plastic substrate 4 made of an organic substance
Prepare 00. Note that a base insulating film 4 for preventing diffusion of impurities from the substrate and improving the electrical characteristics of the TFT.
01 is provided. As a material of the base insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (Si
Ox Ny), or a laminated film of these,
It can be used in a thickness range of nm, and as a forming means, a thermal CVD method, a plasma CVD method, an evaporation method, a sputtering method,
A formation method such as a reduced pressure thermal CVD method can be used.

Next, a gate wiring (including a gate electrode) 402 having a single-layer structure or a laminated structure is formed. As a means for forming the gate wiring 402, a thermal CVD method, a plasma CVD method, a low-pressure thermal CVD method, an evaporation method, a sputtering method, or the like is used to form the gate wiring 402, preferably 10 to 1000 nm, preferably 30 to 300 nm.
After forming a conductive film having a thickness in the range described above, the conductive film is formed by a known patterning technique. As a material of the gate wiring 402, a material mainly containing a conductive material or a semiconductor material,
For example, Ta (tantalum), Mo (molybdenum), Ti
(Titanium), W (tungsten), chromium (Cr), etc., high melting point metal materials, silicide which is a compound of these metal materials and silicon, N-type or P-type conductive polysilicon, etc., low resistance Metal material Cu (copper), Al
Any structure having at least one material layer containing (aluminum) as a main component can be used without particular limitation.

Next, a gate insulating film is formed. As the gate insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), an organic resin film (BC)
B (benzocyclobutene) film, a laminated film of these, or the like can be used in a thickness range of 100 to 400 nm. Thermal CVD, plasma C
A formation method such as a VD method, a low-pressure thermal CVD method, an evaporation method, a sputtering method, or a coating method can be used. Here, FIG.
As shown in FIG. 2A, a gate insulating film 403 having a stacked structure
a and 403b were used. Lower gate insulating film 403a
Is to form a silicon nitride film or the like having a thickness of 10 nm to 60 nm for effectively preventing diffusion of impurities from a substrate or a gate wiring.

Next, an amorphous semiconductor film is formed. As the amorphous semiconductor film 404, an amorphous silicon film containing silicon as a main component is 20 to 100 nm, more preferably 2 to 100 nm.
It can be used in a film thickness range of 0 to 60 nm. As a means for forming an amorphous semiconductor film, thermal CVD, plasma CV
A formation method such as a D method, a low pressure thermal CVD method, an evaporation method, and a sputtering method can be used.

The gate insulating films 403a, 403
If b and the amorphous semiconductor film are formed continuously without exposure to the air, favorable interface characteristics can be obtained because impurities do not enter the interface between the gate insulating film and the amorphous semiconductor film.

Next, after the amorphous semiconductor film is crystallized to form a crystalline semiconductor film, the obtained crystalline semiconductor film is patterned into a desired shape. (FIG. 4 (A))
Note that there is no particular limitation on the order in which the semiconductor film is patterned, and for example, the patterning may be performed after addition of an impurity element.
As the crystallization treatment, a crystallization method using laser light irradiation may be used. Also, if the natural oxide film on the surface of the amorphous semiconductor film is removed with a hydrofluoric acid-based etchant such as buffered hydrofluoric acid immediately before this crystallization treatment, silicon bonds near the surface are terminated with hydrogen and bonded to impurities. This is preferable because it becomes difficult to form a favorable crystalline semiconductor film.

Next, an insulating layer 405 is formed over the crystalline semiconductor layer 404. This insulating layer 405 protects the channel formation region during the step of adding the impurity element. This insulating layer 4
Reference numeral 05 denotes a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), an organic resin film (BCB).
Film), or a laminated film of these films or the like can be used in a thickness range of 100 to 400 nm. The insulating layer 405 is formed using a known patterning technique, for example, normal exposure or backside exposure. (FIG. 4 (B))

Next, using the insulating layer 405 as a mask,
A doping step of adding an impurity element imparting p-type to the crystalline semiconductor film is performed, so that an impurity region 406 is formed. (FIG. 4C) As an impurity element that imparts p-type to a semiconductor material, an impurity element belonging to Group 15 of the Group 15, for example, B can be used. In this step, B (boron) is added to the crystalline semiconductor film whose surface is exposed by appropriately setting doping conditions (dose amount, acceleration voltage, and the like) by a plasma doping method. As another doping method, an ion implantation method can be used. The impurity region 406 is a high-concentration impurity region and will be a source / drain region later.

Next, heat treatment (at 150 to 350 ° C. for one hour or more) is performed to form an impurity region 407 having a low sheet resistance by the action of hydrogen contained in the semiconductor layer. The source region and the drain region of the TFT completed according to the present embodiment are mainly amorphous, but have a sheet resistance of about 5 kΩ.
And very low values.

Next, an interlayer insulating film 408 is formed on the entire surface. As the interlayer insulating film 408, any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film (a polyimide film, a BCB film, or the like) or a stacked film thereof can be used.

Next, after forming a contact hole by using a known technique, wirings 409 and 410 are formed to obtain a state shown in FIG. The wirings 409 and 410 function as a source wiring or a drain wiring. Finally, heat treatment is performed in a hydrogen atmosphere, and the whole is hydrogenated to complete a P-channel TFT.

Further, in this embodiment, the example in which the patterning of the active layer is performed before the formation of the insulating layer 405 is described. However, the present invention is not particularly limited. For example, before the crystallization step, before the doping, or after the heat treatment. May go.

In this embodiment, a step of adding a trace amount of an impurity element to the channel formation region to control the threshold value of the TFT (also referred to as a channel doping step) may be added.

This embodiment can be combined with the second embodiment.

[Embodiment 4] An example of manufacturing a liquid crystal display panel using the active matrix substrate obtained by any one of Embodiments 1 to 3 will be described below.

The top view shown in FIG. 5 shows a pixel portion, a driving circuit,
FPC (Flexible Printed Wiring Board: Flexible Print
An active matrix substrate on which an external input terminal to which an ed circuit is attached, a wiring 81 for connecting the external input terminal to the input portion of each circuit, and the like, and a counter substrate 82 provided with a color filter and the like are formed of a sealing material 83. Are pasted together.

A light-shielding layer 86a is provided on the counter substrate side so as to overlap with the gate-side drive circuit 84.
5, a light shielding layer 86b is formed on the counter substrate side. In the color filter 88 provided on the counter substrate side on the pixel portion 87, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displayed, red (R)
, A green (G) colored layer, and a blue (B) colored layer, a color display is formed, and the arrangement of the colored layers of these colors is arbitrary.

Here, the color filter 88 is provided on the opposite substrate for colorization, but is not particularly limited.
When manufacturing an active matrix substrate, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer is provided between adjacent pixels in the color filter to shield portions other than the display area from light. Here, the light-blocking layers 86a and 86b are provided also in a region covering the driving circuit. However, the region covering the driving circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, without providing the above-mentioned light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield the light by a stacked layer of a plurality of layers, and the portion other than the display region ( The gap between each pixel electrode) and the driving circuit may be shielded from light.

Further, an FPC 89 comprising a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

The liquid crystal display device manufactured as described above can be used as a display unit of various electronic devices.

FIG. 6 is a block diagram of the liquid crystal display device. FIG. 6 shows a circuit configuration for performing analog driving. In this embodiment, the source-side drive circuit 9
0, a pixel portion 91 and a gate-side drive circuit 92. In this specification, a drive circuit is a generic term including a source-side processing circuit and a gate-side drive circuit.

The source side driving circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate-side drive circuit 92 includes a shift register 92a, a level shifter 92
b, a buffer 92c is provided. If necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

In this embodiment, the pixel section 91 includes a plurality of pixels, and each of the plurality of pixels is provided with a TFT element.

The source-side drive circuit 90 and the gate-side drive circuit 92 are all formed by P-channel TFTs.
All circuits are formed using an EEMOS circuit as a basic unit. However, power consumption is slightly increased as compared with the conventional CMOS circuit.

Although not shown, a gate-side drive circuit may be further provided on the opposite side of the gate-side drive circuit 92 across the pixel portion 91.

This embodiment can be freely combined with any one of Embodiments 1 to 3.

[Embodiment 5] In this embodiment, the pixel structure is shown in FIG.
1 and the cross-sectional structure is shown in FIG. A-
A ′ sectional view and BB ′ sectional view are shown.

In this embodiment, the storage capacitor is formed by using the insulating film on the second semiconductor layer 1002 as a dielectric,
002 and the capacitor electrode 1005. In addition,
The capacitor electrode 1005 is connected to the capacitor wiring 1009. Further, the capacitor electrode 1005 is formed over the same insulating film as the first electrode 1004 and the source wiring 1006 at the same time. In addition, the capacitor wiring includes the pixel electrode 1011 and the connection electrode 1.
010 and the gate wiring 1007 are formed simultaneously on the same insulating film.

In this embodiment, the impurity region 1012
An impurity element imparting a p-type is added to -1014. Note that reference numeral 1012 denotes a source region, and 1013 denotes a drain region.

In this embodiment, the example in which the gate electrode and the source wiring are formed simultaneously has been described. However, the number of masks is increased by one, and the gate electrode, the first electrode, and the capacitor wiring are formed in different steps. Is also good. That is, first, only a portion which overlaps with the semiconductor layer and serves as a gate electrode is formed, a p-type impurity element is added, heat treatment is performed at a low temperature, and then a first electrode is formed to overlap the gate electrode. At this time, a contact between the gate electrode and the first electrode is formed by mere overlapping without forming a contact hole. Further, a source wiring and a capacitor wiring are formed at the same time as the first electrode. This makes it possible to use low-resistance aluminum or copper as the material of the first electrode and the source wiring.
Further, a p-type impurity element is added to a semiconductor layer which overlaps with the capacitor wiring, so that the storage capacity can be increased.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured using the TFT obtained in Embodiment 3 will be described below with reference to FIGS. In this embodiment, the TFTs used for the pixel portion and the driving circuit are all constituted by P-channel TFTs.
It is an example of an L display device.

FIG. 13 shows an example of a light emitting device having a pixel portion and a drive circuit for driving the pixel portion over the same insulator (but before sealing). It should be noted that the drive circuit has a basic unit of MO.
5 illustrates an S circuit, and illustrates one pixel in a pixel portion.

In FIG. 13, reference numeral 1501 denotes a plastic substrate. First, a base insulating film is formed on the plastic substrate 1501 according to the embodiment.

A P-channel TFT 15 is formed on the underlying insulating film.
04, a driving circuit including a P-channel TFT 1505;
Switching TFT 150 composed of P-channel TFT
Current control TFT 1 comprising 6 and P-channel type TFT
507 are formed. Note that the description of the P-channel TFT is omitted because Embodiment 1 may be referred to. Also,
In this embodiment, all the TFTs are formed of bottom gate type TFTs.

The switching TFT has a structure having two channel forming regions between the source region and the drain region (double gate structure). However, the present invention is not particularly limited, and one channel forming region is formed. Or a triple gate structure formed by three.

Further, before the second interlayer insulating film is provided on the drain region of the current control TFT, a contact hole is provided in the first interlayer insulating film. This is to simplify the etching process when forming a contact hole in the second interlayer insulating film. A contact hole is formed in the second interlayer insulating film so as to reach the drain region, and a pixel electrode connected to the drain region is provided. The pixel electrode functions as a cathode of the EL element and is formed using a conductive film containing an element belonging to Group 1 or 2 of the periodic table. In this embodiment, a conductive film made of a compound of lithium and aluminum is used.

The insulating film provided to cover the edge of the pixel electrode is called a bank in this specification. The bank may be formed of an insulating film containing silicon or a resin film. When a resin film is used, the specific resistance of the resin film is 1 × 10 ⁶ to 1 × 1.
0 ¹² [Omega] m if (preferably ^{1 × 10 8 ~1 × 10 10} Ωm) adding carbon particles or metal particles such that, it is possible to suppress the dielectric breakdown at the time of film formation.

The EL element 1505 includes a pixel electrode (cathode), an EL layer, and an anode. As the anode, a conductive film having a large work function, typically, an oxide conductive film is used.
As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used.

In this specification, a laminate in which a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, or an electron blocking layer is combined with a light emitting layer is referred to as an EL layer. Define.

Although not shown here, it is effective to provide a passivation film so as to completely cover the EL element 1505 after forming the anode. As the passivation film, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a stacked layer in which the insulating films are combined.

Next, the steps up to the sealing (or enclosing) step for protecting the EL element were performed. The subsequent EL display device will be described with reference to FIG.

FIG. 14 is a top view showing a state in which the steps up to sealing of the EL element have been performed. 701 shown by a dotted line is a pixel portion, 702 is a source side drive circuit, and 703 is a gate side drive circuit. 704 is a cover material, 705 is a first seal material, and 706 is a second seal material.

Reference numeral 708 denotes wiring for transmitting signals input to the source-side drive circuit 702 and the gate-side drive circuit 703, and a video signal or a clock signal from an FPC (flexible print circuit) 708 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached.

Further, by forming the gate-side drive circuit and the source-side drive circuit only with the P-channel TFT, the pixel portion and the drive circuit can all be formed by the p-channel TFT. Accordingly, the yield and throughput of the TFT process can be greatly improved in manufacturing an active matrix type electro-optical device,
Manufacturing costs can be reduced.

This embodiment can also be implemented when either one of the source side drive circuit and the gate side drive circuit is an external IC chip.

In this embodiment, an example in which light is emitted upward is shown. However, a structure in which light is emitted downward may be adopted by appropriately changing the configuration of the EL element.

This embodiment can be freely combined with Embodiments 1 and 2. In this embodiment, an inverted staggered TFT is used. However, the present invention is not particularly limited, and a top gate TFT as shown in Embodiment 1 can be used.

[Embodiment 7] In this embodiment, an example of a circuit configuration of the EL display device shown in Embodiment 6 is shown in FIG. Note that this embodiment shows a circuit configuration for performing digital driving.
In this embodiment, the source side driving circuit 901 and the pixel portion 906
And a gate-side drive circuit 907. In this specification, a drive circuit is a generic term including a source-side processing circuit and a gate-side drive circuit.

The source side driving circuit 901 includes a shift register 902, a latch (A) 903, a latch (B) 904,
A buffer 905 is provided. In the case of analog driving, a sampling circuit (transfer gate) may be provided instead of the latches (A) and (B). The gate driver circuit 907 includes a shift register 908 and a buffer 909.

Further, in this embodiment, the pixel portion 906 includes a plurality of pixels, and the plurality of pixels are provided with an EL element. At this time, the cathode of the EL element is a current control TFT.
It is preferable to be electrically connected to the drain.

Although not shown, a gate-side drive circuit may be further provided on the side opposite to the gate-side drive circuit 907 with the pixel portion 906 interposed therebetween. In this case, both have the same structure and share a gate line, and a structure is adopted in which, even if one of them is broken, a gate signal is sent from the remaining one to operate the pixel portion normally.

[Embodiment 8] A drive circuit and a pixel portion formed by implementing the present invention are used in various electro-optical devices (active matrix type liquid crystal display, active matrix type EL display, active matrix type EC display). Can be. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a head mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.), and the like. Is mentioned. Examples of these are shown in FIGS.

FIG. 16A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 16B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other driver circuits.

FIG. 16C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other driving circuits.

FIG. 16D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302 and other driving circuits.

FIG. 16E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 16F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 17A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904 and other driving circuits.

FIG. 17B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other driving circuits.

FIG. 17C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

[0157]

According to the present invention, the resistance of the source and drain regions can be reduced by heat treatment (for several minutes) at a low temperature (300 ° C., preferably 250 ° C. or less). Even when the TFT is used as a formation substrate, a TFT having a sufficiently low sheet resistance can be manufactured. Therefore, it is also possible to form a TFT element on a flexible plastic film.

In addition, according to the present invention, an electro-optical device can be manufactured with a very small number of steps and at a low temperature in a short time. Therefore, the yield and the throughput are improved, and the manufacturing cost can be reduced.

Further, since an inexpensive electro-optical device can be manufactured, various electric appliances using the same for a display unit can be provided at an inexpensive price.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a TFT.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD. (Example 1)

FIG. 3 illustrates a manufacturing process of a TFT. (Example 2)

FIG. 4 is a diagram showing a manufacturing process of a TFT. (Example 3)

FIG. 5 is a diagram showing an appearance of an AM-LCD.

FIG. 6 is a diagram showing a circuit block diagram of an AM-LCD.

FIG. 7 is a graph showing an experimental result with a film thickness of 50 nm.

FIG. 8 is a graph showing an experimental result with a film thickness of 70 nm.

FIG. 9 is a graph showing an experimental result for a film thickness of 100 nm.

FIG. 10 is a diagram showing a Raman scattering spectrum.

FIG. 11 is a top view illustrating a pixel portion.

FIG. 12 is a cross-sectional view of a pixel portion.

FIG. 13 illustrates a structure of an active matrix EL display device.

FIG. 14 illustrates a top view of an EL display device.

FIG. 15 is a circuit block diagram of an EL display device.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates an example of an electronic device.

FIG. 18 is a diagram showing electric characteristics (VI characteristics) of a TFT.

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Claims (14)

[Claims] 1. An electro-optical device including a pixel portion and a driver circuit on the same insulating surface, wherein the pixel portion and the driver circuit are formed of a p-channel TFT, and a channel formation region of the p-channel TFT is mainly A semiconductor device having a crystalline structure, and wherein a source region or a drain region of the TFT mainly has an amorphous structure. 2. The electro-optical device according to claim 1, wherein the insulating surface is a surface of an insulating film provided on a plastic substrate. 3. The method according to claim 1, wherein said p
The semiconductor layer of the channel type TFT is formed by sputtering, PCVD
A semiconductor device formed by a method, an LPCVD method, a vacuum evaporation method, or a light CVD method. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a goggle type display, a car navigation system, a personal computer, or a portable information terminal. apparatus. 5. A step of forming a semiconductor layer having a crystal structure on an insulating surface, a step of forming an insulating layer on the semiconductor layer having the crystal structure, and a step of forming a conductive layer on the insulating layer. Forming an amorphous region by simultaneously adding a p-type impurity element and hydrogen to a part of the semiconductor layer having the crystal structure by an ion doping method, and performing a heat treatment on the amorphous region. Reducing the resistance value and making the amorphous region a source region or a drain region. 6. The semiconductor device according to claim 5, wherein the conductive layer is a gate electrode, and when the impurity element imparting p-type and hydrogen are added, the impurity element is added to an upper layer of the semiconductor layer using the conductive layer as a mask. A method for manufacturing a semiconductor device, comprising: 7. A step of forming a conductive layer on an insulating surface, a step of forming an insulating layer on the conductive layer, a step of forming a semiconductor layer having a crystal structure on the insulating layer, and an ion doping method. A part of the semiconductor layer having the crystal structure has p
A step of forming an amorphous region by adding an impurity element imparting a type and hydrogen, and performing a heat treatment to reduce the resistance value of the amorphous region, and forming the amorphous region into a source region or a drain region. A method for manufacturing a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 5, wherein the heat treatment is a heat treatment at 100 to 300 ° C. 9. The method for manufacturing a semiconductor device according to claim 5, wherein the heat treatment is a heat treatment at 100 to 300 ° C. in a hydrogen atmosphere. 10. The method according to claim 5, wherein
The method for manufacturing a semiconductor device, wherein the heat treatment is a hydrogen plasma treatment at 100 to 300 ° C. 11. The method according to claim 5, wherein
The method for manufacturing a semiconductor device, wherein the semiconductor layer having a crystal structure is crystallized after being formed by a sputtering method. 12. The method for manufacturing a semiconductor device according to claim 5, wherein the insulating surface is a surface of an insulating film provided on a plastic substrate. 13. A semiconductor device according to claim 5, wherein a manufacturing process temperature after the step of adding the p-type impurity element and hydrogen is 350 ° C. or lower. Method. 14. The amorphous region according to claim 5, wherein the amorphous region is not recrystallized in a manufacturing process after the step of adding the p-type impurity element and hydrogen. A method for manufacturing a semiconductor device.