JP2002140046A - Display device driving method, driving circuit thereof, display device, and electronic apparatus - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To simultaneously realize low crosstalk and high contrast. SOLUTION: A data signal Xi has one horizontal scanning period 1H.
The application period of the positive data voltage + VD / 2 is equal to the application period of the negative data voltage -VD / 2. Scan signal Yj
Takes either one of the positive non-selection voltage and the negative non-selection voltage in the non-selection period Tn, and outputs the positive reset voltage and the negative reset voltage in the reset period Tr.
Take a voltage having the same polarity as the polarity of the non-selection voltage selected in the non-selection period Tn. take.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a display device suitable for achieving both high contrast and low crosstalk when performing gradation display by pulse width gradation, a driving circuit thereof, a display device, and the like. And electronic devices.

[0002]

2. Description of the Related Art In a matrix type display panel, a switching element is provided for each of pixel electrodes arranged in a matrix and an element substrate provided with a plurality of data lines to which one ends of the switching elements are connected. And a counter substrate on which scanning lines and color filters are formed, and a liquid crystal filled between the two substrates.

In such a configuration, a thin film diode (TFD) is used as a switching element.
And the like using a two-terminal nonlinear element. FIG.
FIG. 2 is a circuit diagram showing a configuration of an image display area of a display panel using a TFD.

In the display panel shown in FIG. 1, when a voltage higher than the threshold voltage of the TFD 220 is supplied between the data line 212 and the scanning line 312, the TFD 220 is turned on and a predetermined charge is accumulated in the liquid crystal layer 118. You. After the charge is stored, a voltage lower than the threshold voltage is applied to
Even when D220 is turned off, if the resistance of the liquid crystal layer 118 is sufficiently high, the accumulation of charges in the liquid crystal layer 118 is maintained. Thus, each TFD 220 is driven,
When the amount of charge to be stored is controlled, the alignment state of the liquid crystal changes for each pixel, so that predetermined information can be displayed. At this time, it is only necessary to apply a signal voltage that is turned on to the liquid crystal layer 118 of each pixel to accumulate charges during a part of the period. Therefore, by selecting each scanning line 312 in a time-division manner, scanning can be performed. Multiplex driving in which the line 312 and the data line 212 are shared by a plurality of pixels is possible.

A reset driving method is known as one method of multiplex driving. This drive system
In the latter half of one horizontal scanning period 1H, a selection voltage is supplied to the scanning line, while a reset voltage having a polarity opposite to that of the selection voltage is supplied to the scanning line in the first half period. FIG. 15 is a timing chart showing driving waveforms of the reset driving method.
As shown in FIG. 1A, in the conventional reset driving method, one horizontal scanning period is composed of a reset period Tr and a main selection period T.
s, and the signal level of the scanning signal Yj is determined so that a voltage of the opposite polarity is obtained in each period. For example, the scanning signal Yj
Is + during the main selection period Ts of the n-th frame.
On the other hand, during the reset period Tr, the polarity becomes -Vs of the opposite polarity.
Is applied.

Here, assuming that the display panel operates in the normally white mode, the data signal Xi is as shown in FIGS. Also, the data signal X
With reference to i, the drive waveforms Yj-Xi applied to the liquid crystal layer 118 and the TFD 220 are as shown in FIGS. Comparing the driving waveforms Yj-Xi for displaying white and displaying black, it can be seen that they are different. First, when displaying white, the reset period T
At r, a relatively large voltage is applied to the liquid crystal layer 118 and TFD2.
20, a relatively small voltage is applied to the liquid crystal layer 118 and the TFD 220 during the selection period Ts. The on-resistance of the TFD 220 during the selection period Ts is larger than that when displaying black, so that when displaying white, the liquid crystal layer is charged with a relatively large time constant. However, since the display panel operates in the normally white mode, it is sufficient to charge the liquid crystal layer with a small voltage, so that there is no problem even if the charging time constant is large.

Next, when displaying black, a relatively small voltage is applied to the liquid crystal layer 118 and the TF during the reset period Tr.
On the other hand, a relatively large voltage is applied to the liquid crystal layer 118 and the TFD 220 during the selection period Ts. For this reason, the on-resistance of the TFD 220 during the selection period Ts is smaller than that when displaying black, so that when displaying black, the liquid crystal layer 118 is charged with a relatively small time constant. Therefore, during the selection period Ts, the liquid crystal layer 18 can be charged with a high voltage. As a result, in the reset driving method, high contrast can be realized, and a sharp image can be displayed.

[0008]

However, in this driving method, for example, as shown in FIG. 16, a zebra display consisting of a black and white display of every other scanning line is displayed in a partial area A of the display screen 100a. If so, there is a known problem that so-called crosstalk occurs in the Y direction with respect to the area A.

The reason will be briefly described below. That is, when the zebra display is performed in the region A, the switching period of the voltage ± VD / 2 in the data signal to the data line in the region A coincides with the inversion period of the scanning signal. Is ± VD / during the period when the scanning line for the region A is selected.
2 is fixed to one of them. This is called area A
When viewed from the pixels in the region adjacent in the Y direction, it means that the data voltage in a part of the holding period is fixed to one. On the other hand, the selection voltages on adjacent scanning lines have opposite polarities as described above. Therefore, in a region adjacent to the region A in the Y direction, the effective voltage value applied during a part of the holding period is significantly different between pixels located in even-numbered rows and pixels located in odd-numbered rows. As a result, in a region adjacent to the region A in the Y direction, a density difference occurs between the pixels in the odd-numbered rows and the pixels in the even-numbered rows, and the above-described crosstalk occurs. In other words, the conventional driving method has a problem that high contrast and low crosstalk cannot be achieved at the same time.

The present invention has been made in view of such circumstances, and a purpose thereof is to provide a method of driving a display device which achieves both high contrast and low crosstalk, a driving circuit thereof, a display device, and It is to provide an electronic device.

[0011]

In order to achieve the above object, a display device driving method according to the present invention comprises a plurality of scanning lines extending in a row direction and a plurality of data lines extending in a column direction. The pixels provided corresponding to the respective intersections are displayed in a gray scale. Each of the data lines has one of a positive data voltage and a negative data voltage as a data voltage, and one horizontal scan is performed. The application period of the positive-side data voltage and the application period of the negative-side data voltage in the period are equal, and the timing of polarity inversion of the data voltage is determined and supplied in accordance with the gray level to be displayed, and the plurality of scans are performed. Each of the lines is 1
While sequentially selecting each horizontal scanning period, the one horizontal scanning period is divided into a non-selection period, a reset period, and a main selection period, and the scanning line selected in the non-selection period is provided with the positive data voltage and On the basis of the center voltage of the negative side data voltage, one of a positive side non-selection voltage and a negative side non-selection voltage is supplied, and in the reset period following the non-selection period, the center is applied to the scanning line. On the basis of the voltage, of the positive reset voltage and the negative reset voltage, a voltage having the same polarity as the polarity of the non-selection voltage selected in the non-selection period is supplied, and the voltage is applied in the main selection period following the reset period. A voltage having a polarity opposite to the polarity selected in the reset period, out of the positive-side selection voltage and the negative-side selection voltage, is supplied to the scanning line based on the center voltage.

According to the present invention, the data signal is supplied to the data line such that the application period of the positive data voltage is equal to the application period of the negative data voltage in each horizontal scanning period. The signal will not include frequency components below the horizontal scanning frequency. Therefore, crosstalk generated due to fluctuation of the effective voltage of the data line due to the low frequency component of the data signal can be eliminated in principle. Furthermore, since the polarity of the voltage supplied to the scanning line is inverted between the reset period and the main selection period, if the display device operates in the normally white mode, the white display is performed during the main selection period. Thus, while a relatively small voltage is applied, a relatively large voltage can be applied when displaying black. As a result, when displaying black, a large voltage can be charged to the electro-optical material (for example, liquid crystal), the transmittance is sufficiently reduced, and a high contrast can be realized. Therefore, according to this driving method, low crosstalk and high contrast can be simultaneously realized.

Here, it is preferable to supply adjacent scanning lines with voltages whose polarities are inverted with respect to the center voltage. This makes it possible to further reduce crosstalk. Further, the non-selection period is preferably a half period of the one horizontal scanning period,
Further, both the reset period and the main selection period may be １ ／ of the one horizontal scanning period.

Next, the drive circuit according to the present invention displays a pixel provided corresponding to each intersection of a plurality of scanning lines extending in the row direction and a plurality of data lines extending in the column direction with gradation display. The data line is provided with one of a positive data voltage and a negative data voltage as a data voltage, and a positive data voltage application period in one horizontal scanning period and the negative data voltage are applied to each data line. And a data line driving circuit for supplying the data voltage by inverting the timing of the polarity of the data voltage in accordance with the gray level to be displayed. And the horizontal scanning period is divided into a non-selection period, a reset period, and a main selection period, and the positive data voltage and the negative data voltage are applied to the scanning lines selected in the non-selection period. With voltage On the basis of the cardiac voltage, one of the positive-side non-selection voltage and the negative-side non-selection voltage is supplied, and in the reset period following the non-selection period, the scan line is connected to the center voltage with respect to the positive side. Of the reset voltage and the negative reset voltage, a voltage having the same polarity as the polarity of the non-selection voltage selected in the non-selection period is supplied, and the central voltage is applied to the scanning line in the main selection period following the reset period. And a scanning line driving circuit for supplying a voltage having a polarity opposite to the polarity selected in the reset period among the positive side selection voltage and the negative side selection voltage with reference to the following.

According to the present invention, the data line driving circuit comprises:
Since the data signal is supplied to the data line such that the application period of the positive data voltage and the application period of the negative data voltage in each horizontal scanning period are equal, the effective voltage of the data line is reduced by the low frequency component of the data signal. In principle, the crosstalk caused by the fluctuation of can be eliminated. Further, the scanning line driving circuit inverts the polarity of the voltage supplied to the scanning lines during the reset period and the main selection period. Therefore, if the display device operates in the normally white mode, the white line is displayed when white is displayed. While a relatively small voltage is applied during the selection period, a relatively large voltage can be applied when displaying black. As a result, when displaying black, a large voltage can be charged to the electro-optical material (for example, liquid crystal), the transmittance is sufficiently reduced, and a high contrast can be realized. Therefore, according to this drive circuit, low crosstalk and high contrast can be simultaneously realized.

Next, in the display device of the present invention, a first substrate having a plurality of data lines formed thereon is opposed to the first substrate at a predetermined distance, and a second substrate having a plurality of scanning lines formed thereon. A substrate, an electro-optic material sandwiched between the first substrate and the second, a pixel provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines, and And a drive circuit. According to this display device, low crosstalk and high contrast can be realized simultaneously.

Here, it is preferable that the pixel includes a switching element and a capacitance element made of the electro-optical material, and the capacitance element is driven by the switching element. According to this configuration, the selected pixel and the non-selected pixel are electrically separated by the switching element, so that the contrast, the response, and the like are good, and a high-definition display is possible.

In addition, the switching element is a thin film diode element having a conductor / insulator / conductor structure, one of which is connected to either the scanning line or the data line, and the other is And a configuration connected to the capacitance element. The use of the thin film diode element as the switching element is advantageous in that the manufacturing process is simplified and that a short circuit between the scanning line and the data line does not occur in principle.

Next, in order to achieve the above object, the electronic apparatus of the present invention is provided with the above display device, so that low crosstalk and high contrast can be simultaneously realized as described above.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. <Electrical Configuration> First, the electrical configuration of the display device according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing an electrical configuration of the display device. In the figure, on the liquid crystal panel 100, 320 data lines (segment electrodes) 212 are formed extending in the column (Y) direction, while 240 scanning lines (common electrodes) 312 are formed in rows (X). Data line 2
A pixel 116 is formed at each intersection between the scanning line 12 and the scanning line 312. Further, each pixel 116 is provided with the liquid crystal layer 11.
8 and a TFD (Thin Fil
m Diode (thin film diode) 220 in series. In this embodiment, for convenience of explanation, the total number of the scanning lines 312 is set to 240 and the total number of the data lines 212 is set to 320, and the matrix type display device of 240 rows × 320 columns will be described. It is not intended to limit the invention.

The Y driver 350 is generally called a scanning line driving circuit, and scan signals Y1, Y2,.
40 to the corresponding scan line 312,
More specifically, the scanning lines 312 are sequentially selected one by one (every one horizontal scanning period). Then, the selected one horizontal scanning period is divided into a non-selection period Tn, a reset period Tr, and a main selection period Ts. The non-selection voltage is applied to the non-selection period Tn, the reset voltage is applied to the reset period Tr, and the main selection period is set. In the period Ts, a selection voltage is applied.

The X driver 250 is generally called a data line driving circuit, and supplies data signals X 1, X 2, X 2, X 2, X 3, X 2, X 3,. ......, X320
Are supplied via the corresponding data lines 212.

On the other hand, the control circuit 400
It supplies various control signals and clock signals to be described later to the 0 and Y drivers 350 to control both. The drive voltage forming circuit 500 generates a voltage ± VD / 2 used also as a data voltage in the data signal and a non-selection voltage of the scanning signal, and a voltage ± VS used as a selection voltage of the scanning signal. is there. In the present embodiment, the polarity of the voltage applied to the scanning line 312 or the data line 212 is
2, the high potential side is defined as positive, and the low potential side is defined as negative with reference to the intermediate potential of the data voltage ± VD / 2 applied to the reference voltage.

<Mechanical Configuration> Next, the mechanical configuration of the display device according to the present embodiment will be described. FIG. 2 is a perspective view showing the overall configuration of the display device. As shown in this figure, in the liquid crystal panel 100, the element substrate 2
00 and the opposing substrate 300 are attached to each other. Then, on the terminal portion protruding from the opposing substrate 300 on the opposing surface of the element substrate 200, a bare chip X
The driver 250 is mounted by COG (Chip On Glass) technology, and one end of an FPC (Flexible Printed Circuit) substrate 260 for supplying various signals to the X driver 250 is connected. Similarly, a bare chip Y driver 350 is mounted on a terminal portion protruding from the element substrate 200 on the opposing surface of the opposing substrate 300 by COG technology, and an FPC board 360 for supplying various signals to the Y driver 350. One end is connected.
The control circuit 400 and the drive voltage forming circuit 500 (see FIG. 1) are connected to the other ends of the FPC boards 260 and 360, respectively.

Here, the mounting in the X driver 250 and the Y driver 350 is, first, at a predetermined position with the substrate, a film-like anisotropic conductive material in which conductive fine particles are uniformly dispersed in an adhesive. Second, sandwich the membrane,
This is performed by pressing and heating a driver, which is a bare chip, onto the substrate. Connection of the FPC boards 260 and 360 is performed in the same manner. Instead of mounting the X driver 250 and the Y driver 350 on the element substrate 200 and the counter substrate 300, respectively, for example, TAB (Tape Aut)
Using an omated bonding technique, a TCP (Tape Carrier Package) on which a driver is mounted may be electrically and mechanically connected by an anisotropic conductive film provided at a predetermined position on a substrate.

<Detailed Configuration of Liquid Crystal Panel> Next, the detailed configuration of the pixel 116 in the liquid crystal panel 100 will be described. FIG. 3 is a partially broken perspective view showing the structure. As shown in this figure, on the opposing surface of the element substrate 200,
Pixel electrodes 234 made of a transparent conductor such as ITO (Indium Tin Oxide) are arranged in a matrix in the X direction and the Y direction. Of these, 240 pixel electrodes 234 arranged in the same column are arranged in the Y direction. Each of the extending data lines 212 is connected via a TFD 220. Here, when viewed from the substrate side, the TFD 220 is formed of tantalum alone or a tantalum alloy, and the data line 2
12 and a first conductor 222 branched from the first conductor 222.
And a second conductor 226 made of chromium or the like, and adopts a conductor / insulator / conductor sandwich structure. Therefore, the TFD 220 has a diode switching characteristic in which the current-voltage characteristic is non-linear in both positive and negative directions.

The insulator 201 is formed on the upper surface of the element substrate 200 and has transparency and insulation. The reason why the insulator 201 is formed is to prevent the first conductor 222 from peeling off by heat treatment after the deposition of the second conductor 226, and to diffuse impurities into the first conductor 222. This is to prevent it. Therefore, when these do not cause a problem, the insulator 201 can be omitted. On the other hand, scanning lines 312 made of ITO or the like extend in a row direction orthogonal to the data lines 212 and are arranged at positions facing the pixel electrodes 234 on the opposing surface of the counter substrate 300. Therefore,
The scanning line 312 functions as a counter electrode of the pixel electrode 234.

The element substrate 200 and the opposing substrate 300 are separated from each other by a sealant (not shown) applied along the periphery of the substrate and a spacer (not shown) appropriately dispersed. In this closed space, for example, a TN (Twisted Nematic) type liquid crystal 105 is sealed. Therefore, the liquid crystal layer 11 in FIG.
Numeral 8 is composed of the scanning line 312, the pixel electrode 234, and the liquid crystal 105 located between the data line 212 and the scanning line 312 at the intersection.

In addition, the opposite substrate 300 is provided with color filters arranged in, for example, a stripe, a mosaic, a triangle, or the like according to the use of the liquid crystal panel 100, and the other regions are shielded from light. Therefore, a black matrix is provided. In addition, an alignment film or the like that has been rubbed in a predetermined direction is provided on each of the opposing surfaces of the element substrate 200 and the opposing substrate 300.
A polarizer or the like corresponding to the orientation direction is provided on the back surface of each substrate (all are not shown).

<Control Circuit> First, various control signals such as a control signal and a clock signal generated by the control circuit 400 in FIG. 1 will be described. First, the start pulse Y
D is a pulse output at the beginning of one vertical scanning period (one frame), as shown in FIG. Second, the clock signal YCLK is a reference signal on the scanning line side.
As shown in FIG. 2, the period has a period of 1H corresponding to one horizontal scanning period.

Third, the AC drive signal MY is a signal for AC driving the pixel 116 on the scanning line side. As shown in FIG. 5, two horizontal scanning periods 2H constitute one cycle and are the same. In the horizontal scanning period in which the scanning line is selected, the signal level is inverted every vertical scanning period. The timing at which the signal level of the AC drive signal MY is inverted occurs when 3 / 4H has elapsed from the start of the horizontal scanning period. Therefore, the AC drive signal M
By Y, driving is performed in which the polarity of the selection voltage is inverted every horizontal scanning period 1H, and the polarity is inverted every vertical scanning period.

Fourth, the control signal INH is a signal for selecting the latter half of one horizontal scanning period 1H, and becomes H-active during the latter half as shown in FIG.
Fifth, the latch pulse LP is for latching a data signal on the data line side, and is output at the beginning of one horizontal scanning period 1H as shown in FIG. Sixth, the reset signal RES is, as shown in FIG.
These pulses are output at the data line side at the beginning of the first half of one horizontal scanning period and at the beginning of the second half of the period. Seventh, the AC drive signal MX is a signal for AC driving the pixel 116 on the data line side, and as shown in FIG. 7, from the latter half of one horizontal scanning period 1H to the next horizontal scanning period 1H. Maintain the same level until the first half,
Thereafter, the signal is a signal whose level is inverted. Note that the AC drive signal MX in the first half of the horizontal scanning period 1H and the AC drive signal MY in the second half of the horizontal scanning period 1H are at an inverted level.

Eighth, the gradation code pulse GCP is a pulse for gradation control. As shown in FIG. 7, as shown in FIG. 7, one horizontal scanning period 1H is divided from the end points of the first half period and the second half period to the near side. The pulse is arranged at a position of a period corresponding to the level of the intermediate gradation. Here, in the present embodiment, it is assumed that gradation data indicating a pixel density is represented by 3 bits and 8 gradations are displayed, and (000) of the gradation data indicates white (off). On the other hand, (11
Assuming that 1) indicates black (on), the grayscale code pulse GCP is generated in each of the first half period and the second half period.
The pulses corresponding to the six pulses (001) to (110) excluding white and black are arranged corresponding to the intermediate gradation levels. More specifically, (00)
1), (010), (011), (100), (10
1) and (110) correspond to “1”, “2”, “3”, “4”, “5” and “6” of the gradation code pulse GCP in FIG. 7, respectively.

In FIG. 7, the gradation code pulse G
The CPs are arranged at equal pitches for convenience of description, but actually, the applied voltage-density characteristics (V-
In many cases, the pitch differs according to the (I characteristic).

<Scanning Line Driving Circuit> Next, details of the scanning line driving circuit 350 will be described. FIG. 4 is a block diagram showing a configuration of the scanning line driving circuit 350. In this figure, a shift register 3502 is a 240-bit shift register corresponding to the total number of scanning lines 312, and converts a start pulse YD supplied at the beginning of one frame into a clock signal YCLK having a cycle of one horizontal scanning period 1H. Therefore, the signals are shifted and the transfer signals YS1, YS2,.
The output is sequentially and exclusively performed as S240. Here, the transfer signals YS1, YS2,..., YS240 specify the scanning line 312 to be selected in one-to-one correspondence with each scanning line 312.

Subsequently, a voltage selection signal forming circuit 3504
Outputs a voltage selection signal that determines a voltage to be applied to each scanning line 312 from the AC drive signal MY and the control signal INH. Here, in the present embodiment, the voltage of the scanning signal applied to the scanning line 312 is + VS (positive selection voltage / positive reset voltage) and + VD / 2 as described above.
(Positive-side non-selection voltage), -VS (negative-side non-selection voltage), -VD
/ 2 (negative side selection voltage / negative side reset voltage). In this example, the positive selection voltage and the positive reset voltage are set to +
VS, and the positive selection voltage and positive reset voltage are -VS
However, it goes without saying that different voltages may be used.

The period during which the positive-side reset voltage + VS or the negative-side reset voltage -VS is actually applied is a period from the start of one horizontal scanning period to the passage of ＨH to the passage of ／ H. The period during which the positive-side selection voltage + VS or the negative-side selection voltage -VS is actually applied is a period from the elapse of 3 / 4H from the start of one horizontal scanning period to the end of one horizontal scanning period. The selection voltage is + VS after the negative reset voltage -VS is applied, and is -VS after the positive reset voltage + VS is applied. That is, the polarity of the selection voltage is uniquely determined so as to be the reverse polarity of the immediately preceding reset voltage.

Next, the non-selection voltage is + VD / 2 after the selection voltage + VS is applied, and is -VD / 2 after the selection voltage -VS is applied. It is fixed.

Therefore, the voltage selection signal forming circuit 3504
.., And Y240 so that the voltage levels of the scanning signals Y1, Y2,.
Is generated. That is, the transfer signals YS1, YS2,.
, YS240 attains an H level, and when the corresponding scanning line 312 is selected, the voltage selection signal forming circuit 3504 first controls the voltage level of the scanning signal to the scanning line 312. During the period when the signal INH is at the H level (the latter half of one horizontal scanning period, 1 / 2H), the selection voltage is set to a selection voltage corresponding to the AC drive signal MY. Second, after the control signal INH transitions to the L level, The voltage selection signal forming circuit 3504 is set to a corresponding non-selection voltage.
Generates a voltage selection signal.

More specifically, voltage selection signal forming circuit 350
4 outputs a voltage selection signal for selecting + VS when the AC drive signal MY is at the H level during the period when the control signal INH is at the H active level, and − when the AC drive signal MY is at the L level. A voltage selection signal for selecting VS is output during the period. Here, the signal level of the AC drive signal MY is inverted when a ３H period has elapsed from the start of one horizontal scanning period.
The polarity of the reset voltage and the polarity of the selection voltage are always opposite polarities.

Then, a voltage selection signal forming circuit 3504
If a voltage selection signal for selecting the positive side selection voltage + VS is output, then the positive side non-selection voltage + VD / 2
If a voltage selection signal for selecting the negative side selection voltage −VS is output while outputting a voltage selection signal for selecting the negative side non-selection voltage −VD / 2, Will be done. The generation of such a voltage selection signal is performed by a voltage selection signal forming circuit 3504.
Is executed for each of the 240 scanning lines 312.

Next, the level shifter 3506 expands the voltage amplitude of the voltage selection signal output by the voltage selection signal forming circuit 3504. And selector 3
508 selects a voltage indicated by the voltage selection signal whose voltage amplitude has been enlarged and selects the corresponding scanning line 3
12 is applied to each of them.

<Voltage Waveform of Scanning Signal> Next, the voltage waveform of the scanning signal supplied by the scanning line driving circuit 350 having the above configuration will be described with reference to FIG. As shown in this figure, when the start pulse YD is supplied at the beginning of one vertical scanning period (one frame), this start pulse YD
Are sequentially shifted by the clock signal YCLK for each horizontal scanning period 1H, and this is transferred to the transfer signals YS1, YS2,
.., And YS240 are sequentially and exclusively output.

First, when a certain scanning line is selected for one horizontal scanning period 1H by a certain transfer signal, in the non-selection period Ts, the positive non-selection voltage + VD / 2 and the negative side are selected according to the signal level of the AC drive signal MY. One of the non-selection voltages -VD / 2 is selected and supplied to the scanning line.

Next, the latter half period of one horizontal scanning period 1H is selected by the control signal INH, and the polarity of the reset voltage and the selection voltage is determined according to the signal level of the AC drive signal MY in the latter half period. For this reason, the voltage of the scanning signal supplied to the scanning line is set in the reset period T.
In r, for example, if the AC drive signal MY is at the L level, the voltage becomes the negative reset voltage -VS. Thereafter, when the AC drive signal MY goes to the H level at the start of the main selection period Ts, the voltage becomes the positive side selection voltage + VS, and when the main selection period Ts ends, the positive side non-selection voltage + VD /
Hold 2. In the latter half period 1 / 2H of one horizontal scanning period after one frame has elapsed, the AC drive signal MY
Is inverted, the voltage of the scanning signal supplied to the scanning line becomes the positive reset voltage + VS, then the negative selection voltage -VS, and then the negative selection voltage corresponding to the selection voltage. The non-selection voltage -VD / 2 is maintained.

For example, as shown in FIG.
The scanning signal Y of the scanning line selected first in the frame
The voltage of 1 becomes the negative non-selection voltage -VD / 2 in the non-selection period Tn of the horizontal scanning period, becomes the negative reset voltage -VS in the reset period Tr, becomes the positive selection voltage + VS in the main selection period Ts, Then, the non-selection voltage + VD /
Hold 2. Then, in the next (n + 1) th frame, the non-selection period Tn of the first horizontal scanning period becomes the positive non-selection voltage + VD / 2, the reset period Tr becomes the positive reset voltage + VS, and the positive selection voltage Ts in the main selection period Ts. Then, the cycle is repeated to maintain the positive side non-selection voltage + VD / 2 corresponding to the selection voltage.

On the other hand, since the level of the AC drive signal MY is inverted every 1 H during one horizontal scanning period, the voltage of the scanning signal supplied to the adjacent scanning line is alternately inverted every 1 H during each horizontal scanning period. Relationship. For example, as shown in FIG. 5, the voltage of the scanning signal Y1 to the scanning line selected first in a certain n-th frame changes to the negative non-selection voltage −VD / 2 in the non-selection period Tn of the horizontal scanning period. When the reset voltage Tr becomes the negative reset voltage −VS during the reset period Tr and becomes the positive select voltage + VS during the main selection period Ts, the voltage of the scanning signal Y2 to the second selected scanning line becomes the voltage of the horizontal scanning period. In the non-selection period Tn, the voltage becomes the positive non-selection voltage + VD / 2, in the reset period Tr, it becomes the positive reset voltage + VS, and in the main selection period Ts, it becomes the negative selection voltage -VS.

As described above, the voltage of the scanning signal according to the present embodiment becomes a non-selection voltage in the non-selection period Tn of the horizontal scanning period, and then takes a reset voltage having the same polarity as the non-selection voltage in the reset period Tr. Then, during the main selection period Ts, a selection voltage having a polarity opposite to that of the reset voltage is taken.

<Data Line Driving Circuit> Next, details of the data line driving circuit 250 will be described. FIG. 6 is a block diagram showing a configuration of the data line driving circuit 250. In this figure, an address control circuit 2502 generates a row address Rad used for reading gradation data, resets the row address Rad by a start pulse YD supplied at the beginning of one frame, and resets the row address Rad. The configuration is such that a step is made by a latch pulse LP supplied every horizontal scanning period.

The display data RAM 2504 has 240 rows ×
This is a dual-port RAM having an area corresponding to 320 columns of pixels. On the writing side, the gradation data Dn supplied from a processing circuit (not shown) is written to an arbitrary address according to a writing address Wad, while on the reading side, , The gradation data D at the address specified by the row address Rad
The configuration is such that 320 pieces of data for one row of n are collectively read.

Next, the PWM decoder 2506 is for performing pulse width modulation on the data signal in accordance with the gradation, and outputs a voltage selection signal for selecting the voltage of the data signals X1 to X320 in accordance with the display data. It is generated for each data line 212 from the AC drive signal MX, the reset signal RES, and the gradation code pulse GCP. Here, in the present embodiment, the voltage of the data signal applied to the data line 212 is
The two values are + VD / 2 (positive data voltage) and -VD / 2 (negative data voltage). In this embodiment, the display data is 3 bits (8 gradations).

[0052] PWM decoder 2506 generates a voltage selection signal such that the voltage level of the data signal has the following relationship. That is, the voltage level of the data signal is
First, the reset signal RES supplied at the beginning of one horizontal scanning period causes the level of the AC drive signal MX to be opposite to the level of the AC drive signal MX. Second, at the rise of the gradation code pulse GCP corresponding to the display data, The PWM signal is inverted so that it is inverted to the same level as the AC drive signal MX.
Decoder 2506 generates a voltage selection signal. FIG. 7 shows a binary representation of the display data signal input to the PWM decoder 2506 and a voltage selection signal resulting from decoding the display data signal. However, the PWM decoder 2506 is
If the display data is (000), the display data is set to (11) so that it is at an inverted level with respect to the AC drive signal MX.
In the case of 1), the PWM decoder 2506 generates a voltage selection signal so as to be at the same level as the AC drive signal MX. Now, the selector 2508 is connected to the PWM decoder 25.
06, is actually selected and supplied to each of the corresponding data lines 212.

<Voltage Waveform of Data Signal> Next, the voltage waveform of the data signal supplied by the data line driving circuit 250 having the above configuration will be described with reference to FIG. As shown in this figure, when the grayscale data is other than (000) or (111), the voltage level of the data signal Xi is the falling level of the grayscale code pulse GCP corresponding to the grayscale data. Inverts to the same level as the AC drive signal MX. However, the voltage level of the data signal Xi is an inversion level of the AC drive signal MX if the grayscale data is (000), while the grayscale data is (11).
If it is 1), it will be at the same level as the AC drive signal MX.

For this reason, in the period 1H corresponding to one horizontal scanning period, the positive data voltage +
The period during which VD / 2 is applied and the period during which the negative data voltage -VD / 2 is applied are equal to each other regardless of the grayscale data.

Next, FIG. 8 is a timing chart of a data signal and a scanning signal for examining crosstalk. As shown in this figure, when the gradation to be displayed is “white”, “slightly white”, “slightly black”, and “black”, the data signal Xi has the positive data voltage + VD / 2 and the period during which the negative data voltage is -VD / 2 are equal to each other. That is, the signal level is inverted at least once in each horizontal scanning period. Therefore, no matter what gradation is displayed, the data signal X
The signal level of i does not become either the positive data voltage + VD / 2 or the negative data voltage -VD / 2.

Further, when the gradation to be displayed is inverted every line such as "white, black, white ...", the signal level of the data signal Xi is inverted every 1 / 2H. In addition, no matter how the gradations to be displayed on each line are combined, at least the signal level of the data signal Xi is inverted at least once in one horizontal scanning period. Therefore, according to the present embodiment, the effective voltage applied to a certain data line does not change and crosstalk does not occur, and the quality of a display image can be improved.

FIG. 9 is a timing chart showing signal waveforms for examining contrast. Assuming that the scanning signal Yj shown in FIG. 11A is supplied to the scanning line and the data signal Xi (white) shown in FIG. 10B is supplied to the data line, the j-th scanning line and the i-th scanning line are provided. In the pixel corresponding to the intersection of the data lines, the liquid crystal layer 118 and the TF
The driving voltage Yj-Xi shown in FIG. On the other hand, the data signal Xi (black) shown in FIG.
Is supplied to the data line, at the pixel corresponding to the intersection of the j-th scanning line and the i-th data line,
A drive voltage Yj-Xi shown in FIG. 9E is applied to the liquid crystal layer 118 and the TFD 220. When these drive waveforms are compared, during the reset period Tr, the pixel becomes -VS-VD / 2 when displaying white on the pixel, and becomes -VS + VD / 2 when displaying black. In addition, the main selection period Ts
, When displaying white on the pixel, VS−VD
/ 2, and when displaying black, + VS + VD / 2
Becomes That is, the driving waveforms Yj-Xi are different between when displaying white and when displaying black.

First, when displaying white, a relatively large voltage is applied to the liquid crystal layer 118 and the TF during the reset period Tr.
On the other hand, a relatively small voltage is applied to the liquid crystal layer 118 and the TFD 220 during the selection period Ts. Since the ON resistance of the TFD 220 during the selection period Ts is larger than that when displaying black, the liquid crystal layer 118 is charged with a relatively large time constant when displaying white. However, since the display panel operates in the normally white mode, it is sufficient to charge the liquid crystal layer 118 with a small voltage, so that there is no problem even if the charging time constant is large.

Next, when displaying black, a relatively small voltage is applied to the liquid crystal layer 118 and the TF during the reset period Tr.
On the other hand, a relatively large voltage is applied to the liquid crystal layer 118 and the TFD 220 during the selection period Ts. For this reason, the on-resistance of the TFD 220 during the selection period Ts is smaller than that when displaying black, so that when displaying black, the liquid crystal layer 118 is charged with a relatively small time constant. Therefore, during the selection period Ts, the liquid crystal layer 118 can be charged with a high voltage.

FIG. 10 is a graph showing VT characteristics (liquid crystal transmittance characteristics with respect to driving voltage) and contrast characteristics in the driving method of the present embodiment. In this figure, the curve connecting the black triangles indicates the VT characteristic when displaying white, and the curve connecting the black circles indicates the VT characteristic when displaying black.
It shows the T characteristic. Further, a curve connecting the black squares indicates a contrast characteristic. Due to the difference between the drive waveforms Yj-Xi described above, the VT characteristic differs between the case where white is displayed and the case where black is displayed as shown in this figure, and high contrast can be obtained. . As described above, according to the driving method of the present embodiment, low crosstalk and high contrast can be satisfied at the same time, and the quality of a displayed image can be greatly improved.

<Application> In the above-described embodiment, the reset period Tr and the main selection period Ts have been described as 1 / 4H. However, this is merely an example, and the reset period Tr is not limited.
May be set shorter than １ ／ H, and the main selection period Ts may be lengthened accordingly.

In FIG. 1, the TFD 220 is connected to the data line 212 and the liquid crystal layer 118 is connected to the scanning line 31.
2 but on the contrary, the TFD 22
0 is on the scanning line 312 side, and the liquid crystal layer 118 is on the data line 21 side.
Alternatively, a configuration may be employed in which each of them is connected to the second side.

The TFD 220 in the above-described liquid crystal panel 100 is an example of a switching element. In addition, the TFD 220 includes a ZnO (zinc oxide) varistor and an MSI (Metal Sequential).
A two-terminal element such as an element using a mi-Insulator) or a series connection or parallel connection of two of these elements in the opposite direction is applicable.
ransistor (thin film transistor) or a three-terminal element such as an insulated gate field effect transistor.

Here, when a TFT is applied as a switching element, for example, a silicon thin film may be formed on the surface of the element substrate 200, and a source, a drain, and a channel may be formed on the thin film. In the case where an insulated gate field effect transistor is used as a switching element, for example, the element substrate 200 may be a semiconductor substrate and a source, a drain, and a channel may be formed on the surface of the semiconductor substrate. Therefore, the pixel electrode 234 is formed of a reflective electrode made of a metal such as aluminum and used as a reflective type.

When a three-terminal element is used as the switching element, the data lines 21
2 and the scanning line 312, not only one but also the intersection of both, so that the possibility of wiring short-circuiting increases accordingly.
Since the configuration is more complicated than D, it is disadvantageous in that the manufacturing process is complicated.

Further, the present invention can be applied to a passive liquid crystal using an STN (Super Twisted Nematic) liquid crystal without using a switching element such as a TFD or a TFT. Further, the pixel electrode 234 is made of a reflective metal,
Alternatively, a reflective layer may be separately formed below the pixel electrode 234 and used as a reflective type. Further, the reflective layer may be formed to be extremely thin and used as a transflective type.

Further, in the above description, a display device using liquid crystal as an electro-optical material has been described as an example. However, a display device that performs display by an electro-optical effect, such as electroluminescence, a fluorescent display tube, and a plasma display, is used. Applicable to the device. That is, the present invention is applicable to all display devices having a configuration similar to the above-described display device.

<Electronic Equipment> Next, some examples in which the above-described liquid crystal device is used in specific electronic equipment will be described. <Part 1: Mobile Computer> Next, an example in which the above-described display device is applied to a display unit of a mobile personal computer will be described. FIG. 11 is a perspective view showing the configuration of the personal computer. In the figure, a computer 2200 includes a main body 2204 having a keyboard 2202 and a liquid crystal panel 100 used as a display. This liquid crystal panel 1
Although a backlight is provided on the back of 00 to enhance visibility, it is not shown because it does not appear in appearance.

<Part 2: Mobile Phone> An example in which the above-described display device is applied to a display unit of a mobile phone will be described. FIG. 12 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 2300 includes the above-described liquid crystal panel 100 together with a plurality of operation buttons 2302, an earpiece 2304, and a mouthpiece 2306. Note that a backlight for improving visibility is also provided on the back surface of the liquid crystal panel 100, but is not shown in the appearance, and is not shown.

<Part 3: Digital Still Camera> Next, a digital still camera using the above-described display device as a finder will be described. FIG. 13 is a perspective view showing the configuration of the digital still camera, but also simply shows the connection with an external device.

In a conventional camera, a film is exposed by an optical image of a subject, while a digital still camera 2 is used.
Reference numeral 400 denotes a CCD (Charge Coupled Dev)
In this case, an image pickup signal is generated by photoelectric conversion by an image pickup device such as ice). Here, the digital still camera 2
The liquid crystal panel 100 described above is provided on the back surface of the case 2402 in the 400, and is configured to perform display based on an image pickup signal by a CCD. Therefore, the liquid crystal panel 100 functions as a finder for displaying the subject. In addition, a light receiving unit 2404 including an optical lens, a CCD, and the like is provided on the front side (the rear side in FIG. 13) of the case 2402.

Here, when the photographer confirms the subject image displayed on the liquid crystal panel 100 and presses the shutter button 2406, the CCD image pickup signal at that time is transferred and stored in the memory of the circuit board 2408. . In this digital still camera 2400, a video signal output terminal 2412 and an input / output terminal 2414 for data communication are provided on the side surface of the case 2402.
As shown in the figure, a television monitor 2420 is connected to the video signal output terminal 2412, and a personal computer 2430 is connected to the input / output terminal 2414 for data communication, as necessary. . Further, by a predetermined operation, the imaging signal stored in the memory of the circuit board 2408 is transmitted to the television monitor 2420.
And output to a personal computer 2430.

As the electronic equipment, in addition to the personal computer shown in FIG. 11, the portable telephone shown in FIG. 12, and the digital still camera shown in FIG. 13, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, Car navigation system, pager, electronic organizer, calculator, word processor, workstation, videophone, P
An OS terminal, a device including a touch panel, and the like can be given. Needless to say, the above-described display device can be applied as a display unit of these various electronic devices.

[0074]

As described above, according to the present invention, 1
Since the data signal is inverted at least once during the horizontal scanning period and a reset period is provided before the main selection period,
Low crosstalk and high contrast can be realized simultaneously.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration of a liquid crystal panel in the display device.

FIG. 3 is a partially cutaway perspective view schematically showing a configuration of a main part of the liquid crystal panel.

FIG. 4 is a block diagram showing a configuration of a Y driver in the display device.

FIG. 5 is a timing chart for explaining the operation of the Y driver.

FIG. 6 is a block diagram showing a configuration of an X driver in the display device.

FIG. 7 is a timing chart for explaining the operation of the X driver.

FIG. 8 is a timing chart showing driving waveforms for explaining crosstalk in the display device.

FIG. 9 is a timing chart showing driving waveforms for explaining contrast in the display device.

FIG. 10 is a graph for explaining VT characteristics and contrast characteristics in the display device.

FIG. 11 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the display device is applied.

FIG. 12 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the display device is applied.

FIG. 13 is a perspective view showing a configuration of a digital still camera as an example of an electronic apparatus to which the display device is applied.

FIG. 14 is a circuit diagram showing a configuration of an image display area of a display panel using a TFD.

FIG. 15 is a timing chart showing a driving waveform of a conventional reset driving method.

FIG. 16 is a plan view showing a display screen when zebra display is performed using a conventional reset driving method.

[Explanation of symbols]

 100 Liquid crystal panel 105 Liquid crystal 116 Pixel 118 Liquid crystal layer 200 Element substrate 212 Data line 220 TFD 234 Pixel electrode 250 X driver (data line drive circuit) 300 … Opposed substrate 312… scan line 350… Y driver (scan line drive circuit) 2200… personal computer 2300… mobile phone 2400… digital still camera

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621B 623 623 623C 641 641A F term (Reference) 2H093 NA32 NA43 NB21 NC10 NC12 NC22 NC34 NC35 NC38 ND04 ND06 ND15 ND35 NE06 NF05 NF13 5C006 AC02 AC24 AC26 AF42 AF44 AF71 BB17 BC03 BC07 BC13 BF02 BF24 EC09 EC13 FA36 FA54 5C080 AA10 BB05 DD10 DD30 EE29 FF09 JJ01 JJ02 JJ04 KK20 KK02 KK02 KK02 KK02 KK06

Claims (9)

[Claims] 1. A method for driving a display device, in which pixels provided corresponding to intersections of a plurality of scanning lines extending in a row direction and a plurality of data lines extending in a column direction are displayed in a gray scale. In each of the data lines, one of a positive data voltage and a negative data voltage is used as a data voltage, and a positive data voltage application period and a negative data voltage application period in one horizontal scanning period are set. The timing of polarity inversion of the data voltage is determined and supplied in accordance with the gray level to be displayed, and each of the plurality of scanning lines is sequentially selected for each horizontal scanning period. The scanning period is divided into a non-selection period, a reset period, and a main selection period, and a scanning line selected in the non-selection period, with reference to a center voltage of the positive data voltage and the negative data voltage, Positive side not selected And supplying either one of a negative reset voltage and a negative non-selection voltage to the scan line in the reset period following the non-selection period. Supplying a voltage having the same polarity as the polarity of the non-selection voltage selected in the non-selection period, and applying a positive-side selection voltage and a negative voltage to the scan line in the main selection period following the reset period with respect to the center voltage. A method for driving a display device, comprising: supplying a voltage having a polarity opposite to a polarity selected in the reset period among side selection voltages. 2. The method of driving a display device according to claim 1, wherein voltages whose polarities are inverted with respect to the center voltage are supplied to adjacent scanning lines. 3. The method according to claim 1, wherein the non-selection period is a half period of the one horizontal scanning period. 4. The reset period and the main selection period,
4. The method according to claim 3, wherein both of the periods are １ ／ of the one horizontal scanning period. 5. 5. A drive circuit of a display device for displaying a gradation of a pixel provided at each intersection of a plurality of scanning lines extending in a row direction and a plurality of data lines extending in a column direction. In each of the data lines, one of a positive data voltage and a negative data voltage is used as a data voltage, and a positive data voltage application period and a negative data voltage application period in one horizontal scanning period are set. A data line driving circuit that determines the polarity inversion timing of the data voltage in accordance with a gray level to be displayed, and selects and sequentially selects each of the plurality of scanning lines for each horizontal scanning period , The one horizontal scanning period is a non-selection period,
The scan line selected in the non-selection period is divided into a reset period and a main selection period, and a positive non-selection voltage and a negative One of the non-selection voltages is supplied, and in the reset period following the non-selection period, the non-selection of the positive reset voltage and the negative reset voltage with respect to the center voltage with respect to the center voltage. A voltage having the same polarity as the polarity of the non-selection voltage selected in the period is supplied, and in the main selection period following the reset period, the scan line is supplied with the positive side selection voltage and the negative side selection voltage based on the center voltage. And a scanning line driving circuit for supplying a voltage having a polarity opposite to the polarity selected in the reset period. 6. A first substrate on which a plurality of data lines are formed, a second substrate on which a plurality of scan lines are formed, facing the first substrate at a constant distance, and a first substrate on which a plurality of scanning lines are formed. 6. The drive of the display device according to claim 5, wherein: an electro-optical material sandwiched between the plurality of data lines; and pixels provided corresponding to intersections of the plurality of scan lines and the plurality of data lines. A display device provided with a circuit. 7. The display according to claim 6, wherein the pixel includes a switching element and a capacitance element made of the electro-optical material, and the capacitance element is driven by the switching element. apparatus. 8. The switching element is a thin-film diode element having a conductor / insulator / conductor structure, one of which is connected to one of the scanning line or the data line, and the other is: The display device according to claim 7, wherein the display device is connected to the capacitance element. 9. An electronic apparatus comprising the display device according to claim 6. Description: