JP2002034235A - Charge pump circuit and its controlling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that, in a charge pump circuit that raises a voltage in a small step of a power source voltage Vdd or smaller, forward bias is applied to a parasitic diode and that the circuit malfunctions. SOLUTION: This charge pump circuit is provided with at least first and second charge transferring MOS transistors M1, M2 connected in series, a clock driver 3 that supplies a clock to first and second capacitors 1, 2 and the one end of the second capacitor 2, a first switching means S2 for connecting the first and second capacitors 1, 2 in series to a pumping node, and second switching means S1, S3 for connecting the capacitors 1, 2 parallel to the node. Then, the clock driver 3 changes the clock state when both of the first and second switching means are turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for outputting a boosted voltage in steps equal to or lower than a power supply voltage Vdd and a control method thereof, and more particularly, to a normal charge pump by removing the influence of a parasitic diode associated with a charge transfer element. The present invention relates to a control method of a charge pump circuit that enables an operation.

[0002]

2. Description of the Related Art A charge-pump circuit developed by Dicson connects a plurality of pumping packets in series and boosts the voltage of each pumping packet.
on), a voltage higher than the power supply voltage Vdd of the LSI chip is generated. For example, program / eras (program / eras) of flash memory
e) is used to generate the voltage for.

[0005] However, the conventional charge pump circuit boosts the voltage in steps of the power supply voltage Vdd, and there has not been proposed any charge pump circuit capable of raising the voltage in a smaller voltage step. The present inventor has already proposed a charge pump circuit capable of increasing the voltage step smaller than Vdd and improving the circuit efficiency η (Japanese Patent Application No. 11-348475).

[0004] The outline is as follows. 10 to 12 are circuit diagrams showing the configuration and operation of the -0.5 Vdd step-up charge pump circuit. This charge pump circuit is -0.5 with respect to the ground voltage (0 V).
This is for creating a boosted voltage of Vdd.

In FIG. 10, diodes D1 and D2 are connected in series as charge transfer elements. The ground voltage (0 V) is supplied to the cathode of the diode D1. The diodes D1 and D2 are generally constituted by charge transfer MOS transistors for integration in an LSI.

The switches S1, S2 and S3 connect the two capacitors 1 and 2 to the connection point of the diodes D1 and D2 by switching them in parallel or in series. These switches S
1, S2 and S3 can be constituted by MOS transistors. Thereby, the switches S1, S2, S
ON / OFF of 3 corresponds to ON / OFF of the MOS transistor. The clock driver 3 supplies a clock CLK to the capacitor 2. The output voltage output from the diode D2 is applied to the load 4.

Hereinafter, an outline of a control method of the charge pump circuit will be described. Now, the power supply voltage Vdd of the clock driver 3 is 5V. Also, a diode D1,
By providing D2 and switches S1, S2, S3,
Actually, a voltage drop (Voltage Drop) occurs in that portion, but here, this is ignored and the voltage drop is set to 0V.

When S1 = OFF, S2 = ON, and S3 = OFF when the input clock of the clock driver 3 is at a high level (CLK = High), the two capacitors 1 and 2 are connected in series, and each node voltage is , VL1 ≒
0V, VA = VB = 2.5V, and VC = 5V. VL
1 is the voltage at the connection node (pumping node) between the diode D1 and the capacitor 1, VA is the voltage at the connection node between the capacitor C1 and the switch S2, VB is the voltage at the connection node between the switch 2 and the capacitor 2, and VC is the clock driver 3. And the voltage at the connection node of the capacitor 2.

That is, assuming that the capacitance values of the capacitors 1 and 2 are equal, the charge is equally distributed to the capacitors 1 and 2 so that the capacitors 1 and 2 respectively have Vd
It is charged to a voltage of d / 2. (See FIG. 10) Next, when S2 = OFF and S1 = S3 = ON from the state in which CLK == High, the two capacitors 1, 2
Switches to parallel connection. Thereby, each node voltage becomes VL1Ｌ2.5V, VA = 5V, VB = 2.5V,
VC = 5V. Next, when the input clock CLK is transited to the low level (CLK = Low) from the parallel connection state, the capacitors 1 and 2 are coupled to the pumping node. , Each node voltage is VL1 ≒ −2.5V, VA = 0V, VB = −2.5V
V and VC = 5V. (Refer to FIG. 12) As described above, by repeatedly switching the capacitors 1 and 2 alternately in series and parallel according to the input clock CLK, the output voltage of -2.5 V (= -1 / 2 Vdd) is output from the diode D2. Is supplied to the load 4.

[0010]

SUMMARY OF THE INVENTION Diodes D1, D2
For pseudo charge transfer with source and gate connected
When constituted by S transistors, the pumping node V
When the voltage of L1 becomes 2.5V, the diode D1
However, there is a problem that unnecessary current flows transiently due to forward bias. Therefore, to avoid this problem, the gate voltage of the charge transfer MOS transistor may be controlled separately from the source voltage.

At the timing when the capacitors 1 and 2 are connected in series, the gate voltage of the charge transfer MOS transistor corresponding to the diode D1 is set to low level to turn on (see FIG. 10), and the capacitors 1 and 2 are turned on. At the timing when 2 are connected in parallel, the gate voltage of this charge transfer MOS transistor is set to a high level to control it to turn off (FIG. 11).
reference).

However, in the above-described method of controlling the charge pump circuit, the voltage VL1 at the pumping node is 0
The change is repeated from V → 2.5V → −2.5V. For this reason, the MOS transistor for charge transfer is a P-channel type,
In any case of the N-channel type, there is a problem that the parasitic diode formed accompanying the MOS transistor is biased in the forward direction, and the boosting operation is not performed normally.

FIG. 13 shows a diode D as a charge transfer element.
FIG. 4 is a diagram showing a problem in a case where 1 is made of a P-channel MOS transistor. In this case, the back gate bias effect (Back Gate Bias Effect) of the MOS transistor
In order to improve the efficiency of the charge pump circuit, the source S and the substrate B are grounded.

As shown in FIG. 13A, there is no problem when the voltage VL1 of the pumping node is -2.5V. However, as shown in FIG.
In the case of 5V, if the parasitic diode formed between the drain and the substrate is forward biased, a forward current of the diode flows between the drain and the substrate, the power efficiency is deteriorated, and the charge pump operation is normal. Will not be performed.

FIG. 14 is a diagram showing a problem when the diode D1 is formed by an N-channel MOS transistor as a charge transfer element. In this case, to suppress the back gate bias effect of the MOS transistor,
The structure is such that the drain D (pumping node) and the substrate B are connected.

As shown in FIG. 14A, there is no problem when the voltage VL1 at the pumping node is -2.5V.
However, when the voltage VL1 is 2.5 V as shown in FIG. 14B, a parasitic diode formed between the substrate and the source is biased in the forward direction. Then
A forward current of the diode flows between the substrate and the source, so that the power efficiency deteriorates and the charge pump operation is not performed normally.

An object of the present invention is to prevent a parasitic diode from being forward-biased and an unnecessary current from flowing in a charge pump circuit for boosting a voltage step smaller than Vdd, thereby enabling the charge pump circuit to operate normally. It is to be.

[0018]

A charge pump circuit according to the present invention comprises at least a first and a second MOS transistor for charge transfer connected in series, a first and a second capacitor, and a second capacitor. Clock supply means for supplying a clock to one end; first switch means for connecting the first and second capacitors in series to a connection point of the first and second charge transfer MOS transistors; The first and second capacitors are connected to the first and second charge transfer M
Second connection for connecting in parallel to the connection point of the OS transistor
Wherein the clock supply means changes the state of the clock when the first and second switch means are turned off.

According to this configuration, the timing at which the clock supplied to the capacitor changes from the low level to the high level (or from the high level to the low level) is adjusted so that both the first and second switch means are turned off. are doing. In this state, the first and second capacitors are disconnected from the connection point (pumping node) between the first and second charge transfer MOS transistors.

As a result, the change in the potential of the pumping node is suppressed, so that the first and second charge transfer
The parasitic diode associated with the S transistor is prevented from being forward biased.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 show -0.5.
FIG. 3 is a circuit diagram illustrating a configuration and an operation of a charge pump circuit that outputs a boosted voltage of Vdd. This charge pump circuit generates a boosted voltage of -0.5 Vdd with respect to the ground voltage (0 V).

P-channel MOS as a charge transfer element
The transistors M1 and M2 are connected in series. MO
The S transistors M1 and M2 have a configuration in which a substrate and a source are connected to prevent a back gate bias effect. Although there is no particular limitation on the MOS transistors M1 and M2, for example, a gate and a source are connected to form a kind of diode.

The switches S1, S2 and S3 are connected to the connection points (pumping nodes) of the MOS transistors M1 and M2.
The two capacitors 1 and 2 are switched and connected in parallel or in series. That is, when the switch S2 (first switch means) is turned on, the MOS transistors M1 and M2 are connected in series, and when the switch (S1, S3) (second switch means) is turned on, the MOS transistors M1 and M2 are connected in parallel. Is done.

As will be described later, the switch S2 and the switches (S1, S3) are generally controlled to alternately turn on and off. These switches S
1, S2 and S3 can also be constituted by MOS transistors. Thereby, the switches S1, S2, S
ON / OFF of 3 corresponds to ON / OFF of the MOS transistor.

The clock driver 3 supplies a clock CLK to the capacitor 2. The clock driver 3 is not particularly limited, but may be a CMO supplied with the power supply voltage Vdd.
It consists of an S-type inverter. And the diode D
The output voltage output from 2 is applied to the load 4.

In the following, referring to FIGS. 1 to 7,
A control method of the charge pump circuit having the above configuration will be described. FIG. 7 is a timing chart for explaining a control method of the charge pump circuit.

Note that, although not particularly limited, the power supply voltage Vdd of the clock driver 3 is set to 5 V,
2 have the same capacitance value. Further, the description will be made on the assumption that the voltage drop caused by the MOS transistors M1 and M2 and the switches S1, S2 and S3 is also 0V.

(1) First control step At time t1, switches S1 and S3 are turned off, and switch S
1, S2 and S3 are all turned off. The input clock CLK of the clock driver 3 has a low level (CLK
= Low). In this state, each node voltage is VL1 ≒ −2.5V, VA = 0V, VB =
−2.5V and VC = 0V. VL1 is the voltage of the connection node (pumping node) between the MOS transistor M1 and the capacitor 1, and VA is the capacitor 1 and the switch S2.
The connection node is also a voltage, and VB is a switch 2 and a capacitor 2
Is the voltage of the connection node between the output of the clock driver 3 and the capacitor 2 (see FIGS. 1 and 7).

(2) Second Control Step Next, at time t2 when the switches S1, S2, and S3 are all in the OFF state, the clock CLK is changed from the low level to the high level. Then, VC changes to 5V, and VB changes to 2.5V due to the effect of the capacitor coupling. The voltage VL1 of the pumping node is connected to the switch S1,
Since both S2 and S3 are off, no change occurs (see FIGS. 2 and 7).

(3) Third Control Step Thereafter, a time t3 when the input clock of the clock driver 3 maintains the high level (CLK = High) state
Then, S2 is turned on. Thereby, the two capacitors 1 and 2 are connected in series to the pumping node.

As a result, the capacitors 1 and 2 are connected to Vdd
/ 2, and each node voltage is VL1 ≒ 0
V, VA = VB = 2.5V, and VC = 5V. That is, the average output current Iout flows through the MOS transistor M1, and Iout also flows from the output of the clock driver 3 (see FIGS. 3 and 7).

(4) Fourth Control Step Next, at time t4 when the clock CLK = High,
The switch S2 is turned off. As a result, the switches S1, S2, and S3 are turned off again. The voltage of each node is maintained as it is (see FIGS. 4 and 7).

(5) Fifth Control Step Next, at time t5 when all of the switches S1, S2, and S3 are off, the input clock CLK is changed to low level (CLK == Low). Then, due to the effect of the capacitor coupling, each node voltage becomes VL1 ≒ 0V, V
A = 2.5V, VB = -2.5V, and VC = 0V.
(See FIGS. 5 and 7).

(6) Sixth Control Step Next, at time t6 when the input clock CLK is maintained at the low level, S1 and S3 are turned on. Thereby, capacitors 1 and 2 are connected in parallel to the pumping node. Therefore, each node voltage is VL1 = −2.
5V, VA = 0V, VB = -2.5V, and VC = 0V (see FIGS. 6 and 7).

Thereafter, the process returns to the first control step, and the first to sixth control steps are repeated.

According to the control method described above, unlike the conventional example, the voltage VL1 at the pumping node is suppressed to 0 V at the maximum, so that the parasitic diode is forward-biased and an unnecessary current flows, so that the charge pump operation is normal. Is prevented from being performed.

FIG. 8 shows a P-channel MOS charge transfer element.
It is a figure showing the case where it is manufactured with a transistor. In this case, the source and the substrate are grounded in order to suppress the back gate bias effect, but the parasitic diode is not forward biased when the pumping node is 0 V or -2.5 V. There is no problem because there is not.

FIG. 9 is a diagram showing a problem in the case where the charge transfer element is made of an N-channel MOS transistor. In this case, the structure is such that the drain (pumping node) and the substrate are connected to suppress the back gate bias effect. In any case where the pumping node is 0 V or -2.5 V, there is no problem because the parasitic diode is not forward biased.

In summary, the charge pump circuit of the present invention firstly operates in a state where the switches S1, S2 and S3 are all turned off (the capacitors 1 and 2 are disconnected from the pumping node) and the clock driver 3 Is to change the clock CLK. Second, after the clock CLK is changed to the high level, the switch S
2 and turn on capacitors 1 and 2 in series with the pumping node. Third, the clock CL
After changing K to a low level, the switches (S1, S1
3) turn on and connect capacitors 1 and 2 in parallel to the pumping node. According to this rule, when the charge transfer element of the charge pump circuit is realized by a MOS transistor, it is possible to avoid a forward bias of a parasitic diode associated with the MOS transistor.

Although the charge transfer MOS transistors M1 and M2 are diode-connected in this embodiment, the threshold voltage (Th
(Reshold Voltage). The present invention
The charge transfer MOS transistor M is not limited to this.
1 and M2 are turned on and off alternately according to the clock CLK, and the charge transfer MOS transistors M1 and M2 are turned on and off.
When M2 is turned on, it can be applied to a charge pump circuit configured to supply a boosted voltage (for example, 2 Vdd in absolute value) to those gates.

In this case, M1 is turned on and M2 is turned off during the period when the capacitors 1 and 2 are connected in series, and M1 is turned off and M2 is turned on during the period when the capacitors 1 and 2 are connected in parallel. These gate voltages are controlled so that

As a result, the MOS transistors M1, M
2 and the on-resistance of the MOS transistors M1 and M2 is reduced, so that a charge pump circuit with high efficiency and large output current can be realized.

In this embodiment, the charge transfer MOS
The transistors M1 and M2 are configured by P-channel MOS transistors, but are not limited thereto, and may be configured by N-channel MOS transistors.

In this embodiment, an example in which the present invention is applied to a single-stage charge pump circuit that outputs a boosted voltage of -0.5 Vdd has been described. However, the present invention increases the number of charge pump stages by -1. The present invention can also be applied to a two-stage charge pump circuit that outputs a boosted voltage of 0.5 Vdd.
In general, the present invention can be applied to a multi-stage charge pump circuit incorporating the charge pump circuit of the present embodiment as a core.

In such a multi-stage charge pump circuit, for example, the first stage outputs a voltage of -0.5 Vdd,
In the second and higher stages, a general Dickson-type charge pump circuit is configured.

The charge pump circuit according to the present embodiment is of a type in which the two capacitors 1 and 2 are switched in series and parallel to perform a voltage step-up of a voltage step of -0.5 Vdd. By switching in parallel, it is possible to increase the voltage in smaller voltage steps. The present invention can be applied to such a charge pump circuit.

In this embodiment, the charge pump circuit for outputting a negative boosted voltage has been described.
The same can be applied to a charge pump circuit having a step of +0.5 Vdd.

[0048]

According to the charge pump circuit and the control method of the present invention, in the charge pump circuit which performs boosting at a step lower than the power supply voltage by repeatedly connecting the capacitor to the pumping node in series and in parallel, Since the forward bias of the parasitic diode is prevented, the charge pump operation can be performed normally, and the power efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a charge pump circuit and a control method thereof according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 7 is a timing chart showing a charge pump circuit and a control method thereof according to the embodiment of the present invention.

FIG. 8 is a diagram showing a case where the charge transfer element is made of a P-channel MOS transistor.

FIG. 9 is a diagram showing a case where the charge transfer element is made of an N-channel MOS transistor.

FIG. 10 is a circuit diagram showing the configuration and operation of a conventional charge pump circuit.

FIG. 11 is a circuit diagram showing the configuration and operation of a conventional charge pump circuit.

FIG. 12 is a circuit diagram showing the configuration and operation of a conventional charge pump circuit.

FIG. 13 is a diagram showing a problem in the case where the charge transfer element is made of a P-channel MOS transistor.

FIG. 14 is a diagram showing a problem in a case where the charge transfer element is formed by an N-channel MOS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Capacitor 2 Capacitor 3 Clock driver M1 Charge transfer MOS transistor M2 Charge transfer MOS transistor S1 First switch S2 Second switch S3 Third switch

Claims (15)

[Claims] A first charge transfer MOS transistor connected in series, first and second capacitors, clock supply means for supplying a clock to one end of the second capacitor, First switch means for connecting the first and second capacitors in series to the connection point of the first and second charge transfer MOS transistors;
A second switch unit for connecting the first and second capacitors in parallel to a connection point of the first and second charge transfer MOS transistors, the charge pump circuit comprising: Means for changing the state of the clock when the first and second switch means are turned off. 2. The first switch means turns on the clock after the clock changes from a first state to a second state, thereby causing the first and second capacitors to transfer the first and second charges. 2. The charge pump circuit according to claim 1, wherein the charge pump circuit is connected in series to a connection point of the MOS transistors. 3. The second switch means turns on after the clock changes from the second state to the first state, thereby causing the first and second capacitors to transfer the first and second charges. 3. The charge pump circuit according to claim 2, wherein the charge pump circuit is connected in parallel to a connection point of the MOS transistors for use. 4. The charge pump circuit according to claim 3, wherein said first and second charge transfer MOS transistors are P-channel MOS transistors. 5. The charge pump circuit according to claim 3, wherein said first and second charge transfer MOS transistors are N-channel MOS transistors. 6. At least first and second MOS transistors for charge transfer connected in series, a plurality of capacitors, clock supply means for supplying a clock to these plurality of capacitors, and a plurality of capacitors First switch means for connecting in series to a connection point of the first and second charge transfer MOS transistors, and the plurality of capacitors being connected in parallel to a connection point of the first and second charge transfer MOS transistors; Second switch means for:
A charge pump circuit comprising: the clock supply means for changing the state of the clock when the first and second switch means are turned off. 7. The first switch means turns on after the clock changes from the first state to the second state, thereby connecting the plurality of capacitors to the first and second charge transfer MOS transistors. 7. The charge pump circuit according to claim 6, wherein the charge pump circuit is connected in series to a point. 8. The second switch means turns on after the clock changes from the second state to the first state, thereby connecting the plurality of capacitors to the first and second charge transfer MOS transistors. The charge pump circuit according to claim 7, wherein the charge pump circuit is connected to the point in parallel. 9. A plurality of charge transfer MOs connected in series
A charge pump circuit comprising: an S transistor; a plurality of capacitors coupled to a connection point of the plurality of charge transfer MOS transistors; and clock supply means for supplying a clock to the plurality of capacitors. The capacitors are at least first and second
First switch means for connecting the first and second capacitors in series to the connection point of the charge transfer MOS transistor; and the first and second capacitors.
Second switching means for connecting the capacitor in parallel to the connection point of the charge transfer MOS transistor, and the clock supply means is configured to switch the clock signal when the first and second switching means are turned off. A charge pump circuit for changing a state of a clock. 10. The first switch means turns on the clock after the clock changes from the first state to the second state, thereby causing the first and second capacitors to transfer the first and second charges. 10. The charge pump circuit according to claim 9, wherein the charge pump circuit is connected in series to a connection point of the MOS transistors. 11. The second switch means turns on after the clock changes from the second state to the first state, thereby causing the first and second capacitors to transfer the first and second charges. 11. The charge pump circuit according to claim 10, wherein the charge pump circuit is connected in parallel to a connection point of the MOS transistor. 12. At least first and second charge transfer MOS transistors connected in series, and first and second charge transfer MOS transistors.
And a clock supply means for supplying a clock to one end of the second capacitor, and a series connection means for connecting the first and second capacitors in series to a connection point between the first and second charge transfer MOS transistors. A charge pump circuit comprising: first switch means; and second switch means for connecting the first and second capacitors in parallel to a connection point of the first and second charge transfer MOS transistors. The method of controlling a charge pump circuit, wherein the state of the clock is changed by the clock supply unit after the first and second switch units are turned off. 13. A first step of turning off the first and second switch means, a second step of changing the clock from a first state to a second state by the clock supply means, By turning on the first switch means,
And a third step of connecting the second capacitor in series, a fourth step of turning off the first switch means, and changing the clock from a second state to a first state by the clock supply means. A fifth step of turning on the second switch means,
And a sixth step of connecting a second capacitor in parallel, wherein the first to sixth steps are repeated, and the control method of the charge pump circuit according to claim 12, wherein 14. At least first and second MOS transistors for charge transfer connected in series, a plurality of capacitors, clock supply means for supplying a clock to the plurality of capacitors, and a plurality of capacitors First switch means for connecting in series to a connection point of the first and second charge transfer MOS transistors, and the plurality of capacitors being connected in parallel to a connection point of the first and second charge transfer MOS transistors; And a second switch means for controlling the charge pump circuit, wherein the clock supply means changes the state of the clock after the first and second switch means are turned off. A method for controlling a charge pump circuit, comprising: 15. A first step of turning off the first and second switch means, a second step of changing the clock from a first state to a second state by the clock supply means, A third step of connecting the plurality of capacitors in series by turning on a first switch, a fourth step of turning off the first switch, and a second step of turning off the clock by the clock supply. A fifth step of changing from the state to the first state; and a sixth step of connecting the plurality of capacitors in parallel by turning on the second switch means. 15. The method according to claim 14, wherein the sixth step is repeated.