JP2002033385A - Semiconductor device manufacturing method and semiconductor device evaluation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device and an evaluation method for a semiconductor device in which the adhesion between a metal wiring such as Cu and a Cu diffusion preventing film such as a SiN film and a SiC film formed by CVD is improved. I will provide a. SOLUTION: An insulating film 1 is formed on a semiconductor substrate, a wiring groove 7 is formed in the insulating film 1, a metal wiring 8 is buried in the wiring groove 7, and a surface treatment of the metal wiring 8 is performed to form a modified layer 5. A CVD film (SiN) 6 is formed on the insulating film 1 and the metal wiring 8.
Is formed, and the adhesion of the CVD film to the metal wiring is improved by the surface treatment. The surface treatment is performed using ion water, aqueous hydrogen peroxide, persulfuric acid, alkalis, or the like. By giving the reaction selectivity in the initial stage of CVD by this surface treatment, the adhesion between the Cu wiring and the CVD film can be improved without increasing the resistance or causing a leak between the wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a pretreatment for forming a CVD film formed on a metal wiring such as Cu.

[0002]

2. Description of the Related Art FIG. 16 is a flow chart for explaining a step of forming a metal wiring on a conventional semiconductor substrate, and FIG. 15 is a sectional view of the step. First, an insulating film 111 made of TEOS or the like is formed on a semiconductor substrate such as silicon. Next, a normal PEP (Photo Engra
ving Process) The wiring groove 117 is formed in the insulating film 111 by the processing.
Is formed by patterning (see FIG. 15A). Next, a metal film 112 such as Cu is deposited on the insulating film 111. The metal film 112 is also sufficiently filled inside the wiring groove 117 (see FIG. 15B). Next, the surface of the metal film 112 such as Cu is formed, for example, by CMP (Chemical Mesh).
A flattening process is performed by a canical polishing method. By this flattening process, the metal film 112 is filled only in the wiring groove 117 to form the metal wiring 113, and the metal film formed in the other part of the insulating film is removed (). next,
The semiconductor substrate is washed by an acid treatment to remove metal impurities attached to the surface and oxides 114 formed on the surface (see FIG. 15C). Next, the semiconductor substrate is subjected to normal plasma CVD (Chemical Vapor Deposition).
The substrate is placed in the apparatus and the surface of the substrate is modified by discharge or reduction annealing of NH ₃ plasma to form a modified layer 115 (FIG. 15D).
16 is a modified layer 1 covering the insulating film 111 and the metal wiring.
15 (see FIG. 15E).

[0003]

When Cu or a Cu alloy is used as a metal wiring, Cu has a strong tendency to diffuse in an insulating film. In a Cu wiring forming process, Cu or SiN, SiC, or a barrier metal such as a barrier metal is formed after a CMP process. It is necessary to cap the Cu wiring with a diffusion prevention film. But,
In particular, the SiN film has low adhesion to Cu, and the CVD approach, that is, forming a CVD SiN film using silicidation, ammonia plasma treatment, or the like, results in poor contact and increases resistance and leakage between wires. There was a problem that it easily occurred. The present invention has been made in view of such circumstances, and a metal wiring such as Cu and C
Provided are a method of manufacturing a semiconductor device and a method of evaluating a semiconductor device, which have improved adhesion to a Cu diffusion preventing film such as a SiN film or a SiC film formed by VD.

[0004]

According to the present invention, a surface treatment is performed on a Cu wiring or an insulating film on a semiconductor substrate after a CMP process or before a CVD process, and the reaction selectivity is improved in the initial stage of the CVD process. With this, the Cu wiring and the C
It is characterized in that the adhesion between VD films is improved.
That is, a method of manufacturing a semiconductor device according to the present invention includes the steps of: forming an insulating film on a semiconductor substrate; forming a wiring groove in the insulating film; embedding a metal wiring in the wiring groove; And a step of forming a CVD film on the insulating film and the metal wiring, wherein the adhesion of the CVD film to the metal wiring is improved by the surface treatment. I have. The metal wiring may be made of copper or a copper alloy. The CVD film may be a silicon nitride film.
The silicon nitride film may be used as a copper diffusion prevention film. The surface treatment may be mainly an oxidation reaction. Before or simultaneously with the surface treatment, the metal oxide on the surface of the metal wiring may be removed using an acid. Before or at the same time as the surface treatment, a slurry additive component such as an organic substance adhering to the surface of the metal wiring may be removed. The oxidizing agent used in the oxidation reaction is at least one of ionic water, aqueous hydrogen peroxide, persulfuric acid, and alkalis, and the acid is at least one of a chelating agent, sulfuric acid, halogen, and a halogen compound. Further, the slurry additive component removing method may be any one of a surfactant treatment, an alkali treatment, and a gas-dissolved water MHz treatment.

According to a semiconductor device evaluation method of the present invention, the surface condition of the metal wiring surface-treated by any one of the above-described semiconductor device manufacturing methods is determined by an electrochemical measurement by a cyclic voltammetry method in a 50 mM VCl solution in a 10 mM KCl solution. . -750 mVv from Ag / AgCl
s. When the potential is swept through the range up to Ag / AgCl at −2 mV / sec, the range is swept a plurality of times to −25 in the immediately preceding cycle in which the reduction current does not completely flow.
0 to -500 mV vs. When the peak current value observed in Ag / AgCl is from -500 to -750 mVvs. Ag / Ag
It is characterized in that it is evaluated that the current is higher than the peak current value observed with Cl. The surface condition of the metal wiring subjected to the surface treatment by the above-described method for manufacturing a semiconductor device of the present invention is -250 to -500 mVvs. A
The peak current value observed in g / AgCl (A region) is −
500 to -750 mVvs. Ag / AgCl (B region)
, And the surface state of the metal wiring obtained by the conventional method is −500 to −750 mVvs. In the previous cycle. Ag / Ag
The peak current value observed at Cl is -250 to -500 m
Vvs. It is higher than the peak current value observed for Ag / AgCl. That is, by performing the surface treatment of the present invention, it is possible to increase the resistance without causing an increase in resistance, leakage between wires, and the like.
Although the adhesion between the u wiring and the CVD film can be improved, the surface state can be easily observed by this electrochemical measurement. A region and B region are shown in FIG.
Is shown in

[0006]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 and FIG.
An example will be described. FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device for forming an embedded wiring, and FIG. 2 is a flowchart illustrating a process of forming a metal wiring on a semiconductor substrate. First, an insulating film (silicon oxide film) 1 made of TEOS (tetraethyloxysilane) or the like is formed on a semiconductor substrate (not shown) such as silicon. Next, a wiring groove 7 is patterned and formed in the insulating film 1 by a normal PEP process using a photoresist (not shown) (see FIG. 1A). Next, Cu, A
A metal film 2 such as g is deposited. The metal film 2 is sufficiently filled in the wiring groove 7 (see FIG. 1B). Next, the surface of the metal film 2 such as Cu
The flattening process is performed in the MP apparatus by the CMP method. The conditions of this CuCMP are 300 gf / cm ² , TR / TT
= 12/20, 2 minutes. TR represents the number of rotations of the table supporting the polishing cloth, and TR represents the number of rotations of the top ring supporting the wafer (that is, the number of rotations of the wafer).

By this flattening process, the metal film 2 of Cu or the like is filled only in the groove to form the metal wiring 8, and the metal film 2 formed on the other portion of the insulating film 1 is removed by etching. (See FIG. 1C). Then, for example,
The semiconductor substrate is washed by an acid treatment such as 1 wt% DHF (dilute hydrofluoric acid) to remove metal impurities adhering to the surface and oxides 4 such as CuO and Cu ₂ O formed on the surface and to remove the surface. In a wet state, anticorrosion treatment is performed with 0.05% BTA (benzotriazole) rinse, rinse drying is performed, and then the semiconductor substrate is taken out of the CMP apparatus (). Thereafter, a surface treatment such as an oxidation reaction, which is a feature of the present invention, is performed on the metal wiring and the insulating film. That is, in this embodiment, 0.1 wt% TMAH + anode ion water or 0.5 wt% KOH solution or the like is used for the surface treatment liquid, and the anticorrosive agent is removed and the surface is oxidized by the treatment with the anodic ion water. . Thereafter, a drying process is performed. Immediately after the completion of the drying process, the semiconductor substrate is immediately placed in a normal plasma CVD apparatus, and the NH ₃ plasma is discharged or reduced and annealed to modify the substrate surface by immediately placing the Cu modified layer 5. (Fig. 1
(D)). Subsequently, a silicon nitride film (SiN) 6 is deposited on the insulating film 1 and the Cu modified layer 5 covering the metal wiring 8 by plasma CVD (see FIG. 1E).

As described above, in this embodiment, after the CMP process or the CVD process, the Cu wiring or the insulating film on the semiconductor substrate is subjected to the anodic ion water treatment to perform the surface treatment, and the reaction selectivity in the initial stage of the CVD. , The adhesion between the Cu wiring and the CVD film is improved without causing an increase in resistance, leakage between wirings, and the like.

Next, a second embodiment will be described with reference to FIG. FIG. 10 is a flowchart illustrating a step of forming a metal wiring on a semiconductor substrate according to the present invention. First, an insulating film made of TEOS or the like is formed on a semiconductor substrate such as silicon. Next, using a photoresist to form a normal PE
A groove is patterned and formed in the insulating film by the P process (). Next, a metal film such as Cu or Ag is deposited on the insulating film. The metal film sufficiently fills the inside of the groove (). Next, the surface of a metal film such as Cu
The flattening process is performed by the CMP method in the P device. By this flattening process, a metal film such as Cu is filled only in the groove to form a metal wiring, and the metal film formed in other portions on the insulating film is removed (). Next, the semiconductor substrate is washed by an acid treatment to remove metal impurities adhering to the surface and oxides formed on the surface. Thereafter, the semiconductor substrate is taken out of the CMP apparatus.

Thereafter, a surface treatment such as an oxidation reaction, which is a feature of the present invention, is performed on the metal wiring and the insulating film. That is, in this embodiment, 5% hydrogen peroxide (H ₂ O ₂ ) water + 4.5
After rinsing with a wt% glycine aqueous solution for 1 minute, the chemical solution is removed by a pure water rinsing method (). After the drying process is completed, the semiconductor substrate is immediately placed in a normal plasma CVD apparatus without any time after the completion of the drying process, and the CH ₃ plasma is discharged or reduction-annealed to modify the substrate surface. A carbonized film (SiC) is deposited on the insulating film and the metal wiring (). As described above, in this embodiment, the surface treatment is performed by rinsing the Cu wiring and the insulating film on the semiconductor substrate with the 5% hydrogen peroxide solution + 4.5% glycine aqueous solution for 1 minute after the CMP process or before the CVD process. To increase the adhesion between the Cu wiring and the CVD film without causing an increase in resistance, leakage between wirings, etc. by giving a reaction selectivity in the initial stage of CVD.

Next, the operation of the present invention will be described with reference to FIGS. A source gas for forming a CVD film made of an insulating film such as SiN or SiC has a large amount of a reducing material, and a metal surface constituting a wiring embedded in the CVD film usually has an oxide film. The process is susceptible to this oxide reduction reaction. on the other hand,
Transition metals such as Cu include CuO, Cu ₂ O, Cu (O
H) It is known to have multiple oxidation states, such as ₂ . If these oxidizing species and thickness are controlled, the CVD film seems to be stable and good. However, this is not the case. DHF
Treatment, anode ionized water treatment, ESCA of water mark part (this part means discoloration that can be obtained by applying pure water to Cu and naturally drying) (FIG. 3), GIXR
(FIGS. 4 and 5) The surface condition is hardly changed by the analysis. FIG. 3 is a characteristic distribution diagram showing the state of Cu on the surface where the vertical axis represents the count number and the horizontal axis represents the binding energy (eV). From this figure, no particular difference is recognized in the type of film regardless of the surface treatment.

FIGS. 4 and 5 are characteristic diagrams for analyzing the thickness of the surface layer by light reflection. The vertical axis represents the reflectance, and the horizontal axis represents the irradiation angle. No matter what kind of surface treatment is performed, almost the same characteristics can only be obtained, and no particular difference is recognized in the film thickness. Such a surface layer has a thickness of 50 μm.
m, and Cu, CuO, Cu ₂ O, Cu (OH) _{2 and the} like are mixed. In such a surface state, CV
The adhesion between the Si film, which is a D film, and the Cu film is good (○) when treated with anodic ion water, but poor (悪) when treated with DHF, and worse (悪 い) at the watermark portion. State. In the treatment for forming CuO, the adhesion is not good when the ozone water treatment is performed (x), and the adhesion is good when the treatment with hydrogen peroxide + glycine is performed (o).
Thus, the adhesion between the two cannot be explained by the oxidized species of Cu or the film thickness.

The Cu film subjected to the surface treatment is shown in FIG.
10 mM KCl of pH 6 constituting the electrochemical cell shown in FIG.
50 → -750mVvs. Ag / AgC
When the reduction reaction observation is performed by electrochemical measurement by the cyclic voltammetry method in which the potential is swept at 1 and −2 mV / sec, the observation is made in a plurality of times in this range, and the observation is made in the cycle immediately before the reduction current completely stops flowing. From
The surface of the Cu film with good adhesion is -350 to -450 mV
vs. Ag / AgCl (A region), defective is -500
mVvs. Ag / AgCl to cathode region (-750
mVvs. (Ag / AgCl), a high peak current is observed (FIGS. 6 to 8). 6 to 8 show 10 m of pH6.
It shows the waveform of Cu reduction in the MKCl solution, the vertical axis represents current density (mA / cm ² ), and the horizontal axis represents potential (mVvs.
(Ag / AgCl). FIG. 6A shows Cu
6 (b) is immediately after the ozone water treatment on the Cu surface, FIG. 7 (a) is immediately after the anodic water treatment on the Cu surface, FIG. 7 (b) is after the KOH treatment on the Cu surface,
FIG. 8A shows that after the hydrogen peroxide solution on the Cu surface is treated for 5 minutes,
FIG. 8B shows the respective Cu reduction waveforms from the treatment of the hydrogen peroxide solution on the Cu surface to the treatment with glycine. FIG. 14 is a schematic diagram of an electrochemical cell. This electrochemical cell has a container filled with the 10 mM KCl solution having a pH of 6, in which a Cu electrode and a Pt electrode (counter electrode) are arranged, and a reference electrode (Ag / AgCl) is additionally provided.

These are the equilibrium potentials of Cu redox (CuO + 2H ⁺ + 2e ⁻
= 2Cu + H ₂ O: 0.588 V vs. NHE, Cu ₂
O + 2H ⁺ + 2e ⁻ = 2Cu + H ₂ O: 0.471 Vv
s. NHE), indicating that ESCA requires significantly different energy for reduction even in the same oxidation state. In other words, the energy required for this reduction greatly contributes to the adhesion.

FIG. 9 shows the results of the EELS measurement of the SiN / Cu interface for those having good and poor adhesion.
In both of the EELS waveforms, almost all waveforms peculiar to SiN are shown. In the case of a signal having good adhesion, a signal rises from around 101 eV, whereas the signal having a poor adhesion is denoted by
A signal rises from 104 eV. This is because those having good adhesion include a signal of metal Si. Therefore, those with good adhesion are SiN
/ Cu has a metal bond of Si-Cu in the interface layer, and Cu subjected to the surface treatment of the present invention can preferentially form this bond state in the initial reaction of CVD. In FIG. 9, the vertical axis indicates the number of counts by the photodiode × 10.
00, the horizontal axis represents energy loss (eV), and the state of metal bonding at the SiN / Cu interface. Further, the anode water treatment shown in the above-described embodiment,
Other than the oxidizing agent + chelating agent treatment, the present invention is applicable as long as the energy state required for reduction is controlled, for example, treatment with alkali such as KOH or treatment with hydrogen peroxide.

Next, a third embodiment, which is a method of forming a multilayer wiring to which the method of manufacturing a semiconductor device according to the present invention is applied, will be described with reference to FIGS. 11 to 13
FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device. In this example,
The description of the element isolation forming step and the transistor forming step is omitted, and only the two-layer wiring of the multilayer wiring structure will be described. In this embodiment, a multilayer wiring having an embedded Cu wiring by a damascene process will be described. FIG.
As shown in (a), a semiconductor substrate 201 such as silicon
A first interlayer insulating film 202 made of CVD SiO ₂ or the like is formed thereon. An element isolation region and a transistor such as a MOSFET are formed in a surface region of the semiconductor substrate 201 (not shown). Next, a first metal wiring is formed. For this purpose, first, an etching stopper film 203 made of a silicon nitride film or the like for etching a wiring groove is formed on the semiconductor substrate 201 by the first interlayer insulating film 20.
2 is formed.

Then, a second interlayer insulating film 204 having a low relative dielectric constant is deposited on the etching stopper film 203 as an insulating film between wirings. Several materials and forming methods can be considered for the second interlayer insulating film. For example,
There is a silicon oxide film to which fluorine (F) or boron (B) is added by a low-pressure plasma CVD method, and a silicate film or a polymer film by a spin coating method. Silicate-based films include those containing an organic component and those containing no organic component. As another film formation method, there is an organic film formed by a vapor deposition polymerization method. Here, a low dielectric constant film is mainly described, but a silicon oxide film such as a TEOS film can also be used. In this embodiment, a fluorine-added silicon oxide film formed by a low pressure plasma CVD method is used. next,
A photoresist film 205 is formed on the second interlayer insulating film 204 of the semiconductor substrate 201. This photoresist film 2
05 is patterned into a first wiring pattern shape (FIG. 11A). Next, using the patterned photoresist film 205 as a mask, RIE (Reactive Ion
A wiring groove 217 into which the first wiring is buried is formed using an etching stopper 203 by using an etching method (FIG. 11B).

Next, a metal film serving as a first wiring material is formed in the wiring groove 217, the semiconductor substrate 201, and the second interlayer insulating film 2.
04. As this deposition method, for example,
A titanium nitride film (TiN) which is a Cu diffusion prevention film
A Cu film having a thickness of about 100 nm is deposited by a sputtering method, and then a Cu film having a thickness of about 100 nm is deposited. Further, a Cu film is formed on the sputtered Cu film by an electroplating method.
Deposit about nm. As described above, the metal film is composed of the titanium nitride film, the sputtering Cu film, and the electroplated Cu film. Next, the Cu film forming the metal film is flattened by a CMP method or the like, and the Cu film is left only in the wiring groove 217. The metal film in the wiring groove 217 forms the first wiring 206. After that, a diffusion prevention film 207 for Cu is deposited on the entire surface of the second interlayer insulating film 204 including the first wiring 206. As the diffusion preventing film 207, a thin silicon nitride film (S
iN) (FIG. 11C). In order to deposit the diffusion prevention film 207 for Cu on the entire surface of the second interlayer insulating film 204 including the surface of the first wiring 206, the surface treatment of the present invention is performed as a pretreatment, for example, the surface shown in the first embodiment. Perform processing.

Next, the diffusion preventing film 2 is formed on the semiconductor substrate 201.
For example, a third interlayer insulating film 208 made of a fluorine-added silicon oxide film is deposited by low-pressure plasma CVD so as to cover layer 07. A photoresist film 209 is formed on third interlayer insulating film 208, and this photoresist film 209 is patterned so as to form a connection hole. Then, the first wiring 20 is formed on the third interlayer insulating film 208 by lithography and dry etching such as RIE.
6 is formed (FIG. 12).
(A)). Next, after removing the photoresist film 209, a metal film serving as a first connection wiring is deposited on the semiconductor substrate 201. As this deposition method, for example, a titanium nitride film (TiN) of a high melting point metal is deposited to a thickness of 300 nm by a sputtering method, and then tungsten (W) is deposited.
A film is deposited on the entire surface of the TiN film. Thus, the metal film is
It is composed of a TiN film and a W film. Next, the W film forming the metal film is planarized by a CMP method or the like, and the metal film is left only in the first connection hole 218.
The metal film in the first connection hole 218 forms a first connection wiring 210 electrically connected to the first wiring 206.

Next, a stopper film 211 serving as an etching stopper at the time of processing the second wiring groove is deposited on the entire surface of the third interlayer insulating film 208 including the first connection wiring 210. As the stopper film 211, a thin silicon nitride film (SiN) formed by a plasma CVD method that also has a Cu diffusion preventing effect is used (FIG. 12B). Cu
In order to deposit an anti-diffusion film 211 over the entire surface of the third interlayer insulating film 208, the surface treatment of the present invention, for example, the surface treatment shown in the first embodiment is performed as a pretreatment. Next, a fourth interlayer insulating film 212 made of a fluorine-added silicon oxide film is deposited on the semiconductor substrate 201 by, for example, a low-pressure plasma CVD method so as to cover the stopper film 211. Then, a photoresist film 213 is formed on the fourth interlayer insulating film 212. This photoresist film 213 is patterned so as to form a wiring groove. Then, a second wiring groove 219 reaching the first connection wiring 210 is formed in the fourth interlayer insulating film 212 by lithography and dry etching such as RIE.
(C)).

Next, after removing the photoresist film 213,
A metal film serving as a second wiring is deposited on the semiconductor substrate 201. As this deposition method, for example, a titanium nitride film (TiN), which is a Cu diffusion prevention film, is deposited to a thickness of 10 nm by a sputtering method, and then a film thickness of about 100 n
An m-th Cu film is deposited. Further, a Cu film is deposited to a thickness of about 800 nm on the sputtering Cu film by electroplating. As described above, the metal film is composed of the TiN film, the sputtering Cu film, and the electroplated Cu film. Next, the Cu film forming the metal film is planarized by a CMP method or the like, and the Cu film is left only in the second wiring groove 219. The metal film in the second wiring groove 219 constitutes a second wiring 214 electrically connected to the first connection wiring 210. After that, a diffusion preventing film 215 for preventing diffusion of Cu into the insulating film is deposited on the entire surface of the fourth interlayer insulating film 212 including the second wiring 214. This diffusion prevention film 2
A thin silicon nitride film (SiN) or the like formed by a plasma CVD method is used as the reference numeral 15 (FIG. 13A).

In order to deposit a diffusion preventing film 215 for Cu on the entire surface of the fourth interlayer insulating film 212, a surface treatment of the present invention, for example, the surface treatment shown in the first embodiment is performed as a pretreatment. Next, for example, low-pressure plasma CVD so as to cover the semiconductor substrate 201 with the diffusion prevention film 215.
A fifth interlayer insulating film 216 made of a fluorine-added silicon oxide film is deposited by the method (FIG. 13B). By repeating the above method, the third, fourth,... Multi-layer wirings having low wiring resistance are sequentially formed with good adhesion.

[0023]

According to the present invention, the metal wiring such as Cu and the C which covers the metal wiring are formed by performing a surface treatment before forming the insulating film on the semiconductor substrate on which the metal wiring such as Cu is formed.
Adhesion with an insulating film formed by VD is improved, an increase in wiring resistance of the metal wiring is suppressed, and a short circuit is suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device for forming an embedded wiring according to the present invention.

FIG. 2 is a flowchart illustrating a step of forming a metal wiring on a semiconductor substrate according to the present invention.

FIG. 3 is a characteristic diagram showing ESCA data of a Cu surface by various surface treatments.

FIG. 4 is a characteristic diagram showing GIXR data of a Cu surface by a surface treatment.

FIG. 5 is a characteristic diagram showing GIXR data of a Cu surface by a surface treatment.

FIG. 6 is a characteristic diagram showing electrochemical measurement data of a Cu surface by a surface treatment.

FIG. 7 is a characteristic diagram showing electrochemical measurement data of a Cu surface by a surface treatment.

FIG. 8 is a characteristic diagram showing electrochemical measurement data of a Cu surface by a surface treatment.

FIG. 9 is a characteristic diagram showing EELS data of the SiN / Cu interface.

FIG. 10 is a flowchart illustrating a step of forming a metal wiring on a semiconductor substrate of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 14 is a schematic diagram of an electrochemical cell used in the present invention.

FIG. 15 is a sectional view showing a manufacturing process for forming a conventional wiring structure.

FIG. 16 is a flowchart illustrating a process of forming a metal wiring on a conventional semiconductor substrate.

[Explanation of symbols]

1, 111, 202, 204, 208, 212, 216
... insulating film, 2, 112 ... metal film, 4, 114
... metal oxide, 5, 115 ... modified layer, 6, 1
16 silicon nitride film (SiN), 7, 117, 2
17, 219: wiring groove, 8, 113: metal wiring, 201: semiconductor substrate (wafer), 203, 2
07, 211, 215: diffusion preventing film for preventing copper diffusion, 205, 209, 213: photoresist film, 218: connection hole, 206, 214: wiring, 210: connection wiring.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Naoto Miyashita 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office 5F033 HH11 HH12 HH14 HH33 JJ19 JJ33 KK11 KK12 KK33 MM01 MM12 MM13 NN06 NN07 PP15 PP27 QQ00 QQ09 QQ13 QQ19 QQ25 QQ37 QQ48 QQ73 QQ89 QQ93 QQ94 RR01 RR04 RR06 RR09 RR11 RR13 RR21 SS04 SS11 SS15 SS21 TT02 TT04 XX14 XX28 5F043 AA26 BB27 BE12 DD10FF03

Claims (9)

[Claims] A step of forming an insulating film on the semiconductor substrate; a step of forming a wiring groove in the insulating film; a step of embedding a metal wiring in the wiring groove; and a step of performing a surface treatment of the metal wiring. Forming a CVD film on the insulating film and the metal wiring; and improving the adhesion of the CVD film to the metal wiring by the surface treatment. 2. The method according to claim 1, wherein the metal wiring is made of copper or a copper alloy. 3. The method according to claim 1, wherein the CVD film is a silicon nitride film. 4. The method according to claim 3, wherein the silicon nitride film is used as a copper diffusion prevention film. 5. The method according to claim 1, wherein the surface treatment is mainly an oxidation reaction. 6. The method according to claim 5, wherein the metal oxide on the surface of the metal wiring is removed using an acid before or simultaneously with the surface treatment. 7. The semiconductor device according to claim 5, wherein a slurry additive component such as an organic substance attached to the surface of the metal wiring is removed before or simultaneously with the surface treatment. Production method. 8. The oxidizing agent used for the oxidation reaction is at least one of ionic water, aqueous hydrogen peroxide, persulfuric acid, and alkalis, and the acid is a chelating agent, sulfuric acid, halogen, or a halogen compound. At least one, and
The slurry additive component removal method includes a surfactant treatment,
8. The method for manufacturing a semiconductor device according to claim 5, wherein the method is any one of an alkali treatment and a gas dissolved water MHz treatment. 9. The surface state of the metal wiring surface-treated by the method for manufacturing a semiconductor device according to claim 2 is 50 mV vs. 50 mV vs. 10 mM KCl in electrochemical measurement. -750 mV from Ag / AgCl
vs. When the potential is swept through the range up to Ag / AgCl at -2 mV / sec, this range is swept a plurality of times to reduce the current by -2 in the immediately preceding cycle in which the reduction current does not completely flow.
50 to -500 mVvs. When the peak current value observed in Ag / AgCl is from -500 to -750 mVvs. Ag / A
A method for evaluating a semiconductor device, which is evaluated as good when the current value exceeds a peak current value observed in gCl.