JP2002026278A - Ferroelectric memory device and method of manufacturing the same - Google Patents

Abstract

(57) [PROBLEMS] To provide a ferroelectric memory device capable of reducing the parasitic capacitance to a bit line and reducing the area of the entire memory array. A ferroelectric memory device includes a substrate, a plurality of ferroelectric memory cells arranged in an array including a plurality of columns on the substrate, and a ferroelectric memory extending in a column direction and located in the same column. A bit line to which the cell is connected. Each dielectric memory cell includes a transistor formed on a substrate and having a gate and a source / drain, a plug electrode connected to the source / drain of the transistor, and a plug electrode connected to the plug electrode and located above the plug electrode. It includes an island-shaped lower electrode, a ferroelectric film located on the lower electrode, and a pair of upper electrodes located on the ferroelectric film and sharing the lower electrode. The pair of upper electrodes are arranged such that a line connecting the centers of gravity of the upper electrodes is not parallel to the bit lines. That is, the segments connecting the centers of gravity of the upper electrodes are arranged so as to be perpendicular to the bit lines or at a certain angle other than a right angle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a ferroelectric memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art "TC parallel unit serial connection type ferroelectric memory" capable of reducing total chip size
(D. Takashima et.al., JSSCC, pp787
-792, May 1998). This is one in which both ends of a capacitor (C) are connected between the source and drain of a cell transistor (T), respectively, and this is used as a unit cell, and a plurality of the unit cells are connected in series. As a feature of this memory, for each of a plurality of memory cells arranged in an array, an upper electrode is connected to one of source and drain regions sandwiching a gate electrode of a memory cell transistor,
A lower electrode is connected to the other.

FIG. 14 shows a conventional memory cell arrangement.
Each memory cell is arranged so that its longitudinal center line is parallel to a bit line for selecting a column (that is, perpendicular to a word line 102 for selecting a row). More specifically, each memory cell includes a lower electrode 1
05, a pair of upper electrodes 107 sharing the lower electrode 105, and a ferroelectric film (not shown) sandwiched between the upper and lower electrodes to form a pair of capacitors. In this arrangement, the line connecting the centers of gravity of the pair of upper electrodes 105 extends parallel to the bit lines.

In the conventional memory structure shown in FIG. 14, since the direction of the capacitor pair and the direction of the bit line are the same,
The length of the bit line per unit cell has been uniquely determined by the area occupied by the capacitor itself and the contact allowance of the upper electrode.

[0005]

On the other hand, in the TC parallel unit serial connection type ferroelectric memory, as the number of memory cells connected to one memory cell block increases, the area of the entire memory array can be reduced. However, since the upper limit of the number of memory cells is mainly determined by the parasitic capacitance to the bit line, it is difficult to increase the number of memories in the conventional layout shown in FIG.

[0006] In order to solve the above problems, an object of the present invention is to reduce the parasitic capacitance to a bit line, increase the number of memory cells connected to one memory cell block, and improve the sense sensitivity. An object of the present invention is to provide a ferroelectric memory device capable of reducing the area of the entire memory cell array.

Specifically, by arranging a line segment connecting the centers of gravity of a pair of upper electrodes of each memory cell so as not to be parallel to the bit line, the pitch of the word line can be reduced and the pitch of the bit line can be reduced. To enlarge.

It is a second object of the present invention to provide a method for manufacturing a ferroelectric memory device as described above.

[0009]

In order to achieve the above object, a ferroelectric memory device according to a first aspect of the present invention comprises a substrate and a plurality of ferroelectric memories arranged in an array on the substrate. And a memory cell. Each memory cell includes a transistor formed on a substrate, the transistor including a gate, a source, and a drain; and a plurality of plug electrodes connected to the source and the drain of the transistor and located along the first direction on the substrate, respectively. Is connected to one of the plug electrodes and shares an island-shaped lower electrode located above the plug electrode, a ferroelectric film located on the lower electrode, and a lower electrode located on the ferroelectric film. And a pair of upper electrodes. A feature of this memory device is that a line connecting the centers of gravity of a pair of upper electrodes is a first segment on which a pair of plug electrodes are arranged.
Is not parallel to the direction of.

In a more preferred form, each memory cell comprises a transistor formed on a substrate, the transistor including a gate, a source, and a drain; and a nearest-neighboring plug electrode connected to the source and the drain of the transistor, respectively. , Connected to one of the plug electrodes, an island-shaped lower electrode positioned above the plug electrode, a ferroelectric film positioned on the lower electrode, and positioned on the ferroelectric film,
Including a pair of upper electrodes sharing the lower electrode, a line connecting the centers of gravity of the pair of upper electrodes is substantially orthogonal to a line connecting the closest and adjacent plug electrodes.

According to a second aspect of the present invention, there is provided a ferroelectric memory device, comprising: a substrate; a plurality of ferroelectric memory cells arranged on the substrate in an array including a plurality of columns; And a bit line to which ferroelectric memory cells in the same column are connected. Each ferroelectric memory cell includes a transistor formed on a substrate and having a gate and a source / drain, a plug electrode connected to the source / drain of the transistor, and a plug electrode connected to and located above the plug electrode. A lower electrode in the form of an island, a ferroelectric film positioned on the lower electrode, and a pair of upper electrodes positioned on the ferroelectric film and sharing the lower electrode. A feature of this memory device is that a line connecting the centers of gravity of the pair of upper electrodes is not parallel to the bit line.

A line connecting the centers of gravity of the pair of upper electrodes is, for example, perpendicular to the bit line or extends obliquely to the bit line. As an example of the oblique direction, the pair of upper electrodes has a line connecting the centers of gravity thereof at 45 ° with respect to the bit line.
Are arranged at an angle. In this way, the line connecting the center of gravity of the upper electrode of the memory cell is positioned perpendicularly or obliquely to the bit line, so that the distance between the word lines is reduced and the distance between the bit lines is increased. Becomes possible. That is, the entire array area can be reduced, and the parasitic capacitance to the bit line can be reduced.

The plug extending from the source / drain is located at the position of the center of gravity of the lower electrode or eccentric from the center of gravity of the lower electrode.

Preferably, the ferroelectric memory cell further has an oxidation-resistant film located below the lower electrode. Further, it is preferable that the upper part or all of the plug electrode of the ferroelectric memory cell is made of a material that does not lose conductivity in an oxidizing atmosphere. This is to prevent oxygen contained in the annealing gas from oxidizing the plug electrode in the subsequent heat treatment step, while maintaining conductivity.

According to a third aspect of the present invention, there is provided a ferroelectric memory device comprising: a substrate; and a plurality of ferroelectric memories arranged on the substrate in an array including a plurality of columns, each having a longitudinal center line. Body memory cell, and a bit line for selecting the column, the ferroelectric memory cell in the same column, the longitudinal center line thereof at a predetermined angle with respect to the bit line, Connected to the same bit line. The feature of this memory device is that the longitudinal center line of the memory cell connected to the adjacent bit line is halved.
The point is that they are shifted by a pitch and are located alternately.

Each memory cell includes a transistor formed on a substrate and having a gate and a source / drain, a plug electrode connected to the source / drain of the transistor, and a plug electrode located above the plug electrode. A lower electrode is connected and extends in a direction perpendicular to the bit line, a ferroelectric film located on the lower electrode, and a pair of upper electrodes located on the ferroelectric film and sharing the lower electrode.

Preferably, the lower electrode has a planar shape in which two rectangles rotated by 45 ° with respect to the bit line are connected.

This ferroelectric memory device further has via contacts arranged between the adjacent memory cells arranged along the direction of the bit lines. A sufficient distance can be provided from the via contact to the constricted portion, which is the connection portion of the rectangular lower electrode, and the parasitic capacitance can be reduced. Also, since the memory cells connected to the adjacent bit lines are alternately arranged with a shift of 1/2 pitch,
At the same time as securing a sufficient space around the contact, it is possible to make the space between the cells closest, and the area of the entire array can be reduced.

As another layout example, each memory cell includes a pair of lower electrodes located at a predetermined interval above a plug electrode, a ferroelectric film formed on each lower electrode, and a ferroelectric film. And an upper electrode located on the film.
The pair of lower electrodes is connected to a common plug electrode, and a straight line connecting the centers of gravity of these lower electrodes is perpendicular to the bit lines. In this case, the horizontal cross-sectional shape of the common plug electrode is, for example, elliptical. The lower electrode has, for example, a rectangular planar shape rotated by 45 ° with respect to the bit line. This configuration enables the lower electrode, the ferroelectric film, and the upper electrode to be collectively processed, in addition to the effects of the close-packed arrangement of cells and the space around the contact.

As a fourth feature of the present invention, a method for manufacturing a ferroelectric memory device is provided. First, transistors each including a gate, a source, and a drain are formed in an array on a substrate of a first conductivity type. Next, a plurality of plug electrodes extending in the first direction are formed on the source and the drain of each transistor. Then, a lower electrode is formed so as to be in contact with the plug electrode. A ferroelectric film is formed on a lower electrode of each transistor. A pair of upper electrodes are formed on the ferroelectric film such that a line connecting the centers of gravity is located along a second direction different from the first direction.
Further, the lower electrode and the ferroelectric film are processed so that the lower electrode of each transistor is connected to one plug electrode.
Finally, a via contact is formed to contact a plug electrode not connected to the lower electrode.

Other features and advantages of the present invention will become apparent from the detailed description given below with reference to the drawings.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIGS. 1 and 2
1 is a plan view of a ferroelectric memory device according to a first embodiment of the present invention.

The ferroelectric memory device has a plurality of ferroelectric capacitor cells 20 arranged in a matrix on a substrate. The ferroelectric capacitor cell 20 is connected to a word line 2 for selecting a row (row) of the matrix and a bit line 10 for selecting a column. Specifically, at one end of an element region 1 (a region surrounded by a dashed line in FIG. 1) for a memory block including a plurality of memory cells 20, a transfer gate (memory block selection gate) is provided. A bit line is connected, and a plate line is connected to the opposite end. In the write and read operations, a specific gate line is turned off after a specific memory cell block is selected by a memory block selection gate.
By setting the level, a specific memory cell is selected, and further, by charging and discharging the plate line, writing and reading operations to and from the capacitor are performed.

In the ferroelectric memory device according to the first embodiment,
Each ferroelectric capacitor cell 20 is a rectangular cell arranged such that its center line in the longitudinal direction is perpendicular to the bit line 10.

As shown in FIG. 2, each capacitor cell 20 has a transistor formed on a substrate and having a gate 12 and a source / drain 3, and a plug electrode 4a connected to the source / drain of the transistor. The rectangular lower electrode 5 is connected to the plug electrode 4a and extends in a direction perpendicular to the bit line 10. On the lower electrode 5, a ferroelectric film 6 and a pair of upper electrodes 7 located on the ferroelectric film 6 and sharing the lower electrode are arranged. The lower electrode 5, the ferroelectric film 6, and the upper electrode 7 constitute a capacitor.

As shown in FIG. 2A, a pair of upper electrodes 7 share a single lower electrode 5 and have a capacitor structure in which a ferroelectric film 6 is interposed therebetween. Has formed. This capacitor constitutes a nonvolatile memory utilizing the polarization reversal characteristics of the ferroelectric film 6. As described above, in the first embodiment, the line connecting the centers of gravity of the pair of upper electrodes 7 is orthogonal to the bit line 10. In the first embodiment, the direction of the bit line 10 and the direction of the plug electrodes 4a and 4b closest to and adjacent to each other in each capacitor cell 20 match. Therefore, the line connecting the centers of gravity of the pair of upper electrodes 7 is orthogonal to the line connecting the plugs that are closest and adjacent to each other.

As shown in the sectional view taken along the line BB of FIG.
Below the lower electrode 5, a switching transistor including a gate 12 and a source / drain 3 is formed. Plug electrodes 4 a and 4 b are connected to source / drain 3. Among these, the plug electrode 4a is connected to the lower electrode 5 constituting the capacitor, and when the word line 2 to which the ferroelectric capacitor cell is connected is selected, the transistor is turned on and stored in the capacitor. The charge (accumulated data) is output to the bit line. In the first embodiment, the plug electrode 4a is located at the center of gravity of the lower electrode 5.

On the other hand, the plug electrode 4b is connected to the upper metal wiring 9 via the upper via contact 8b.

In such a cell arrangement, bit line 1
Since each capacitor cell 20 is arranged in a direction perpendicular to 0, the interval (pitch) between word lines 2 can be reduced. In the conventional cell arrangement, as shown in FIG. 10, rectangular capacitor cells are arranged in a direction parallel to the bit lines,
There is a limit in shortening the interval between the word lines 102.
In addition, since each capacitor cell 20 is arranged in a direction perpendicular to the bit line 10, the pitch of the bit line 10 can be widened to some extent, and the parasitic capacitance to the bit line can be greatly reduced. .

FIG. 3 shows a modification of the capacitor cell shown in FIG. The ferroelectric capacitor cell 30 shown in FIG.
Instead of a rectangular lower electrode, it has an hourglass-shaped lower electrode 35 having a constricted portion at the center, and a pair of upper electrodes 37 adapted to the shape of the lower electrode 35.

The feature of this cell structure is that the lower electrode 35 has a constricted portion at the center, so that a sufficient distance can be provided between the via contact 8b formed above the plug electrode 4b and the lower electrode 35. On the point. As described above, by keeping the distance between the lower electrode and the contact while keeping the interval between the word lines tight, the array size can be reduced and the parasitic capacitance can be further reduced. Reduction of parasitic capacitance greatly contributes to improvement of reliability of device performance. That is, the cell arrangement shown in FIG. 3 sufficiently satisfies the expectations of a semiconductor integrated circuit such as high integration and high performance.

<Second Embodiment> FIG. 4 shows a capacitor cell 4 of a ferroelectric memory device according to a second embodiment of the present invention.
FIG. 11 is a diagram showing a plane layout of a zero.

The feature of the memory device of the second embodiment is that the capacitor cells 40 in the same column are connected to the same bit line so that the center line in the longitudinal direction is orthogonal to the bit line, and are adjacent to each other. The center lines of the capacitor cells connected to the bit lines are shifted by 1/2 pitch each other,
It is in a staggered position.

In the second embodiment, the planar shape of the capacitor cell 40 is formed by connecting two rectangles obtained by rotating the lower electrode 45, the ferroelectric film 46, and the upper electrode 47 by 45 ° with respect to the bit line. Character shape. The plug electrode 4a corresponding to the plug electrode 4a in FIG. 2 is located below the center of gravity of the lower electrode 45, that is, below the two rectangular connecting portions.
In accordance with the shape of the lower electrode 45, the shapes of the ferroelectric film 46 and the upper electrode 47 are also 4
It becomes a rectangle rotated by 5 °. This layout can secure a further distance from the via contact 8b than the shape of the lower electrode having the constricted portion described in connection with FIG. 3 in the first embodiment.

The ferroelectric capacitor cells 40 included in the adjacent columns (the columns extending in the horizontal direction in FIG. 4 correspond to the columns) are different from each other with a pitch shifted by ピ ッ チ. Such an arrangement is realized by the shape of the lower electrode 45 rotated by 45 °. That is, since the lower electrode 45 has a rectangular shape rotated by 45 ° with respect to the bit line, a sufficient space can be secured between the ends of adjacent capacitor cells in the same column. Then, the end of the capacitor cell of the next column can be inserted. Therefore, it is possible to make the structure closer than the first embodiment.

Conversely, when the array area is made the same as the conventional one, it becomes possible to maximize the effective area of each individual capacitor cell. When the effective area of the capacitor cell increases, the storage capacity of the memory cell is sufficiently ensured, and the operation margin during the sensing operation is ensured. In addition, it is possible to increase the resistance to fatigue deterioration due to the write / read cycle and imprint. As a result, the reliability of the entire memory device is improved, and a high-performance memory can be provided.

FIG. 5 shows a modification of the cell arrangement of the second embodiment. In the example of FIG. 5, the lower electrode 55 is divided into two in one capacitor cell 50, and these lower electrode pairs are commonly connected by the plug electrode 4a. At this time, in order to ensure the connectivity, the horizontal cross-sectional shape of the plug electrode 4a is
Make it elliptical.

This layout is excellent in that the lower electrode 55, the ferroelectric film 56, and the upper electrode 57 can be processed collectively. That is, in the layout shown in FIG. 4, a photolithography process for the lower electrode and a photolithography process for the ferroelectric film 46 and the upper electrode 47 are separately required, but in the configuration of FIG. Since the lower electrode 55 can be processed collectively, a photolithography step for processing the lower electrode can be omitted.

Third Embodiment FIG. 6 shows a capacitor cell 6 of a ferroelectric memory device according to a third embodiment of the present invention.
FIG. 11 is a diagram showing a plane layout of a zero. A feature of the third embodiment is that a pair of upper electrodes 67 sharing one lower electrode 65 is connected to a bit line (not shown) extending parallel to an adjacent parallel line in the element region 1. That is, they are arranged so as to form a predetermined angle. In other words, FIG.
In the example shown in (1), the plug 64a is located at the center of gravity of the lower electrode 65, and a pair of plugs 64a and 64b connected to the source / drain of the same cell are arranged along the direction in which the bit line extends. Therefore, the line connecting the center of gravity of the pair of upper electrodes 67 is constant with respect to the line connecting the plug 64a connected to the source / drain of each capacitor cell 60 and the via contact 68b in the same element region 1. Make an angle. The via contact 68b is a via contact formed above a plug 64b (not shown) that forms a pair with the plug 64a and for connecting an upper metal wiring.

Although the example of FIG. 6 shows an arrangement in which the upper electrode forms an angle of 45 ° with the center of gravity bit line, the present invention is not limited to this, and the rotation angle θ with respect to the bit line is parallel to the bit line. Unless otherwise required (in the range of 0 <θ <180 °), it can be adjusted appropriately. This makes it possible to optimally adjust the length / width ratio of the memory cell array according to the use of the memory device to be manufactured.

Further, by rotating the line connecting the centers of gravity of the pair of upper electrodes 67 with respect to the bit lines, the pitch of the word lines 2 can be narrowed and the close-packed arrangement can be achieved. .

FIG. 7 shows a modification of the capacitor cell of the ferroelectric memory device shown in FIG. In the capacitor cell 70 of FIG. 7, the lower electrode 75 is a polygon in which a rectangle and a triangle are combined. A pair of upper electrodes 7 of the capacitor cell 70
7 forms a predetermined angle with respect to a straight line connecting the plug 74a located at the center of gravity of the lower electrode 75 and the via contact 78b. Also in the example of FIG. 7, the plug 74a and the via contact 78b are located along the direction of the bit line (not shown).
The line segment connecting the center of gravity 7 forms a predetermined angle with respect to the bit line.

The characteristics of the capacitor cell 70 shown in FIG.
Plug 74 connecting lower electrode 75 to source / drain
a and the upper electrode 77 can be separated by an effective distance. Features of ferroelectric capacitors are:
Because the orientation and surface condition of the lower electrode may be sensitive,
It is important to adjust the distance between the plug 74a and the upper electrode 77 as the case may be. The layout shown in FIG. 7 facilitates such adjustment of the distance between the plug and the electrode.

If it is desired to further increase the distance between the plug 74a and the upper electrode 77, a triangular area connecting two rectangles may be a trapezoidal area. In this case, the interval between the word lines is increased to about the same level as the cell arrangement of the related art.
The execution distance between the plug and the upper electrode can be increased to a considerable extent while maintaining the same word line interval, and the memory performance can be improved.

<Fourth Embodiment> FIGS. 8 and 9 show a capacitor cell of a ferroelectric memory device according to a fourth embodiment of the present invention. In the fourth embodiment, the position of the plug connecting the lower electrode to the source / drain of the transistor is
It is eccentric from the center of gravity of the lower electrode.

The capacitor cell 80 shown in FIG.
Except for the position a, the capacitor cell has the same configuration as the capacitor cell shown in FIG. That is, in FIG. 1, the plug 84a is located at the center of gravity of the lower electrode.
Then, the position of the plug 84 a is located slightly off the center of gravity of the lower electrode 85.

By eccentricity of the plug 84a, a degree of freedom in design can be ensured in a logic memory mounted chip or the like. Actually, in an actual product, a certain degree of eccentricity may be required at the plug position.
The layout has the effect of reducing the word line pitch and securing design flexibility.

FIG. 9 shows another example in which the plug position is eccentric. The capacitor cell 90 includes a rectangular lower electrode 95 extending parallel to the word line 2, a pair of upper electrodes 97 located on the lower electrode, and a ferroelectric film (not shown) sandwiched between the upper electrode and the lower electrode. And In the example shown in FIG. 9, the plug 94a connecting the lower electrode 95 to the source / drain of the transistor is outside the upper electrode pair 97. Also, via contacts 9 in the same element region 1
8b is positioned such that a straight line connecting the plug 94a and the via contact 98b is parallel to a bit line (not shown).

This layout is effective when it is necessary to ensure an effective distance between the plug and the upper electrode, as in FIG. Specifically, the upper electrode 97 and the plug 94
Although the upper electrode may be close to each other, the upper electrode 97 and the plug
When a sufficient distance from 4a is required, the arrangement of FIG. 9 can realize a reduction in the overall array area. Further, since the interval between the bit lines can be made larger than that of the layout of FIG. 1, the parasitic capacitance with respect to the bit lines can be reduced, and the memory performance can be improved.

<Fifth Embodiment> FIGS. 10 to 13 are views showing a process of manufacturing the ferroelectric memory device shown in FIG.

(A) First, as shown in the sectional view taken along the line AA in FIG. 10A and the sectional view taken along the line BB in FIG. A region 63 is formed, and a gate 12 and an n-type diffusion layer (source / drain) 3 are formed. Gate and source /
For example, tungsten silicide or the like may be formed on the surface of the drain. Thereafter, an interlayer insulating film 64 is deposited and flattened by a CVD method or the like, and a contact hole reaching the source / drain 3 is opened by photolithography and etching. Fill the contact hole with an electrode material (eg, doped polycrystalline silicon or tungsten)
After deposition by VD method etc., CMP (Chemical Mechanical Polishing)
The surface is flattened by CDE (Chemical Dry Etching) and the plug electrode 4b is formed. Further, an oxidation resistant film (such as a nitride film) 11 is deposited, and thereafter, a contact hole for the plug 4a is formed, and an electrode material is filled in the same manner as 4b. The oxidation resistant film 11 prevents oxygen generated in the electrode material in a later heat treatment step from diffusing into a lower layer.

(B) Next, as shown in FIG. 11, a lower electrode material, a ferroelectric film, and an upper electrode material are sequentially deposited. The lower and upper electrode materials include platinum (Pt),
Iridium (Ir), iridium dioxide (IrO ₂ ), or the like is used. Further, as a ferroelectric material, PZT (P
bZr _x Ti _1-x O ₃ ) or SBT (SrBi ₂ Ta ₂ O ₉ )
Is used.

(C) Next, as shown in FIG. 12, an upper electrode 7, a ferroelectric film 6, and a lower electrode 5 are formed by photolithography and etching. At this time, patterning is performed so that the upper electrodes 7 are arranged in a direction perpendicular to the bit lines 10.

(D) Finally, as shown in FIG. 9, an interlayer insulating film 65 is deposited. For example, P-TEOS (tetra et
An interlayer insulating film 65 is formed by a hoxy silage type plasma CVD or an O ₃ -TEOS type plasma CVD. Then, a via hole 18a connected to the plug 4B is formed by photolithography and etching, and the hole is filled with tungsten or the like by a CVD method or the like to complete the via contact 18b. Thereafter, an upper metal wiring including the bit line 10 is formed, and the ferroelectric memory device is completed.

[0055]

As described above, according to the ferroelectric memory device of the present invention, each capacitor cell is arranged so that its longitudinal direction is perpendicular to the bit line (ie, extends parallel to the word line). It is formed, and the interval between word lines can be reduced. This reduces the area of the entire array. Further, since the interval between the bit lines can be increased, the parasitic capacitance to the bit lines can be reduced, and the reliability of device operation can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a ferroelectric memory device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views of the ferroelectric memory device shown in FIG. 1, wherein FIG. 1A is a cross-sectional view taken along the line AA, and FIG.

FIG. 3 is a diagram showing a modification of the capacitor cell shown in FIG.

FIG. 4 is a plan view showing a cell shape of a ferroelectric memory device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a modification of the capacitor cell shown in FIG.

FIG. 6 is a plan view showing a cell shape of a ferroelectric memory device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing another example of the cell shape of the ferroelectric memory device according to the third embodiment of the present invention.

FIG. 8 is a plan view showing a cell shape of a ferroelectric memory device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing another example of the cell shape of the ferroelectric memory device according to the fourth embodiment of the present invention.

FIG. 10 is a view showing a transistor forming step in the method for manufacturing a ferroelectric memory device according to the present invention;
10A is a cross-sectional view taken along line AA of FIG. 1, and FIG.
It is a figure which shows the manufacturing process of the -B cross section.

11A and 11B are diagrams illustrating a process of forming a lower electrode, a ferroelectric, and an upper electrode in a method of manufacturing a ferroelectric memory device according to the present invention. FIG. 1
FIG. 1B is a diagram showing a manufacturing process of the BB cross section of FIG. 1.

12A and 12B are diagrams showing a patterning step of an upper electrode and a lower electrode in a method of manufacturing a ferroelectric memory device according to the present invention. FIG. 12A is a sectional view taken along line AA of FIG.
(B) is a figure which shows the manufacturing process of the BB cross section of FIG.

FIG. 13 is a view showing a step of forming an interlayer insulating layer and a via hole in the method of manufacturing a ferroelectric memory device according to the present invention. FIG.
(B) is a figure which shows the manufacturing process of the BB cross section of FIG.

FIG. 14 is a diagram showing a cell arrangement of a conventional ferroelectric memory device.

[Explanation of symbols]

1, 101 element region 2, 102 word line 3 diffusion layer 4a, 4b, 54a, 64a, 74a, 84a, 94a
Plug electrode 5, 35, 45, 55, 65, 75, 85, 95 Lower electrode 6 Ferroelectric film 7, 37, 47, 57, 67, 77, 87, 97 Upper electrode 8a, 8b, 68b, 78b, 88b , 98b Via contact 9 Metal wiring 10 Bit line 11 Oxidation resistant film 12 Gate 20, 30, 40, 50, 60, 70, 80, 90 Ferroelectric capacitor cell

Claims (19)

[Claims] 1. A semiconductor device comprising: a substrate; and a plurality of ferroelectric memory cells arranged in an array on the substrate, wherein each of the memory cells includes a gate, a source, and a drain formed on the substrate. A plurality of plug electrodes connected to a source and a drain of the transistor, respectively, and located along a direction in a first direction on a substrate; connected to one of the plug electrodes; An island-shaped lower electrode located on the lower electrode, a ferroelectric film located on the lower electrode, and a pair of upper electrodes located on the ferroelectric film and sharing the lower electrode; A line connecting the center of gravity of the upper electrode is not parallel to the first direction. 2. A semiconductor device comprising: a substrate; and a plurality of ferroelectric memory cells arranged in an array on the substrate, wherein each of the memory cells includes a gate, a source, and a drain formed on the substrate. A plug electrode connected to the source and the drain of the transistor, respectively, closest to and adjacent to each other; an island-shaped lower electrode connected to one of the plug electrodes and located above the plug electrode; A ferroelectric film located on the lower electrode, and a pair of upper electrodes located on the ferroelectric film and sharing the lower electrode, wherein a line connecting the centers of gravity of the pair of upper electrodes is A ferroelectric memory device, which is substantially orthogonal to a line connecting the closest and adjacent plug electrodes. 3. A substrate, a plurality of ferroelectric memory cells arranged in an array including a plurality of columns on the substrate, and ferroelectric memory cells extending in the column direction and located in the same column are connected. Wherein each of the ferroelectric memory cells comprises a transistor formed on the substrate and comprising a gate and a source / drain; a plug electrode connected to the source / drain of the transistor; and the plug An island-shaped lower electrode connected to the electrode and located above the plug electrode; a ferroelectric film located on the lower electrode; and a pair of ferroelectric films located on the ferroelectric film and sharing the lower electrode. And a line connecting the centers of gravity of the pair of upper electrodes is not parallel to the bit line. 4. The ferroelectric memory device according to claim 3, wherein a line segment connecting centers of gravity of said pair of upper electrodes is perpendicular to said bit line. 5. The ferroelectric device according to claim 3, wherein a line segment connecting the centers of gravity of the pair of upper electrodes is positioned obliquely at a predetermined angle with respect to the bit line. Body memory device. 6. The ferroelectric memory device according to claim 3, wherein the plug is located at a center of gravity of the lower electrode. 7. The ferroelectric memory device according to claim 3, wherein the plug is located eccentrically from the center of gravity of the lower electrode. 8. The ferroelectric memory device according to claim 3, wherein the shape of the lower electrode is a rectangle whose center line forms a predetermined angle with respect to the bit line. 9. The ferroelectric memory device according to claim 3, wherein the shape of the lower electrode is a shape having a narrow portion between the pair of upper electrodes. 10. The semiconductor device according to claim 1, further comprising a via contact located between adjacent memory cells in the column direction, wherein a distance from a narrow portion of the lower electrode to the via contact is ensured to be a predetermined distance or more. The ferroelectric memory device according to claim 9, wherein: 11. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory cell further includes an oxidation-resistant film located below the lower electrode. 12. The ferroelectric material according to claim 1, wherein the upper part or all of the plug electrode of the ferroelectric memory cell is made of a material that does not lose conductivity in an oxidizing atmosphere. Memory device. 13. A substrate, a plurality of ferroelectric memory cells arranged on the substrate in an array including a plurality of columns, each having a longitudinal center line, and a bit for selecting the column. And ferroelectric memory cells in the same column are connected to the same bit line so that the center line in the longitudinal direction forms a predetermined angle with respect to the bit line, and are connected to adjacent bit lines. The ferroelectric memory device according to claim 1, wherein the center lines in the longitudinal direction of the connected memory cells are staggered by 1/2 pitch. 14. Each of the ferroelectric memory cells includes a transistor formed on the substrate, the transistor including a gate and a source / drain; a plug electrode connected to the source / drain of the transistor; A lower electrode connected to the plug electrode and extending in a direction perpendicular to the bit line; a ferroelectric film positioned on the lower electrode; a ferroelectric film positioned on the ferroelectric film; 14. A pair of upper electrodes sharing a lower electrode.
3. The ferroelectric memory device according to 1. 15. Each of the ferroelectric memory cells includes a transistor formed on the substrate, the transistor including a gate and a source / drain; a plug electrode connected to a source / drain of the transistor; A pair of lower electrodes located at a predetermined interval in the upper layer and commonly connected to the plug electrode; a ferroelectric film located on the pair of lower electrodes; and a pair of upper portions located on the ferroelectric film 14. The ferroelectric memory device according to claim 13, wherein a line segment connecting the centers of gravity of the pair of lower electrodes forms a predetermined angle with respect to the bit line. 16. The ferroelectric memory device according to claim 15, wherein a horizontal cross-sectional shape of the plug electrode is elliptical. 17. A method comprising: forming a transistor comprising a gate, a source and a drain in an array on a substrate of a first conductivity type; and forming a first transistor on the source and the drain of each transistor.
Forming a plurality of plug electrodes along the direction of; forming a lower electrode so as to contact the plug electrode of each transistor; forming a ferroelectric film on the lower electrode of each transistor Forming a pair of upper electrodes on the ferroelectric film of each of the transistors such that a line segment connecting these centers of gravity extends along a second direction different from the first direction; Processing the lower electrode and the ferroelectric film so that the lower electrode of each transistor is connected to one of the plug electrodes. 18. The method according to claim 1, further comprising, before the lower electrode forming step, forming an oxidation-resistant conductive film so as to contact the plug electrode.
8. The method for manufacturing a ferroelectric memory device according to item 7. 19. A step of depositing an interlayer insulating film covering the upper lower electrode, the ferroelectric film, and the upper electrode; The method of claim 17, further comprising: forming a via contact to be reached; and forming a metal wiring connected to the via contact.