JP2002026009A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: To prevent Cu contamination from the back surface of a substrate when a Cu-DD wiring is used. A diffusion preventing layer for preventing Cu diffusion is provided on a silicon oxide film of an SOI substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device for reducing metal contamination such as Cu, particularly from a back surface of a substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to reduce parasitic capacitance and manufacture a higher-speed semiconductor device, SOI is also required for consumer products.
(Silicon On Insulator) Introduction of substrates is in progress. On the other hand, with the increase in the degree of integration of semiconductor devices and miniaturization of semiconductor elements, multilayer wiring has been developed. At the same time,
Cu wiring, which has lower resistance and higher melting point than Al wiring, which has been often used, has come to be used. In other words, in the future, higher integration of semiconductor devices
It is expected that higher performance will be achieved by a combination of an SOI substrate and Cu wiring.

[0005] Cu wiring is made of Al which has been conventionally used.
The RC delay by the wiring itself is smaller than the wiring, and
Even when the current density is high, there is a great advantage that disconnection is difficult, in other words, electromigration resistance is high.

However, since Cu has a large diffusion coefficient in silicon, if a process involving heating is performed after the formation of the Cu wiring, Cu in the Cu wiring diffuses into the SiO ₂ -based interlayer insulating film. As a result, there arises a problem that the leakage current and the relative dielectric constant of the interlayer insulating film increase. In a severe case, there is a problem that Cu diffuses into the gate insulating film and the threshold voltage fluctuates. A similar problem occurs when a high electric field is applied to Cu.

In order to solve the above problem, the side and bottom surfaces of the Cu wiring are covered with a film made of a metal compound such as TaN for preventing diffusion of Cu, which is called a barrier metal film, while the upper surface of the Cu wiring is formed as a so-called top barrier film. Covering with an insulating film such as a silicon nitride film called a so-called silicon nitride film is performed.

[0006] By such a method, C in the interlayer insulating film.
Although the problem of diffusion of u can be solved, the problem of Cu diffusion remains as follows, which cannot be solved by the above method.

That is, when Cu adheres to the back surface of the silicon substrate during the formation of the Cu wiring and the adhered Cu diffuses in the silicon substrate to reach the element region, there is a problem that the element characteristics deteriorate or fluctuate. Occur.

[0008]

As described above, the Cu wiring is an effective wiring for higher integration and higher performance of a semiconductor device. However, in the prior art, the problem caused by Cu diffusing from the back surface of the silicon substrate is caused. Remained unresolved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device and a method of manufacturing the same, which can solve the problem caused by metal diffused from the back surface of a semiconductor substrate. is there.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows. The gist of the present invention is to introduce a structure for preventing metal diffusion into a semiconductor substrate. That is, in order to achieve the above object, a semiconductor device according to the present invention
A first semiconductor substrate; an insulating film provided on the first semiconductor substrate; and a second semiconductor substrate provided on the insulating film. At least one is provided with a metal diffusion preventing layer in which nitrogen is introduced.

Here, the first and second semiconductor substrates may be separate or the same. In the same case, nitrogen is introduced into the semiconductor substrate by, for example, ion implantation. As a result, the semiconductor substrate is divided into a first semiconductor substrate and a second semiconductor substrate at a region including nitrogen.

With such a structure, the metal adhered to the back surface of the first semiconductor substrate can be prevented from diffusing to the second semiconductor substrate by the diffusion preventing layer, and is caused by Cu diffused from the back surface of the substrate. Be able to solve problems.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 1A shows an SOI substrate.
Reference numerals 1 and 3 denote a single crystal silicon substrate, and 2 denotes a silicon oxide film. Although there are several methods for forming an SOI substrate, a bonding method will be described here. First, a silicon oxide film 2 is formed on the surface of a silicon substrate 1 by thermal oxidation. On the other hand, another silicon substrate 3 whose surface is mirror-polished is prepared, and these silicon substrates 1 and 3 are bonded together in a vacuum atmosphere via the silicon oxide film 2.
Thereafter, the silicon substrate 3 is polished to a required thickness, and FIG.
The SOI substrate shown in FIG.

Next, as shown in FIG. 1B, after nitrogen ions are implanted into the silicon substrate 3, annealing is performed.
The diffusion prevention layer 4 is formed in the silicon substrate 3. At this time, enough nitrogen atoms are implanted into the silicon substrate 3 so that the diffusion preventing layer 4 becomes a silicon nitride film in a chemical quantum theory. The diffusion preventing layer 4 is formed on the silicon oxide film 2 so as to be in contact therewith. In this case, the acceleration voltage of the nitrogen ions is controlled so that the nitrogen concentration of the silicon substrate 3 above the silicon oxide film 2 is maximized. Nitrogen may be introduced into the silicon oxide film 2 as well.

Note that a method may be employed in which nitrogen ions are implanted into the upper portion of the silicon oxide film 2 under the condition that the nitrogen concentration becomes maximum, and the upper portion of the silicon oxide film 2 is transformed into the silicon nitride layer 4.

Next, as shown in FIG. 1C, an element isolation groove reaching the diffusion prevention layer 4 is formed in the silicon substrate 3 and the inside thereof is filled with an element isolation insulating film 5 to perform element isolation. Thus, an active element such as a MOS transistor is formed in an element formation region defined by the element isolation insulating film 5. In the figure, 6 is a gate insulating film, 7 is a gate electrode, 8 is a gate side wall insulating film (spacer), and 9 is a source / drain region having an extension. Thereafter, an interlayer insulating film 10 is deposited on the entire surface as shown in FIG.
Open.

Next, as shown in FIG. 2D, after a barrier metal film 12 is formed on the entire surface so as to cover the inner surfaces of the connection holes and the wiring grooves 11, Cu is formed so as to fill the connection holes and the wiring grooves 11. The film 13 is formed on the entire surface by, for example, a plating method. As a material of the barrier metal film 12, TaN, W
Preference is given to nitrides such as N, VN, NbN, CrN, MoN.

Next, as shown in FIG. 2E, the unnecessary Cu film 13 and the barrier metal film 12 outside the connection hole and the wiring groove 11 are removed by CMP, and the Cu dual damascene wiring (Cu-DD wiring) is removed. ) Is formed. After that, an insulating film (not shown) as a top barrier film is formed. In the CMP process, the Cu film 13 and the barrier metal film 12 are formed under different conditions under different conditions in order to suppress dishing.
It is preferable to use so-called two-step polishing for removing by MP.

Next, as shown in FIG. 2 (f), after an interlayer insulating film 14 is deposited on the entire surface, an upper Cu-DD wiring (see FIG. 2 (d) and FIG. A Cu wiring + barrier metal film) 15 is formed. Here, a multi-layer wiring of two layers is shown, but a multi-layer wiring of three or more layers may be formed in the same manner. In this case, not all of the multilayer wirings need to be Cu wirings, and for example, some may be Al wirings. Thereafter, a passivation film 16 is deposited on the entire surface as shown in FIG.

In the step of forming the Cu-DD wiring,
Even if Cu adheres to the back surface of the silicon substrate 1 and Cu diffuses in the silicon substrate 1, the diffusion stops at the diffusion prevention film 4, so that deterioration and fluctuation of element characteristics due to Cu contamination can be prevented. Further, as in the conventional case, the diffusion of Cu into the interlayer insulating film 3 can be prevented by the barrier metal film 12 and the top barrier film (not shown). further,
Prevention of metal contamination from the back surface of the substrate by a metal other than Cu-DD wiring used during manufacturing can also be expected.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the bonding method is used as the method of forming the SOI substrate.
The X method may be used. In this case, high-energy oxygen ion implantation and nitrogen ion implantation are sequentially performed, and then a high-temperature heat treatment is performed to form the silicon oxide film 2 and the diffusion prevention layer 4. Thereafter, the steps shown in FIG.

In the above embodiment, the silicon oxide film 2 and the diffusion prevention layer 4 are in contact with each other.
As shown in (1), the silicon oxide film 2 and the diffusion prevention layer 4 may be formed in completely separate layers. In this case, it is possible to prevent the silicon oxide film 2 from containing nitrogen. Further, as shown in FIG. 4, the positional relationship between the silicon oxide film 2 and the diffusion prevention layer 4 may be reversed so that the silicon oxide film 2 is provided on the diffusion prevention layer 4. Furthermore, a mixed layer in which the silicon oxide film 2 and the diffusion preventing layer 4 are mixed, for example, S
An iON film may be used.

In the above embodiment, the silicon nitride film is used as the diffusion preventing layer 4. However, any insulating film that can prevent the diffusion of Cu, such as a silicon carbide film, an aluminum nitride film, an aluminum oxide film, and a boron nitride film, may be used. A similar effect can be expected. In the case of an aluminum nitride film or the like, it is difficult to form the film by an ion implantation method.
And the like. Further, the above-listed insulating films may be used as the insulating film of the SOI substrate. In this case, if the insulating film of the SOI substrate and the insulating film as the diffusion preventing layer are the same type of insulating film, the substrate structure can be simplified.

Further, the above-described embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, if the effects described in the section of the effect of the invention can be obtained, the structure from which the constituent elements are deleted is the invention. Can be extracted as In addition, various modifications can be made without departing from the scope of the present invention.

[0028]

As described above in detail, according to the present invention, by introducing a structure for preventing metal diffusion into a semiconductor substrate, it is possible to solve the problem caused by the metal diffused from the back surface of the semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method of manufacturing the semiconductor device following FIG. 1;

FIG. 3 is a sectional view showing a modification of the embodiment.

FIG. 4 is an exemplary sectional view showing another modification of the embodiment;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate (first semiconductor substrate) 2 silicon oxide film (first insulating film) 3 silicon substrate (second semiconductor substrate) 4 diffusion preventing layer (second insulating film) 5 element isolation Insulating film 6 ... Gate insulating film 7 ... Gate electrode 8 ... Gate side wall insulating film 9 ... Source / drain region 10 ... Interlayer insulating film 11 ... Connection hole and wiring 12 ... Barrier metal film 13 ... Cu film (Cu wiring) 14 ... Interlayer Insulating film 15: Cu-DD wiring (Cu wiring + barrier metal film) 16: Passivation film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8234 H01L 21/88 R 27/088 21/76 D 27/08 331 R 27/12 27/08 102D 29/78 626C 29/786 627D 21/336 (72) Inventor Hideki Shibata 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama office (reference) 5F032 AA06 AA07 CA17 DA02 DA33 DA43 DA60 5F033 GG03 HH11 HH32 HH34 JJ11 JJ32 JJ34 KK11 KK32 KK34 MM02 MM12 MM13 NN06 NN07 PP26 QQ48 QQ58 QQ64 RR01 RR03 RR05 RR06 RR08 SS11 BD25 XX28 5F048 AC01 BA09 BA16 BC06 BF01 BF02 BF01 BF02 DA07 AA06 AA14 AA26 CC02 DD05 DD12 DD13 DD14 DD15 DD17 EE31 EE38 HL01 HL02 HL21 HM15 NN02 NN62 NN65 QQ17

Claims (6)

[Claims] 1. A semiconductor device comprising: a first semiconductor substrate; an insulating film provided on the first semiconductor substrate; and a second semiconductor substrate provided on the insulating film. A semiconductor device comprising a metal diffusion preventing layer formed by introducing nitrogen into at least one of the second semiconductor substrate and the insulating film. 2. A first semiconductor substrate; a first insulating film provided on the first semiconductor substrate; a second insulating film provided on the first insulating film; A second semiconductor substrate provided on the second insulating film, wherein at least one of the first and second insulating films has a diffusion preventing function for preventing metal diffusion. A semiconductor device characterized by the above-mentioned. 3. The device according to claim 2, wherein at least one of said first and second insulating films is a silicon nitride film, a silicon carbide film, an aluminum nitride film, an aluminum oxide or a boron nitride film. Semiconductor device. 4. The semiconductor device according to claim 1, further comprising a multilayer wiring on said second semiconductor substrate, wherein at least one of said multilayer wirings is made of copper wiring. . 5. A semiconductor device having a step of forming, in the thickness direction, a substrate divided into a first semiconductor layer, at least one of first and second insulating films, and a second semiconductor layer. Wherein at least one of the first and second insulating films is a silicon nitride film formed by implanting nitrogen ions into the substrate and then subjecting the substrate to a heat treatment. A method for manufacturing a semiconductor device. 6. A semiconductor comprising, in a thickness direction, a step of forming a substrate divided into a first semiconductor layer, at least one of first and second insulating films, and a second semiconductor layer. A method of manufacturing a device, wherein at least one of the first and second insulating films is a silicon nitride film deposited on the first semiconductor layer by a CVD method. Production method.