JP2002025269A - Semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device capable of preventing a useless charge / discharge current from repeatedly flowing to a bit line when the same data is repeatedly read from the same memory cell. SOLUTION: Memory cells 10 and 11, dummy cells 12 and 13 for generating a reference potential, bit lines BL (0),
Circuit 15 used for precharging ZBL (0), sense amplifier 14, bit line BL (0) and sense amplifier 1
And a bit line ZB
It includes a transistor Q8 that opens and closes between L (0) and the sense amplifier 14, and a control circuit 40 that controls the transistors Q7, Q8, and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device including a DRAM cell for embedding logic.

[0002]

2. Description of the Related Art Conventionally, DRAMs with embedded logic are used.
(Dynamic Random Access Memory) As a semiconductor device including cells, for example, a semiconductor device as shown in FIG. 5 is provided.

Each of the DRAM memory cells 100 to 103 included in the semiconductor device has a transistor Q1.
01 and a capacitor C101.
A charge corresponding to one bit of data is stored in the capacitor C101.
To store 1-bit data.

The transistor Q101 of the memory cell 100
Is connected to a word line WL (0).
The bit line BL (0) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 100 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The potential V _DD indicates a power supply potential applied to the drain of the transistor Q101 when storing high-level data in a memory cell. The same applies to each of the transistors described below. is there.

The transistor Q101 of the memory cell 101
Is connected to the word line WL (1).
A bit line ZBL (0) paired with the bit line BL (0) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 101 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The transistor Q101 of the memory cell 102
Is connected to a word line WL (2).
The bit line BL (1) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 102 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The transistor Q101 of the memory cell 103
Is connected to a word line WL (3).
A bit line ZBL (1) paired with the bit line BL (1) is connected to the drain of the transistor Q101. Further, one electrode of the capacitor C101 of the memory cell 103 is connected to the source of the transistor Q101. The other electrode of the capacitor C101 is maintained at the intermediate potential V _DD / 2.

The pair of bit lines BL (0), ZB (B) is located between bit line BL (0) and bit line ZBL (0).
An equalizing circuit 105 for precharging L (0) to the intermediate potential V _DD / 2 is formed. This equalizing circuit 105 includes three transistors Q102 to Q104.
It is constituted by. Transistors Q102 to Q1
A control line BLEQ (0) for turning on / off the equalizing circuit 105 is commonly connected to each of the gates 04. A wiring VBL (0) for supplying the intermediate potential V _DD / 2 is connected to the source or the drain of the transistors Q103 and Q104.

Similarly, each bit line BL (1) and bit line ZBL (1) is
(1) An equalizing circuit 106 for precharging ZBL (1) to the intermediate potential V _DD / 2 is formed.
This equalizing circuit 106 has three transistors Q10
5 to Q107. Transistor Q
A control line BLEQ (1) for turning on / off the equalizing circuit 106 is commonly connected to each gate of 105 to Q107. Transistors Q106, Q1
A wiring VBL (1) for supplying the intermediate potential V _DD / 2 is connected to the source or the drain of 07.

The sense amplifier 104 has a function of reading and outputting data from each memory cell forming one row of the memory cell array, and is connected to a pair of a signal line BLSA and a signal line ZBLSA.

The bit line BL is connected to one end of the signal line BLSA.
(0) is connected via a transistor Q108, and a bit line BL (1) is connected to the other end of the transistor Q1.
10 are connected. Further, a data input / output line IO is connected to the signal line BLSA via the transistor Q112.

On the other hand, a bit line ZBL (0) is connected to one end of the signal line ZBLSA via a transistor Q109, and a bit line ZBL (1) is connected to the other end via a transistor Q111. I have. In addition, an input / output line ZIO for data paired with the input / output line IO is connected to the signal line ZBLSA via the transistor Q113.

A control line CL (0) for turning on / off each of the transistors Q108 and Q109 is commonly connected to each gate of the transistors Q108 and Q109. On the other hand, a control line CL (1) for turning on / off each of the transistors Q110 and Q111 is commonly connected to each gate of the transistors Q110 and Q111. The gates of the transistors Q112 and Q113 are commonly connected to a column selection line CSL for turning on / off the transistors Q112 and Q113.

In the semiconductor device described above, for example, data is read from each memory cell forming one row of the memory cell array and output in accordance with the timing shown in FIG. FIG. 6 is a timing chart in the case where low-level data is stored in the memory cell 100 and this data is read from the memory cell 100 and output.

First, by setting the control lines CL (0) and CL (1) to high level and turning on the transistors Q108 to Q111, the bit lines BL (0) and ZBL (0) are turned on.
And the pair of bit lines BL (1) and ZBL (1) are connected to the sense amplifier 104 via the pair of signal lines BLSA and ZBLSA.

Next, control lines BLEQ (0), BLEQ
(1) is set to a high level to equalize circuits 105 and 10
6 is turned on, the bit lines BL (0), ZB
L (0) pair and bit lines BL (1), ZBL
The pair (1) is precharged to the intermediate potential V _DD / 2.
Thereafter, the control line CL (1) is set to the low level to turn off the transistors Q110 and Q111, so that the pair of the bit lines BL (1) and ZBL (1) is connected to the sense amplifier 1
Block from 04.

Further, by turning the control line BLEQ (0) to low level and turning off the equalizing circuit 105, the pair of bit lines BL (0) and ZBL (0) is brought into a floating state. Note that the control line BLEQ (1) is still kept at the high level, and the equalizing circuit 10
6 are in the ON state, the bit lines BL (1),
Precharging of the pair of ZBL (1) is continued.

Next, by setting the word line WL (0) to high level and turning on the transistor Q101 of the memory cell 100, the capacitor C1 of the memory cell 100 is turned on.
The charge stored in 01 moves to the bit line BL (0) and slightly changes the potential of the bit line BL (0) from the intermediate potential V _DD / 2. For example, when low-level data is stored in the memory cell 100, the bit line BL
The potential of (0) drops slightly from V _DD / 2. Since the transistor Q101 of the memory cell 101 is off, the potential of the bit line ZBL (0) is kept at V _DD / 2.

Further, when the sense amplifier 104 is turned on, the sense amplifier 104 is connected to the bit line ZBL.
The bit line BL (0) is set while setting the potential of (0) as the reference potential.
A small change in the potential is detected (sensed) and differentially amplified.
Further, the amplified potential is applied to the bit lines BL (0) and ZBL.
Apply to (0). Thus, for example, when low-level data is stored in the memory cell 100, the potential of the bit line BL (0) decreases to the low-level ground potential 0V, while the potential of the bit line ZBL (0) decreases. Rises to the high-level power supply potential V _DD .

When the column selection line CSL is set to the high level to turn on the transistors Q112 and Q113, the data read from the memory cell 100 is output to the peripheral circuit through the input / output lines IO and ZIO.

[0022]

By the way, in a DRAM, when data is read from a memory cell, the data stored in the memory cell is destroyed, so that the charge transferred from the capacitor of the memory cell to the bit line is lost. It is necessary to rewrite data in the memory cell by amplifying the data by the sense amplifier and supplying (refreshing) the same to the same capacitor. Therefore, it is necessary to amplify the potential of the bit line connected to the memory cell from which data has been read to a value that can sufficiently refresh the memory cell.

In a conventional semiconductor device including a DRAM, as shown in FIG. 6, for example, when low-level data is stored in a memory cell 100, a sense amplifier 104 causes a bit line BL (0) to be sensed. Is lowered to the ground potential 0 V, and the potential of the bit line ZBL (0) is raised to the power supply potential V _DDV .

However, in an image control buffer memory or the like using such a semiconductor device, the same data is repeatedly read from the same memory cell in many cases. Until such a case, a large load capacitance can be obtained by resetting the bit line connected to the memory cell to the intermediate potential V _DD / 2 or repeating the operation of differentially amplifying the potential of the bit line on the reference potential side. However, there is a problem that a useless charge / discharge current repeatedly flows through the bit line having the above.

An object of the present invention is to provide a semiconductor device capable of preventing a useless charge / discharge current from repeatedly flowing through a bit line when the same data is repeatedly read from the same memory cell.

[0026]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention forms a memory cell array and includes a first memory cell for storing supplied data, and a first memory cell. A second memory cell for generating a reference potential used when reading data from the memory cell; a first word line connected to the first memory cell; and a second memory cell connected to the second memory cell. Word line, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, and a first and a second bit line. A precharge means for precharging a pair of two bit lines to a potential on the same side as the level of data previously read from the first memory cell;
Differentially amplifies the signal applied to the first terminal and the signal applied to the second terminal to read data stored in the first memory cell and apply a differential output to each terminal. A sense amplifier, first switch means for opening and closing between a first bit line and a first terminal of the sense amplifier, and opening and closing between a second bit line and a second terminal of the sense amplifier. A second switch means for performing the operation; a control means for activating the first and second word lines and controlling the precharge means and the first and second switch means.

In the above invention, the potential on the same side as the level of the data previously read from the first memory cell is set to
The first and second bit lines are precharged. next,
When the control means activates the first word line, data is read from the first memory cell to the first bit line. Therefore, when the same data is read out as before, the potential of the first bit line hardly changes.

On the other hand, when the control means activates the second word line, the potential held by the second memory cell is applied to the second bit line. At this time, the potential of the second bit line slightly fluctuates from the precharged potential. However, since the first and second switch means are independently controlled by the control means, even if the potential of the first bit line is amplified for the purpose of refreshing the memory cell, the second bit line, ie, The potential of the bit line on the reference potential side is not unnecessarily amplified. Therefore, even when the semiconductor device of the present invention is applied to an image control buffer memory or the like, when the same data is repeatedly read from the same memory cell, unnecessary charge / discharge current can be prevented from repeatedly flowing through the bit line, and the operation can be prevented. The current at the time can be dramatically reduced.

In the above invention, the first memory cell includes the first capacitor for retaining data,
It is preferable that the second memory cell includes a second capacitor for holding a reference potential, the second capacitor having a smaller capacitance than the first capacitor. In this case, a potential difference that can be detected by the sense amplifier can be reliably generated between the first bit line and the second bit line.

In the above invention, the control means may open the first and second switch means after a lapse of a predetermined time from the start of the operation of the sense amplifier, and may close the first switch means after a lapse of the predetermined time. preferable. In this case, since the bit line having a large load capacity is cut off from the operating sense amplifier, the speed of the data read operation in the memory cell can be increased.

In the above invention, the control means includes:
The setting may be such that the second switch means is opened after a predetermined time has elapsed from the start of the operation of the sense amplifier. The semiconductor device may include a DRAM, and the sense amplifier may use a shared sense amplifier system.

[0032]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing a part of a semiconductor device including a DRAM cell for logic embedding. In FIG. 1, two memory cells for forming a memory cell array and storing supplied data and two memories for generating reference potentials used for reading data from these memory cells, respectively. A cell (hereinafter, referred to as a dummy cell), a sense amplifier for reading and outputting data stored in a memory cell, and the like are shown.

As shown in FIG. 1, the memory cells 10, 11
Is composed of an N-channel MOS transistor Q1 and a capacitor C1, and stores 1-bit data by storing a charge corresponding to 1-bit data in the capacitor C1.

The word line WL (0) is connected to the gate of the transistor Q1 of the memory cell 10. Also,
The bit line BL is connected to the drain of the transistor Q1.
(0) is connected. Further, the transistor Q
One electrode of the capacitor C1 of the memory cell 10 is connected to one source. The other electrode of the capacitor C1 is maintained at the intermediate potential V _DD / 2.

The potential V _DD indicates the power supply potential applied to the drain of the transistor Q1 when storing high-level data in the memory cell.
The same applies to each of the channel MOS transistors.

The word line WL (1) is connected to the gate of the transistor Q1 of the memory cell 11. Also,
The bit line BL is connected to the drain of the transistor Q1.
The bit line ZBL (0) paired with (0) is connected. Further, one electrode of the capacitor C1 of the memory cell 11 is connected to the source of the transistor Q1. As in the case of the memory cell 10, the other electrode of the capacitor C1 is also maintained at the intermediate potential V _DD / 2.

The dummy cell 12 generates a reference potential for reading and outputting data from a memory cell (for example, the memory cell 10) connected to the bit line BL (0). This dummy cell 12 is connected at node N1 to bit line ZBL (0), and at node N2 to bit line BL (0). Dummy cell 12 has a dummy word line D at node N3.
It is connected to WL and to a precharge control line PC at a node N4.

On the other hand, the dummy cell 13 is connected to the bit line ZBL
Memory cell connected to (0) (for example, memory cell 1
A reference potential for reading and outputting data from 1) is generated. This dummy cell 13 is connected to the bit line BL (0) at the node N1, and
2 is connected to the bit line ZBL (0). Further, the dummy cell 13 is connected to the dummy word line ZDWL at the node N3, and is connected to the precharge control line ZPC at the node N4.

As shown in FIG. 2, the dummy cells 12, 13 include three N-channel MOS transistors Q13 to Q1.
5, one P-channel MOS transistor Q16,
It is constituted by one capacitor C2. Here, referring to FIGS. 1 and 2, each dummy cell 12,
13 will be described.

The dummy word line DWL is connected to the gate of the transistor Q13 of the dummy cell 12. The bit line ZBL (0) is connected to the drain of the transistor Q13. Further, the source of the transistor Q13 is connected to one electrode of a capacitor C2 whose capacitance is smaller than that of the capacitor C1 (in this embodiment, half of the capacitor C1).
The other electrode of the capacitor C2 is connected to the intermediate potential V _DD / 2
It is kept in.

The gate of the transistor Q14 of the dummy cell 12 is connected to a precharge control line PC for turning on / off the transistor Q14. The transistors Q15 and Q16 of the dummy cell 12
Is connected to the bit line BL (0). The source of the transistor Q15 is kept at the low level ground potential 0V, and the source of the transistor Q16 is kept at the high level power supply potential _VDD .

On the other hand, the transistor Q1 of the dummy cell 13
The gate of No. 3 is connected to a dummy word line ZDWL. The drain of the transistor Q13 has
The bit line BL (0) is connected. Further, one electrode of a capacitor C2 having the same capacity as the capacitor of the dummy cell 12 is connected to the source of the transistor Q13. The other electrode of the capacitor C2 is also maintained at the intermediate potential V _DD / 2.

A precharge control line ZPC for turning on / off the transistor Q14 is connected to the gate of the transistor Q14 of the dummy cell 13. The transistors Q15 and Q1 of the dummy cell 13
The bit line ZBL (0) is connected to each of the gates 6. The source of the transistor Q15 and the source of the transistor Q16 are also kept at the low level ground potential 0V and the high level power supply potential _VDD , respectively.

Description will be made again with reference to FIG. Word lines WL (0), WL (1) and dummy word lines DWL,
ZDWL is connected to row decoder 20. The column selection line CSL is connected to the column decoder 30.
These decoders are controlled by the control circuit 40,
The control means is formed as a whole.

Between the bit line BL (0) and the bit line ZBL (0) forming a pair, three transistors Q2 to Q
4 form an equalizing circuit 15. This equalizing circuit 15 includes an inverter 16 and
Together with the transistor Q6 and the transistor Q17, a precharge circuit for a pair of the bit lines BL (0) and ZBL (0) is formed.

The equalizing circuit 15 is turned on / off by the control circuit 40 at each gate of the transistors Q2 to Q4.
A control line BLEQ for turning off is commonly connected. A bit line BL (0) is connected via an inverter 16 to each gate of the transistor Q6 and the transistor Q17. The source of the transistor Q6 is maintained at a low-level ground potential of 0 V, and the source of the transistor Q17 is maintained at a high-level power supply potential _VDD .

The sense amplifier 14 has a function of reading and outputting data from each memory cell forming one row of the memory cell array, and is connected to a pair of signal lines BLSA and ZBLSA. In the present embodiment, a shared sense amplifier system in which pairs formed by two bit lines are connected one by one to the left and right sides of the sense amplifier 14 is used.

That is, the bit line BL (0) is connected to one end of the signal line BLSA via the transistor Q7, and the bit line BL (1) is connected to the other end of the signal line BLSA.
Connected through. In addition, the signal line BLSA
A data input / output line IO is connected via a transistor Q11.

The control line CL (0) for turning on / off the transistor Q7 by the control circuit 40 is connected to the gate of the transistor Q7. Further, a control line CL (1) for turning on / off the transistor Q9 by the control circuit 40 is connected to the gate of the transistor Q9.

On the other hand, one end of the signal line ZBLSA is connected via a transistor Q8 to a bit line ZBL (0) paired with the bit line BL (0), and the other end is connected to the bit line BL (1). ) Is connected via a transistor Q10. The data input / output line ZIO is connected to the signal line ZBLSA via the transistor Q12.

The control line ZCL (0) for turning on / off the transistor Q8 by the control circuit 40 is connected to the gate of the transistor Q8. A control line ZCL for turning on / off the transistor Q10 by the control circuit 40 is provided at the gate of the transistor Q10.
(1) is connected.

The gates of the transistors Q11 and Q12 are connected to the transistors Q11 and Q12 by the column decoder 30.
A column selection line CSL for turning on / off Q12 is commonly connected.

When the same data is repeatedly read from the same memory cell, the semiconductor device described above operates according to the timing shown in FIG. FIG. 3 is a timing chart when high-level data is repeatedly read from the same memory cell. First, the control line CL
(0) and ZCL (0), and control lines CL (1) and ZC
By setting L (1) to high level, the transistors Q7 to Q10
Turn on. By this operation, bit lines BL (0), Z
BL (0) pairs and bit lines BL (1), ZBL
The pair (1) is connected to the sense amplifier 14 via a pair of signal lines BLSA and ZBLSA.

Since high-level data has been read from the memory cell 10 in the previous reading, the transistor Q15 of the dummy cell 12 is turned on and the transistor Q17 is turned on via the inverter 16. Note that memory cell 1
When data of low level is read from 0, the transistor Q16 of the dummy cell 12 is turned on and the transistor Q6 is turned on via the inverter 16.

Next, the control line BLEQ is set to the high level to turn on the equalizing circuit 15, and the precharge control line PC is set to the high level to turn on the transistor Q14 of the dummy cell 12. By these operations, the pair of bit lines BL (0) and ZBL (0) is set to the high-level potential V.
_While being precharged to _DD , low-level data is written to the capacitor C2 of the dummy cell 12. still,
In order to prevent unnecessary current from flowing in dummy cell 13 during these operations, precharge control line ZP
It is preferable to keep C at a low level.

After that, the control line BLEQ is set to low level to turn off the equalizing circuit 15, and the precharge control line PC is set to low level to turn off the transistor Q14 of the dummy cell 12. By these operations, the pair of bit lines BL (0) and ZBL (0) is brought into a floating state.

Next, the word line WL (0) is set to the high level to turn on the transistor Q1 of the memory cell 10. Therefore, as shown in FIG. 4A, the bit line BL (0)
Is maintained at the high-level potential (V _DD ) indicated by the broken line.
When low-level data is read to the bit line BL (0), the potential of the bit line BL (0) is a potential indicated by a dashed line slightly lower than the high-level potential (V _DD ). Down to

Further, the dummy word line DWL is set to the high level to turn on the transistor Q13 of the dummy cell 12. Therefore, as shown in FIG.
The potential of (0) drops to a potential indicated by a solid line slightly lower than the high-level potential (V _DD ). Specifically, since the capacitance of the capacitor C2 is half that of the capacitor C1,
The potential of the bit line ZBL (0) drops to a potential intermediate between the broken line and the alternate long and short dash line.

Therefore, the bit lines BL (0), ZBL
When the pair (0) is precharged to the high-level potential (V _DD ), regardless of whether the data read from the memory cell 10 is at the high level or the low level, the bit line BL (0) ) And the bit line ZBL (0) can reliably generate a potential difference that can be detected by the sense amplifier 14.

On the other hand, when repeatedly reading low-level data from the memory cell 10, as shown in FIG. 4B, the bit line BL (0) is kept at the low-level potential (0 V) indicated by the broken line. Dripping. When high-level data is read to the bit line BL (0), the bit line B
The potential of L (0) rises to a potential indicated by a dashed line slightly higher than the low-level potential (0 V).

Further, the potential of the bit line ZBL (0) rises to a potential indicated by a solid line slightly higher than the low level potential (0 V). Specifically, for the same reason as described above, the potential of the bit line ZBL (0) rises to a potential intermediate between the broken line and the dashed line. Therefore, also in this case, regardless of whether the data read from the memory cell 10 is at a high level or a low level, a sense amplifier is provided between the bit line BL (0) and the bit line ZBL (0). 14 can reliably generate a potential difference that can be detected.

Next, by turning on the sense amplifier 14, the sense amplifier 14 detects (senses) a minute change in the potential of the bit line BL (0) while using the potential of the bit line ZBL (0) as the reference potential. Perform differential amplification. After a predetermined time from the start of sensing by the sense amplifier 14, that is, after amplifying the potential of the bit line ZBL (0) to some extent, the control lines CL (0) and ZCL (0)
To a low level to turn off the transistors Q7 and Q8,
The pair of the bit line BL (0) and the bit line ZBL (0) is cut off from the sense amplifier 14.

As a result, after the potential of the bit line BL (0) is maintained at the high level potential and the potential of the bit line ZBL (0) is slightly amplified to the low level potential side, these bit lines are switched to the low level potential side. Floating state. On the other hand, since the signal line BLSA and the signal line ZBLSA are connected to the sense amplifier 14, the potential of the signal line BLSA is maintained at the high-level potential V _DD and the potential of the signal line ZBLSA is reduced to the low-level potential 0V. And the data to be output to the peripheral circuit is generated. Here, when the column selection line CSL is set to the high level to turn on the transistors Q11 and Q12, the high-level data read from the memory cell 10 is output to the peripheral circuit via the input / output lines IO and ZIO. .

As described above, in the semiconductor device according to the present embodiment, even if the same data is repeatedly read from the memory cell 10, the bit line connected to the memory cell from which the same data is repeatedly read is stored in the memory cell 10. Side potential. Further, during the sensing by the sense amplifier, the control line ZCL (0) connected to the bit line on the reference potential side is set to low level, and this bit line ZBL (0) is cut off from the sense amplifier. For this reason, the bit line on the reference potential side fluctuates only slightly from the precharged potential, and consequently hardly fluctuates from the precharged potential. Therefore, by applying the present embodiment to a buffer memory or the like for image control, when the same data is repeatedly read and output from the same memory cell, unnecessary charge / discharge current can be prevented from repeatedly flowing through the bit line, Operating current can be dramatically reduced.

Further, since the capacitance of the capacitor C2 is set to half of that of the capacitor C1, the bit line BL (0) is set regardless of whether the data read from the memory cell is at a high level or a low level. And bit line ZBL
During (0), a potential difference detectable by the sense amplifier 14 can be reliably generated.

Further, during sensing by the sense amplifier 14,
Bit lines BL (0), ZBL having large load capacitance
Since (0) is cut off from the sense amplifier 14, the speed of reading data from the memory cell can be increased.

In this embodiment, the memory cell 1
Since the control line CL (0) needs to be set to the high level in order to refresh 0, the control line CL (0) may be kept at the high level (the dashed line in FIG. 3). In this case, when reading low-level data from another memory cell connected to the bit line BL (0),
The potential (0) reaches the low-level potential 0 V earlier than in the present embodiment (the dashed line in FIG. 3). Bit line BL (0) having a large load capacitance during sensing is connected to sense amplifier 1
4, the same effect as in the present embodiment can be obtained except that the data reading speed is slightly lower than that in the present embodiment.

[0069]

As described above, according to the present invention,
When the same data is repeatedly read from the same memory cell, unnecessary charge / discharge current can be prevented from repeatedly flowing to the bit line.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a memory cell array of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a dummy cell of FIG. 1;

FIG. 3 is a timing chart showing an example of a timing of repeatedly reading and outputting high-level data from the same memory cell in the semiconductor device of FIG. 1;

4A and 4B are diagrams illustrating a change in potential of a bit line when electric charge of a capacitor included in a dummy cell of FIG. 1 moves to a bit line. FIG. 4A repeatedly reads high-level data from the same memory cell. (B) shows a case where low-level data is repeatedly read from the same memory cell.

FIG. 5 is a diagram showing a part of a memory cell array of a conventional semiconductor device.

FIG. 6 is a timing chart illustrating an example of a timing of reading and outputting data from a memory cell in the semiconductor device of FIG. 5;

[Explanation of symbols]

10, 11 memory cell 12, 13 dummy cell 14 sense amplifier 15 equalizing circuit 20 row decoder 30 column decoder 40 control circuit Q1-Q4, Q6-Q15 N-channel MOS transistor Q16, Q17 P-channel MOS transistor C1, C2 Capacitor WL (0) , WL (1) word lines DWL, ZDWL dummy word lines BL (0), ZBL (0), BL (1), ZBL (1)
Bit lines CL (0), ZCL (0), CL (1), ZCL (1)
Control line

Claims (6)

[Claims] 1. A first memory cell for forming a memory cell array and storing supplied data, and a second memory cell for generating a reference potential used when reading data from the first memory cell. A memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a first word line connected to the first memory cell. A second bit line connected to the second memory cell and paired with the first bit line; and a pair of the first and second bit lines connected to the first memory cell. And a precharge means for precharging to a potential on the same side as the level of the data previously read from the amplifier, and differentially amplifies the signal applied to the first terminal and the signal applied to the second terminal. Thereby, the first memory cell A sense amplifier for reading the data stored in the memory and applying a differential output to each terminal; and a first switch for opening and closing the first bit line and the first terminal of the sense amplifier. Second switch means for opening and closing between the second bit line and a second terminal of the sense amplifier; and activating the first and second word lines and the precharge means. And a control means for controlling the first and second switch means. 2. The first memory cell includes a first capacitor for holding data, and the second memory cell is a second capacitor for holding a reference potential. 2. The semiconductor device according to claim 1, further comprising a second capacitor having a smaller capacity than the first capacitor. 3. The control means opens the first and second switch means after a lapse of a predetermined time from the start of the operation of the sense amplifier, and closes the first switch means after a lapse of a predetermined time. 3. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein said control means opens said second switch means after a lapse of a predetermined time from the start of operation of said sense amplifier. 5. The semiconductor device according to claim 1, wherein said semiconductor device includes a dynamic random access memory (DRAM). 6. The semiconductor device according to claim 1, wherein said sense amplifier uses a shared sense amplifier system.