JP2002016494A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop(PLL) circuit capable of switching a frequency divider at high speed by providing a fractional frequency dividing circuit in simple configuration, setting a high reference frequency, further setting a wide noise suppression frequency width based on a PLL and shortening frequency switching time as well. SOLUTION: This circuit has an arithmetic means (CPU) 15 for previously calculating frequency divider control data 11 for providing a frequency dividing number corresponding to an output frequency and a frequency divider switching memory circuit 2 for writing the frequency divider control data 11 and controlling a variable frequency divider 1 by reading a frequency dividing value 10 each time an output 9 of the variable frequency divider 1 is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit suitable for constructing a frequency synthesizer capable of obtaining an output frequency having a finer frequency resolution than a reference frequency by using fractional frequency division. The present invention relates to a phase locked loop circuit.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a conventional phase locked loop (PLL) loop circuit. As shown in FIG. 8, the output of the voltage controlled oscillator 27 is frequency-divided by the variable frequency divider 21, the output is compared with the reference signal 25 by the phase comparator 24, and the output is passed through the LPF 26 to the voltage controlled oscillator 27.
To form a phase locked loop circuit connected to the frequency control input 34 of FIG. In the fractional frequency division, the average frequency division number = N + L / A is obtained by using some variable frequency divisions. The frequency division switching calculation circuit 31 calculates the frequency value to be set next from the variable frequency divider output 29, and controls the variable frequency divider 21 through the frequency division switching control circuit 22 after the calculation is completed.

In the case of such fractional frequency division control, the calculation algorithm is a modulation method for increasing the frequency band (noise shaping) of noise generated by switching the frequency division value of the frequency divider, for example, ΣΔ (sigma delta). A modulator or the like is used. As a specific example of a ΣΔ (sigma delta) modulator,
Third-order MASH type ΣΔ (Sigma Delta) as shown in FIG.
A modulator is listed in Akira Yukawa, "Oversampling A / D Conversion Technology", published by Nikkei BP. Also, PLL
An example in which a ΣΔ (sigma-delta) modulator is used as a synthesizer is disclosed in the technology disclosed in Japanese Patent Application Laid-Open No. Hei 4-212522.

[0004]

However, in the conventional phase locked loop circuit, every time the variable frequency divider output 29 is generated, the next fractional frequency division value is calculated according to an algorithm by a calculation circuit (hardware) or software calculation. , A certain calculation time is required, and this algorithm uses a cascade connection type like the MASH type ΣΔ (sigma delta) modulation, so that the calculation time becomes long. Further, the calculation circuit (hardware) for this calculation is also a complicated circuit. Further, in such a circuit configuration, it takes a certain time to switch the frequency divider, and the reference frequency becomes low. There are also problems such as a narrow noise suppression frequency width in the phase locked loop and a long frequency switching time.

The present invention has been made in view of the above-mentioned problems, and realizes a fractional frequency dividing circuit with a simple circuit, can switch a frequency divider at a high speed, and can set a high reference frequency. It is another object of the present invention to provide a phase locked loop circuit in which the noise suppression frequency width by the phase locked loop can be set wide and the frequency switching time can be shortened.

[0006]

According to the present invention, there is provided a phase locked loop circuit for performing a fractional frequency division by switching a frequency dividing ratio of a variable frequency divider. A variable frequency divider that can vary the frequency division ratio by a frequency divider control signal,
Calculating means for calculating frequency divider control data in advance to obtain a frequency division number corresponding to the output frequency, and writing the frequency divider control data, and reading out the data every time an output of the variable frequency divider is generated A frequency divider switching memory circuit for setting a frequency division value of the variable frequency divider, a phase comparator for comparing the output of the variable frequency divider with a reference frequency, and an output of the phase comparator. LPF to remove high frequency components
(Low-pass filter) and the voltage-controlled oscillator capable of changing the oscillation frequency by the output of the LPF (low-pass filter).

Further, in the phase locked loop circuit according to the first aspect, the variable frequency divider switches a frequency division ratio to thereby obtain an average frequency division number (N + L / A) (N, L, and A are integers). (Claim 2).

Further, in the phase locked loop circuit according to claim 1 or 2, the arithmetic means comprises: ΣΔ (sigma.
The frequency dividing value is calculated in advance by a calculation algorithm based on (delta) modulation (claim 3).

Further, in the phase locked loop circuit according to any one of claims 1 to 3, the divider switching memory circuit writes the divider control data into a memory and counts the divider output by a counter. And the read address of the memory, the read data is transmitted to the variable frequency divider,
A frequency division value is set (claim 4).

Further, in the phase locked loop circuit according to any one of claims 1 to 3, the memory includes a plurality of memory blocks, and stores a plurality of the frequency divider control data having different frequencies for each frequency. The frequency can be switched by switching a memory block for writing to and reading from the different memory block (claim 5).

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a phase locked loop circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a phase locked loop circuit according to the present invention.

FIG. 1 shows a phase locked loop circuit according to the present invention.
As shown in the figure, the frequency division ratio of the output 8 of the voltage controlled oscillator 7 is N
The fractional frequency division is performed by the variable frequency divider 1 which can be varied as -1, N, N + 1,.... The fractional frequency division uses several variable frequency divisions to obtain an average frequency division number = N + L / A.

The phase-locked loop circuit according to the present invention provides a frequency divider control data 1 for obtaining a frequency division number corresponding to an output frequency.
Arithmetic means (CPU) 15 for calculating in advance 1 and frequency divider control data 11 are written, and the output 9 of variable frequency divider 1 is output.
Each time occurs, a frequency divider switching memory circuit 2 that reads the frequency division value 10 and controls the variable frequency divider 1 is provided.

Also, a phase comparator 4 for comparing the phase of the output 9 of the variable frequency divider 1 with the reference frequency 5, and an LPF (low-pass filter) which receives the output 13 and removes high-frequency components.
6 and a voltage-controlled oscillator 7 whose oscillation frequency can be changed by an output 14 of an LPF (low-pass filter).

Next, the frequency divider switching memory circuit 2 and the calculation means (CPU) 15 which are the features of the present invention will be described in detail with reference to specific first and second embodiments.

(Embodiment 1) FIG. 2 shows a variable frequency divider 1, a frequency divider switching memory circuit 2, and an arithmetic means (CP
It is a block diagram of U) 15. Fractional frequency division (N + L / A)
When trying to obtain (N, L and A are integers), the arithmetic means (CPU) 15 operates according to the following procedure.

(1) The integers L and A are replaced with, for example, M shown in FIG.
The calculation is performed once according to a calculation algorithm such as a signal diagram of an ASH type ΣΔ (sigma delta) modulator, and a value obtained by adding the calculation result and N is written to the first memory address in the memory 202. (2) Subsequently, the second calculation is performed, and the value obtained by adding the calculation result and N is written to the second memory address in the memory 202. (3) Similarly, the third calculation is performed, and the value obtained by adding the calculation result and N is written to the third memory address in the memory 202. Thereafter, similarly, the value obtained by adding the calculation result and N to the M-th memory address is written to the M-th memory address in the memory 202.
The M-th value of M is a value of the number of times that the calculation result is circulated.

Next, the number of outputs from the output 9 of the variable frequency divider 1 is counted by the counter 201, and the counted number is used as a read address of the memory 202 (when the count number is M and the first address is used). Return). Finally, the frequency division value 10 of the variable frequency divider 1 is set by the data read from the frequency divider switching memory circuit 2. CPU1
5 to the memory 202 and the memory 2
Switching from 02 to readout to the variable frequency divider 1 is performed by the data selector 203.

It is to be noted that instead of writing to the memory each time, M
After the calculations are completed, the calculation results may be collectively transferred to the memory and written.

(Embodiment 2) FIG. 3 shows a variable frequency divider 1, a frequency divider switching memory circuit 2, and arithmetic means (CP
It is a block diagram of U) 15. The memory is composed of two memory blocks 202a and 202b. First, fractional frequency division (Nl + Ll / Al) (Nl, L
From the state of l and Al are integers), next, fractional frequency division (N2 +
When trying to obtain (L2 / A2) (N2, L2 and A2 are integers), the arithmetic means (CPU) 15 operates according to the following procedure.

(1) First, fractional division (Nl + Ll / A
Calculate the divided data corresponding to 1), and
Write to 02a. (2) Next, frequency-divided data corresponding to fractional frequency division (N2 + L2 / A2) is calculated and written to the memory block 202b. (3) First, a circuit is set to read the memory block 202a. (4) When changing the frequency to the next frequency division, the circuit is set to read the memory block 202b.

The above example is an example of switching between two fractional frequency division values. If data is written in a plurality of memory blocks and the readout block is sequentially switched, the fractional value is continuously obtained. The division value can be changed.

As described above, in the present invention, since the frequency divider can be switched at a high speed, the frequency band of noise can be widened as shown in FIG. The principle of noise suppression of the output of a voltage controlled oscillator by noise shaping (broadbanding) in this phase locked loop will be described. As shown in FIG. 5, a phase locked loop performs loop control so as to be the same as a reference signal. It is. For this reason, if the fractional frequency-divided output for generating the spurious is phase-synchronized with the reference signal, spurious signals having opposite phases are generated in the voltage controlled oscillator.
Then, as shown in FIG. 6, the spurious generated by the fractional frequency division is subjected to noise shaping to broaden the noise in the vicinity of the divided output, and the vicinity of the divided output without noise is phase-synchronized with the reference signal. Can be removed.

[0024]

As described above in detail, the phase locked loop circuit according to the present invention does not require a time and a circuit for calculating the next division setting value each time a divided output is output. Since the fractional frequency dividing circuit can be realized by a simple circuit (only for reading out the frequency dividing value data), high-speed operation is possible. Further, since the frequency divider can be switched at high speed, the frequency band due to noise shaving can be widened. Therefore, the reference frequency can be set higher. further,
The noise suppression frequency width by the phase locked loop (PLL) loop can be set wide, and the frequency switching time can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to the present invention.

FIG. 2 is a block diagram of a variable frequency divider, a frequency divider switching memory circuit, and an arithmetic unit (CPU) according to the first embodiment.

FIG. 3 is a block diagram of a variable frequency divider, a frequency divider switching memory circuit, and an arithmetic unit (CPU) according to a second embodiment.

FIG. 4 is a schematic graph for explaining how to broaden noise by speeding up frequency division value switching.

FIG. 5 is a diagram for explaining the principle of noise suppression of the output of a voltage controlled oscillator by noise shaping (band broadening) in a phase locked loop.

FIG. 6 is a waveform diagram illustrating noise shaping.

FIG. 7 is a signal diagram of a third-order MASH type ΣΔ (sigma delta) modulator.

FIG. 8 is a block diagram of a conventional phase locked loop circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 variable frequency divider 2 frequency divider switching memory circuit 4 phase comparator 5 reference frequency 6 LPF 7 voltage controlled oscillator 8 voltage controlled oscillator output 9 variable frequency divider output 10 divided value 11 frequency divider control data 13 phase Output of comparator 14 Output of LPF 15 Operation means (CPU) 201 Counter 202a Memory block 202b Memory block 202 Memory 203 Data selector

Claims (5)

[Claims] In a phase-locked loop circuit for performing fractional frequency division by switching a frequency division ratio of a variable frequency divider, an output of a voltage controlled oscillator is changed by a variable frequency divider capable of varying a frequency division ratio by a frequency divider control signal. A frequency divider, arithmetic means for calculating frequency divider control data for obtaining a frequency division number corresponding to an output frequency in advance, and writing the frequency divider control data, each time an output of the variable frequency divider is generated. A frequency divider switching memory circuit for reading data and setting a frequency division value of the variable frequency divider; a phase comparator for comparing a phase of an output of the variable frequency divider with a reference frequency; L that inputs the output of
A phase-locked loop circuit comprising: a PF (low-pass filter); and the voltage-controlled oscillator capable of changing an oscillation frequency by an output of the LPF (low-pass filter). 2. The phase-locked loop circuit according to claim 1, wherein the variable frequency divider switches a frequency division ratio to obtain an average frequency division number (N + L / A) (N, L, and A are integers).
A phase-locked loop circuit characterized in that: 3. The phase-locked loop circuit according to claim 1, wherein said calculating means calculates a divided value in advance by a calculation algorithm based on ΣΔ (sigma-delta) modulation. Loop circuit. 4. The phase-locked loop circuit according to claim 1, wherein the divider switching memory circuit writes the divider control data in a memory, and counts a divider output by a counter. A phase-locked loop circuit for setting a frequency division value by setting the frequency as a read address of the memory and transmitting the read data to the variable frequency divider. 5. The phase-locked loop circuit according to claim 1, wherein said memory includes a plurality of memory blocks, and stores a plurality of said frequency divider control data having different frequencies for each frequency. A phase locked loop circuit configured to switch a frequency by switching a memory block for writing to and reading from the different memory block.