JP2002016138A - Method of forming via stud and line semiconductor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interconnection with an improved electromigration life. SOLUTION: The formation method of a via stud comprises a) a process for preparing a substrate 10 with at least an attached first level metal 22, wherein the first level metal is provided inside a first insulator 25, b) a process for attaching a layer of a second insulator 35, c) a process for etching a second insulator by etchant for forming a relevance level, wherein the relevance level has at least one line opening 33 and at least one via opening 34, each opening has a side wall and a bottom part, and a first level metal and a part of a first insulator at a lower side of a via opening are exposed by etching, d) a process for etching a part of the exposed first insulator, and e) a process for attaching a liner 51.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and, more particularly, to submicron sized semiconductor devices having high conductivity conductors insulated by low dielectric constant dielectrics. It relates to the structure of high performance interconnects.

[0002]

2. Description of the Related Art Improved performance in semiconductor integrated circuits (ICs) is achieved by reducing loss rates. The loss rate is directly related to the inductance, capacitance, and resistance of the interconnect. Recently, by replacing conventional aluminum-based metals with high-conductivity copper metals, line resistance has been reduced and by using interconnect methods involving multi-level interconnects separated by insulator layers, Inductance has been reduced. However, the increased wiring densities of interlayer insulators and today's high-density circuits increase capacitance, and as a result, interconnect capacitance is a major degrading factor in device performance.

[0003] One way to suggest capacitance is
The purpose is to reduce the dielectric constant (k) of the insulator separating the conductive lines. Since "air" is known to have the lowest dielectric constant (k = 1), organic or inorganic materials containing large amounts of trapped air have been developed. One such material is a porous organic silicate glass. Accordingly, an interconnect made of copper-based metal and a porous insulator are desired.

[0004] One of the limitations of copper-based metals is that a barrier layer (typically one or more layers of refractory metal) is required to provide adhesion and corrosion protection to the copper conductor.
In multilevel interconnects, electrons must pass through this barrier layer as they flow from one level interconnect to another.

[0005] High current densities cause mass transport to conductor lines (a phenomenon known as electromigration).
It is known to form voids in conductor lines to form electrical open circuits. Abrupt changes in mass transport rates (divergence of atomic flux) have been shown to be a major cause of electromigration. Thus, the presence of the barrier metal within the interconnect of the high conductivity metal causes a sudden divergence of the atomic flux and the formation of voids. This is shown in FIG. FIG. 1 is a cross-sectional view of a multi-level interconnect of the state of the art. The n-th level interconnect line M1 (1) is formed by the damascene method, and the (n + 1) -th level interconnect line M2 (3) and the bias stud V1 (2) are connected to a double (dual) damascene. Formed by the method. The interconnect lines and bias studs have barrier layers on the sides and bottom of the conductor lines and studs. As shown, the bias stud V1
, Must flow through the refractory metal barrier layer at the bottom of the bias stud V1. The low diffusivity of copper atoms in the barrier layer metal causes a sharp decrease in the atomic flux density just below the barrier layer at the bottom of the bias stud V1, as shown in FIG.
Eventually, voids 4 are formed.

The use of a porous insulator causes an electrical open circuit at the interface between the bias stud layer V1 and the interconnect line M1 at the same time. The electrical open circuit is interconnect line M
1 is a result of the mechanical separation of the bias stud V1 from the interconnect line M1 caused by the weak mechanical integrity of the surrounding insulator allowing the physical movement of the bias stud V1 to 1. Relative physical movement is the result of expansion and contraction during the heat stroke.

[0007] Thus, despite some inventions of methods and structures, the problem of electrically open circuits in ICs remains, and a method must be sought for its solution.

[0008]

SUMMARY OF THE INVENTION In view of the problems and deficiencies of the prior art, it is an object of the present invention to provide an interconnect having improved electrical performance of a semiconductor IC.

It is another object of the present invention to provide an interconnect having an improved electromigration lifetime.

It is still another object of the present invention to provide an interconnect having a redundant path for current flowing bypassing voids formed by electromigration.

Yet another object of the present invention is to provide an interconnect having an increased surface area for contact between a conductor line and a bias stud.

It is yet another object of the present invention to provide an interconnect having increased mechanical integrity between a bias stud and a metal line.

[0013]

SUMMARY OF THE INVENTION The above and other objects (which will be apparent to those skilled in the art) are provided by the present invention relating to high conductivity metal interconnects having improved electromigration lifetimes. Especially achieved with copper. In one aspect, the present invention provides a semiconductor IC chip having a copper line and bias stud interconnect. The copper line has a barrier layer on its sides and bottom, and the bias stud is a coaxial barrier such that there is no barrier layer between the bias stud and the conductor line above or below the barrier layer. It has a layer partially. The interconnect first defines a bias stud that overlaps the contact interconnect line on at least one side,
This is then achieved by etching the insulating film and forming a previous level interconnect line therein.

In a related aspect, the present invention is directed to a method of forming a copper interconnect having improved electromigration lifetime using a dual damascene method. The method includes a first level interconnect line (M1) that is substantially planar with a first level surrounding dielectric.
Depositing a second insulating film, lithographically defining a first level bias stud pattern (V1), partially etching the insulating film layer, removing the resist, Lithographically defining a two-level interconnect pattern and etching the dielectric layer. In this case, the first level insulating film adjacent to interconnect line M1 is also etched due to the overlapping bias stud pattern. Following this cavity formation, a barrier metal is deposited, followed by electrodeposition of copper and chemical mechanical polishing. The metal in the deep cavity formed adjacent to interconnect line M1 has an electromigration void formed by interconnect line M just below bias stud V1.
When formed in one, it provides a redundant path for current flow.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment will be described with reference to FIGS. In these figures, the same reference numbers indicate the same elements of the invention.

FIG. 3 shows a sectional view of a conventional silicon semiconductor structure. In the figure, all the semiconductor devices and
Contact studs that contact these semiconductor devices and are included in the substrate 10 and contacts not formed on the relevant level are not shown. Also, as shown in FIG. 3, a portion of the first level high conductivity metal interconnect line pattern (M1) 20 is fabricated using a prior art single damascene method. Interconnect line 20
Consists of a barrier layer 21 and a copper interconnect line 22,
The top surface of line 22 is substantially coplanar with surrounding dielectric 25. As shown in FIG. 4, the current technique for dual damascene is implemented to deposit a thin layer 31 of silicon nitride and a thin layer 35 of an interlevel dielectric layer. The material of the interlevel dielectric layer can be organic or inorganic, but preferably has a low dielectric constant. Next, the dielectric 35
Above, a bias stud pattern is photolithographically defined, followed by a suitable etchant, preferably reactive ion etching (RI), as shown in FIG.
A step of partially etching the dielectric 35 using E) is performed. Next, the pattern for the second level interconnect lines is photolithographically defined and the interlevel oxide 35 is further etched to form trenches 33 and holes 34. This etching is performed on the nitride layer 3
1 is completely removed by etching until the metal line 22 is exposed. Figure 5 shows the final form of the current technology.
Shown in In FIG. 5, the bias stud pattern (V1)
And a trench 33 corresponding to the second level interconnect line pattern (M2) are formed in the interlevel dielectric layer. By first defining a second metal interconnect pattern and partially etching the dielectric 35 and then defining a bias stud and etching the dielectrics 35 and 31, It should be noted that the sequence of pattern definition can be reversed. In either method, the partial etching step is adjusted so that the depth of the trenches 33 and holes 34 correspond to the desired interconnect metal line thickness and bias stud height, respectively.

In the present invention, intentionally, the V1 via opening exposes the M1 metal and the level 1 insulator. Preferably, the V1 via opening has at most about 80% M
Exposing one metal and about 20% of the insulator.

In the present invention, the combined bias studs are etched into the insulator layers 31, 35 to expose the metal, preferably copper, at the portion of the first level interconnect line 22. As shown in FIG. 5, the first level insulator 25 surrounding the M1 metal is etched. The first level insulator etch is continued for an approximate depth equal to the thickness of the M1 metal. The overlapping structure of the via studs V1 makes it possible to form a cavity in the insulator 25 adjacent to the metal M1. Preferably, the etching is an oxide etching.

The remaining steps of the double damascene process are resumed, and a barrier layer 51 is sputter deposited, and then an electroplated copper layer 52 is deposited as shown in FIG. Fill 34,36. Next, any excess metal is removed from the unpatterned regions, preferably by chemical mechanical polishing. FIG. 7 shows a cross-sectional view of two different levels of metal lines 20 and 50 connected by a bias stud 70 and an etched insulator 75 of the present invention after polishing. FIG.
Shows a perspective view of the bias stud 70 of the present invention connecting the M1 level 20 with the M2 level 50. It should be noted that the process of the present invention can be performed on two adjacent levels of a semiconductor IC. FIG. 8 shows a void 80 that forms slowly over time or that forms during a stress test. If the thickness of the barrier layer, which is arranged transverse to the direction of electron flow, is less than 100 °, it is shown that back stresses caused by atoms accumulating on the barrier walls are canceled out and no electromigration voids are formed. Have been.
Accordingly, since the thickness of the barrier layer 21 of the interconnect line M1 and / or the barrier layer 51 of the bias stud V1 can be intentionally made smaller than 100 °, no void is formed in the trench metal 75. Thus, regardless of the formation of the electromigration voids 80, the bias stud structure of the present invention provides a continuous path for electron flow. In this example, in the presence of void 80, electrons flow a short distance through barrier layer 21, causing void 8
Bypass 0.

The method of the present invention forms a novel interconnect structure. This structure has been described previously, as shown in FIG. Plan views showing the differences between the current structure and the structure of the present invention are shown in FIGS. The present invention is shown in FIG. 10, where the level shown is the M1 level. In the present invention, an area surrounded by a via connecting the M1 level to the M2 level is indicated by A. FIG. 11 showing the current technology also shows the M1 level. The via connecting the M1 level to the M2 level surrounds the area indicated by B. Although this example illustrates a variation of the terminal end via connection to M1, the method and structure of the present invention can be used to connect any level of via to any portion of the previous metal level. . The inventors also contemplate a process where relevant levels of lines and vias are formed separately. In this case, the method of the present invention can be applied, and the formation of the relevant level lines can be performed after the previous level of insulator etching has been performed.

Although the invention has been described with respect to particular embodiments, given the teachings and explanations herein,
Many variations and modifications will be apparent to those skilled in the art. For example, it can be seen that the copper metal of the preferred embodiment can be replaced with any metal using a barrier layer. Also, the dielectric can be any solid or porous low dielectric constant material. Further, although the example given here is for a double damascene method, it is equally applicable to a single damascene method for forming interconnect lines and bias studs. Furthermore, the present invention is intended to cover all modifications and changes that fall within the scope of the appended claims.

In summary, the following matters are disclosed regarding the configuration of the present invention. (1) A method of forming a bias stud, comprising: a) providing a substrate having at least a first level metal deposited thereon, wherein the first level metal is provided in a first insulator; b) depositing a layer of a second insulator; c) etching the second insulator with an etchant to form an associated level, wherein the associated level comprises at least one line Opening and at least one
Having one via opening, each opening having a sidewall and a bottom, wherein the etching exposes the first level metal and a portion of the first insulator below the via opening. D) etching a portion of said exposed first insulator; and e) attaching a liner. (2) The method of (1) above, wherein the thickness of the liner is at most about 100 °. (3) The method according to (1), wherein the etched portion of the first insulator is substantially equal to a width of the via opening. (4) The method according to (1), wherein the etching in the step c is an oxide etching. (5) The method according to (4), wherein the etching in the step c is continued until at least a part of the exposed first insulator is etched. (6) The method according to (1), wherein the second insulator is an organic or inorganic material. (7) The method according to (6), wherein the second insulator is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and organic silicate glass. (8) The method according to (6), wherein the second insulator has a dielectric constant smaller than 3.0. (9) The method according to (6), wherein the second insulator is chemically porous. (10) The method according to (6), wherein the second insulator has a breaking strength close to zero. (11) The method according to the above (1), further comprising a step of filling the line opening with a metal. (12) The method according to (11), wherein the metal is copper. (13) The method according to (12), wherein the liner is selected from the group consisting of tantalum, titanium, tungsten, tantalum nitride, titanium nitride, and tungsten nitride. (14) comprising a substrate having at least two levels of metal, wherein the first level of metal has a first level having at least one first level line portion, the first level line portion comprising: A second level is provided within the first insulator, the second level including at least one second level line portion having a sidewall and a bottom, and one via portion having a sidewall and a bottom. 2, the via portion connects the first-level line portion and the second-level line portion, and a part of the via portion is connected to the first-level line portion. A line semiconductor structure provided between the first insulator and a liner lining a sidewall and a bottom of a second-level line portion and a sidewall and a bottom of the via portion. (15) The via portion includes a part of the first insulator,
The line semiconductor structure according to (14), wherein the line semiconductor structure is replaced. (16) The above (14), wherein at least one of the first and second insulators is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and organic silicate glass. 2. The line semiconductor structure according to 1. (17) The line semiconductor structure according to (16), wherein the first and second insulators are made of the same material. (18) The line semiconductor structure according to (13), wherein the first-level line portion, the second-level line portion, and the via portion are made of metal. (19) The line semiconductor structure according to (18), wherein the metal is copper. (20) comprising a liner layer below the first level line portion, the liner layer being in contact with the via portion;
The line semiconductor structure according to the above (19). (21) The line semiconductor structure according to (20), wherein the liner layer is selected from the group consisting of tantalum, titanium, tungsten, tantalum nitride, titanium nitride, and tungsten nitride.

[Brief description of the drawings]

FIG. 1 is a simplified cross-sectional view of a state-of-the-art interconnect showing portions of first and second level interconnect metals that connect to each other via a bias stud.

FIG. 2 is a cross-sectional view, similar to FIG. 1, of an interconnect failing an electromigration stress test.

FIG. 3 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, illustrating a starting stage of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, showing a starting stage of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, illustrating a starting stage of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor substrate formed to a first level metal interconnect by a process of the state of the art, illustrating a starting stage of the present invention.

FIG. 7 is a cross-sectional view of the interconnect of the present invention.

FIG. 8 is a cross-sectional view of the interconnect of FIG. 7 with electromigration voids formed during a stress test.

FIG. 9 is a perspective view showing a portion of a state of the art bias stud structure providing a redundant current path.

FIG. 10 is a plan view of a bias stud and a metal line according to the present invention.

FIG. 11 is a plan view of bias studs and metal lines of the current technology.

[Explanation of symbols]

 10 Substrate 20 First Level Interconnect Line Pattern 21 Barrier Layer 22 Copper Interconnect Line 25 Dielectric 31 Thin Layer of Silicon Nitride 33 Trench 34 Hole 35 Thin Layer of Dielectric Layer 36 Cavity 50 Second Level Interconnect Line・ Pattern 51 Barrier layer 52 Copper layer 70 Biastard 75 Groove metal 80 Void

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Houma Dire M Dalal United States 12540 Lagrangeville Very Road, New York 94 (72) Inventor Valendra Agharwala United States 12533 Hopewell Junction Saddle Ridge Drive 56, New York 56 (72) Inventor Terence Kane United States 12590 Wappingers Falls Bowdoin Lane, New York 26 (72) Inventor Paul S. McLaughlin United States 12601 Poughkeepsie David Drive 103, New York 103 (72) Inventor Du New Yen United States 06810 Danbury Hickory Street 15 Connecticut 72) Depart Richard Proctor United States 12533 Hopewell Junction Broke Drive, New York 9 (72) Inventor Hazara Es Lasoar United States 12582 Stormville Judith Drive, New York 27 (72) Inventor Yun-You Wong United States 12570 Powkweig Cipher, New York Lane 34 F-term (reference) 4K024 AA09 AB01 BA15 BB12 DA07 FA06 5F033 HH11 HH18 HH19 HH21 HH32 HH33 HH34 JJ01 JJ11 JJ18 JJ19 JJ21 JJ32 JJ33 JJ34 KK11 KK18 KK19 KK21 Q13 KK13 MM13 NN12 QQ48 RR01 RR04 RR06 RR21 RR25 RR29 TT04 WW02 WW09 XX00 XX09 XX24

Claims (21)

[Claims] 1. A method for forming a bias stud, comprising: a) providing a substrate having at least a first level metal deposited thereon, wherein the first level metal is provided in a first insulator. B) depositing a layer of a second insulator; c) etching the second insulator with an etchant to form an associated level, wherein the associated level is at least one. One line opening and at least one
Having one via opening, each opening having a sidewall and a bottom, wherein the etching exposes the first level metal and a portion of the first insulator below the via opening. D) etching a portion of said exposed first insulator; and e) attaching a liner. 2. The thickness of said liner is at most about 100 °.
The method of claim 1, wherein 3. The method of claim 1, wherein the etched portion of the first insulator is approximately equal to a width of the via opening. 4. The method according to claim 1, wherein the etching in the step c is an oxide etching. 5. The method of claim 4, wherein the etching in step c is continued until at least a portion of the exposed first insulator is etched. 6. The method according to claim 1, wherein said second insulator is an organic or inorganic material. 7. The method according to claim 6, wherein said second insulator is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and an organic silicate glass. 8. The method of claim 6, wherein said second insulator has a dielectric constant less than 3.0. 9. The method of claim 6, wherein said second insulator is chemically porous. 10. The method of claim 6, wherein said second insulator has a breakdown strength near zero. 11. The method of claim 1, further comprising the step of filling said line openings with metal. 12. The method according to claim 11, wherein said metal is copper. 13. The method of claim 12, wherein said liner is selected from the group consisting of tantalum, titanium, tungsten, tantalum nitride, titanium nitride, and tungsten nitride. 14. A semiconductor device comprising a substrate having at least two levels of metal, the first level of metal having a first level having at least one first level line portion.
The level line portion is provided in the first insulator and has a side wall, and the second level is at least one second level line portion having a side wall and a bottom portion and one having a side wall and a bottom portion. A via portion in a second insulator, wherein the via portion connects the first level line portion and the second level line portion, and a part of the via portion is connected to the second level line portion. A line semiconductor structure provided between a first-level line portion and the first insulator, wherein a liner lines a sidewall and a bottom portion of a second-level line portion and a sidewall and a bottom portion of the via portion. 15. The line semiconductor structure according to claim 14, wherein said via portion replaces a part of said first insulator. 16. The semiconductor device according to claim 1, wherein at least one of said first and second insulators is selected from the group consisting of silicon oxide, silicon nitride, a composite of a silicon oxide layer and a silicon nitride layer, and an organic silicate glass. 15. The line semiconductor structure according to 14. 17. The line semiconductor structure according to claim 16, wherein said first and second insulators are made of the same material. 18. The method according to claim 18, wherein the first level line portion and the second level line portion are connected to each other.
14. The line semiconductor structure according to claim 13, wherein the level line portion and the via portion are made of metal. 19. The line semiconductor structure according to claim 18, wherein said metal is copper. 20. The line semiconductor structure of claim 19, further comprising a liner layer below said first level line portion, said liner layer being in contact with said via portion. 21. The line semiconductor structure according to claim 20, wherein said liner layer is selected from the group consisting of tantalum, titanium, tungsten, tantalum nitride, titanium nitride, and tungsten nitride.