JP2002010505A - Charge control device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent malfunction when a clock is cut, and to improve safety and quality of a charging operation. SOLUTION: A charge control means 2 logically controls charging of a secondary battery B. The clock loss detecting means 3 detects a clock loss of the clock input to the charging control means 2 and generates a detection signal when the clock loss occurs. The charge stopping means 4 stops charging based on the detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge control device, and more particularly to a charge control device for controlling charging of a secondary battery.

[0002]

2. Description of the Related Art A secondary battery (storage battery) is a battery whose function is regenerated by being charged after being discharged. Large secondary batteries are widely used as power supplies for power equipment, emergency and standby power supplies, and small secondary batteries are widely used as power supplies for cordless communication devices.

[0003] Among secondary battery types, lithium ion batteries are widely used in portable electronic devices because they can be reduced in size and weight. On the other hand, in recent years, microcomputer control is mainstream, and it is general that a charge control unit or the like that controls charging of a secondary battery is logically controlled.

[0004]

The charge control section of the secondary battery is composed of a logic circuit, but there has been a problem that no countermeasure has been taken against the case where the clock is stopped.

Therefore, when a clock interruption occurs, the charge control logic is also stopped, and normal charging cannot be performed thereafter. In addition, if a voltage is applied in an improper state due to a malfunction when the clock is cut off, especially in the case of a lithium ion battery, there is a possibility of the worst explosion.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a charge control device which prevents malfunctions when a clock is cut off and improves safety and quality of a charge operation. I do.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a charge control device 1 for controlling the charging of a secondary battery as shown in FIG. And a clock disconnection detecting means for detecting a clock disconnection of a clock input to the charge control means and generating a detection signal when the clock disconnection occurs.
And a charge stopping means 4 for stopping charging based on the detection signal.

Here, the charging control means 2 logically controls charging of the secondary battery B. The clock loss detecting means 3 detects a clock loss of the clock input to the charging control means 2 and generates a detection signal when the clock loss occurs.
The charge stopping means 4 stops charging based on the detection signal.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of the charge control device of the present invention. The charging control device 1 controls charging of the secondary battery B.

The charge control means 2 is a digital circuit for logically (logically) controlling the charge of the secondary battery B. The clock loss detecting means 3 detects a clock loss of the clock input to the charging control means 2 and generates a detection signal when the clock loss occurs.

The charge stopping means 4 stops charging when the detection signal is enabled. That is, the charge control unit 2 is instructed to stop charging. The clock supply monitoring means 5 stops charging when the clock is unstablely supplied during charging, and starts charging when the clock is supplied stably. For example, even if the clock recovers after the clock is cut off, the charge control unit 2 is instructed to maintain the charge stop state so that charging is not started until the clock is supplied stably. After that, after the clock is stably supplied, the charge control unit 2 is instructed to start charging.

As described above, the charging control device 1 of the present invention
When the clock stops, charging is interrupted. This makes it possible to ensure safety.
In addition, when the clock starts to operate again, the charging operation is not restored by the unstable supply of the clock, and the charging operation is resumed after it is recognized that the clock is supplied stably. As a result, malfunction can be prevented, and quality can be improved.

The charge control means 2 stops charging based on an instruction from the charge stopping means 4 or the clock supply monitoring means 5 when the clock is cut off or the clock is unstablely supplied, and flows to the secondary battery B. The current path is opened (current does not flow to the secondary battery B). As a result, there is no possibility that a voltage is applied to the secondary battery B in an inappropriate operation state, so that there is no danger of explosion, etc.
It is possible to ensure safety.

Next, a specific configuration realizing the charge control device 1 of the present invention will be described. FIG. 2 is a diagram illustrating a configuration of the charge control device. The charge control device 1a is a device that charges, for example, a lithium ion battery as a secondary battery, and is applicable to a case where one or two or more lithium ion batteries are connected in series.

The charge control device 1a includes a charge path block 10 through which a charge current flows, an analog circuit block 2 for measurement.
0, a control sequence circuit block 30 for a microcomputer or the like
Consists of

The charging path block 10 regulates the voltage source 101 for supplying the charging power supply voltage 102, the sense resistor 103 inserted for measuring the charging current 109, the backflow prevention diode 104, the charging current 109 and the voltage 110. And a battery pack 106 charged by the present device.

The voltage source 101 generally has AC / DC, DC /
It is a switching power supply such as DC. Power supply voltage for charging 1
02 is generally 5 to 6 V in the case of one lithium ion battery. The sense resistor 103 is a resistor for replacing the charging current value with a voltage value dropped by the resistor so that the measurement analog circuit block 20 can read the value.

The backflow prevention diode 104 is connected to the voltage source 10
This is to prevent the output voltage from dropping and the current from flowing back from the secondary battery 107 side when 1 is not working properly.

The Pch-MOSFET 105 is fed back by a dedicated circuit (charge current / voltage control gate modulation circuit 203) described later in the analog circuit block 20 for measurement so that the charging current 109 or the battery voltage 110 becomes a constant level. , Its gate voltage is adjusted.

The battery pack 106 includes a secondary battery 107, a protection circuit 108 for preventing overcurrent and overvoltage from being applied to the battery, and a thermistor 111 for monitoring battery temperature. These are indispensable for safety for lithium ion batteries which may explode if improperly charged.

In this example, the charge current and the battery voltage control P
Both the ch-MOSFET 105 and the sense resistor 103
Although it is on the power supply side with respect to the battery, either one or both may be arranged on the ground side. In addition, Pch-MO
When the SFET is arranged on the ground side, it is generally set to Nch.

The backflow prevention diode 104 drops 0.4 to 0.7 V as a forward voltage when charging, and the allowable heat loss is severe, or the output voltage 102 of the voltage source 101 is restricted. In order to reduce this voltage drop, a Pch-MOSF connected by setting the source to the lower potential side (lower side in the figure) instead of the diode is used.
Use ET112. Then, it is turned on when charging, and turned off otherwise. Backflow can be prevented by the body diode of the Pch-MOSFET 112.

The measuring analog circuit block 20 includes a power-on reset circuit 200, a charging power supply voltage monitoring circuit 2,
01, charging current monitoring circuit 202, charging current / voltage control gate modulation circuit 203, battery voltage monitoring circuit 204, battery temperature / battery mounting monitoring circuit 205, clock disconnection monitoring circuit 2
06.

The charging power supply voltage monitoring circuit 201 determines whether or not the charging power supply voltage 102 output from the voltage source 101 is an appropriate value for performing proper charging. If this voltage value is too low or too high, a signal 211 for interrupting charging is issued.
To the control sequence circuit block 30. This monitoring circuit generally includes a comparator and a reference voltage circuit.

The charging current monitoring circuit 202 includes a sense resistor 1
03, the power supply voltage 102 for charging, the sense resistor 103 and the backflow prevention diode 1
The node 121 during the period 04 is input. The charging current monitoring circuit 202 converts the differential input of the voltage drop value into a charging current level voltage 221 with respect to the ground.

The current flowing from the node 121 to the charging current monitoring circuit 202 is as small as several tens μA or less.
Since the charging current of several tens mA to several A can be neglected, the current value detected by the sense resistor 103 and the actual charging current are regarded as equal. A circuit for converting the differential voltage input to the ground voltage can be constituted by an operational amplifier described later with reference to FIG.

Gate modulation circuit 20 for charging current / voltage control
3 is a Pch-MOSF for performing constant current charging or constant voltage charging according to a charging sequence described later.
The potential of the output terminal 231 connected to the gate of the ET 105 is adjusted.

Charge current / voltage control gate modulation circuit 20
Reference numeral 3 denotes an operational amplifier that inputs a node 110 for measuring a battery voltage, a charging current level voltage 221 and an internal reference voltage.

The battery voltage monitoring circuit 204 performs pre-charging, rapid charging, and recharging according to the battery voltage.
10 is measured, and the state is transmitted to the control sequence circuit block 30 (output signal 241). The current entering the analog circuit block 20 for measurement from the node 110 is as small as several tens of μA, and can be ignored for a charging current of several tens mA to several A.

The battery temperature / battery mounting monitoring circuit 205 is connected to the thermistor 111 contained in the battery pack 106, and generally monitors the temperature of the battery by measuring the impedance of the thermistor having a large negative temperature coefficient. Then, charging is continued only when the temperature is within an appropriate temperature range.
Further, since the battery pack 106 is generally removable, when the battery pack 106 is not present, charging is not performed. When the impedance of the thermistor 111 is in an open state, it is determined that the battery pack 106 is not mounted. To stop charging. Then, the signal 251 indicating the temperature level and the presence or absence of the battery is sent to the control sequence circuit block 3.
Passed to 0. The clock disconnection monitoring circuit 206 will be described later.

On the other hand, the control sequence circuit block 30
Performs a charge control operation based on a signal input from the analog circuit block for measurement 20. For each terminal, I
Reference numeral 1 denotes a terminal to which a charging voltage abnormality detection signal is input, and I2 denotes a charging current level of 0.1 C or less (1 C is an ideal current value from one hour to empty battery in one hour). , A terminal for inputting a signal indicative of a reset signal, I3 is a reset terminal, O1
Is a terminal for outputting a signal for setting the charging current to 1 C / 0.1 C, and O2 is a terminal for outputting a signal for interrupting the charging current.

I4 is a terminal to which a signal (<3.0V, <3.9V, <24.5V) indicating the battery voltage level is input, and I5 is a signal to indicate the temperature level and the presence or absence of the battery. A terminal, I6 is a terminal to which a detection signal indicating a clock interruption is inputted, and I7 is a terminal to which a clock is inputted.

Next, a configuration example of the charging current monitoring circuit 202 will be described. FIG. 3 is a diagram illustrating a configuration example of the charging current monitoring circuit 202. The figure shows a circuit for converting a differential voltage input to a ground voltage.

In the circuit configuration, one of the resistors R3 and R6 is connected to the positive input terminal of the operational amplifier Amp, and one of the resistors R4 and R6 is connected to the negative input terminal. Resistance R
The other of R3 and R4 is connected to the input terminal, and the other of resistor R5 is connected to GND. The output of the operational amplifier Amp is a resistor R6
The other is connected.

Next, a configuration example of the charging current / voltage control gate modulation circuit 203 will be described. FIG. 4 is a diagram showing a configuration example of the charging current / voltage control gate modulation circuit 203. The connection relationship between the elements is such that the charging current level voltage is applied to the minus input terminal of the operational amplifier OP1, and the reference voltage is applied to the plus terminal. The battery voltage is applied to the minus input terminal of the operational amplifier OP2, and the reference voltage is applied to the plus terminal. One of the resistors R7 and R9 is pulled up, and the other of the resistors R7 is connected to the gate of the transistor P3 and the drain of the transistor N1. The other end of the resistor R9 is connected to the source of the transistor P3, and a charging current flows from the drain.

The output terminal of the operational amplifier OP1 is connected to the gate of the transistor N1, and the output terminal of the operational amplifier OP2 is connected to the gate of the transistor N2. The source of the transistor N1 is connected to the drain of the transistor N2,
The source of the transistor N2 is connected to one of the resistors R8,
The other end of the resistor R8 is connected to GND.

Here, the Pch-MOS through which the charging current flows
The transistor P3 of the FET is the transistor 105 of FIG.
Corresponding to The gate bias of the transistor P3 is determined by the voltage generated by the product of the resistor R9 and the current ID flowing therethrough. The current ID is determined by the transistors N1 and N2 to which the output voltages of the operational amplifiers OP1 and OP2 are applied as gate voltages.
Is determined by the drain current.

Since the transistors N1 and N2 are connected in series, the drain current is restricted by the smaller value of the two. Therefore, when the battery voltage is equal to or lower than the reference voltage, the output potential of the operational amplifier OP2 increases, and the conductivity of the transistor N2 increases, so that the current ID is restricted by the transistor N1, and as a result, the charging current is constant in accordance with the reference voltage. Current charging. After the ionization voltage reaches the reference voltage, the current ID is constrained by the transistor N2, resulting in constant voltage charging.

Next, the normal charge control operation of the charge control device 1a will be described. 5 and 6 are flowcharts showing the charge control operation in a normal state. [S1] After the power is turned on, the power supply voltage is checked. If the charging voltage exceeds 4.5 V, go to step S2; otherwise, continue checking in step S1. [S2] It recognizes that the power-on has been completed, and checks the battery state. If the battery voltage exceeds 3.0 V, go to step S3, and if it is 3.0 V or less, go to step S10. [S3] It is determined that quick charging is possible, and the process proceeds to quick charging. In the fast charging, the battery voltage is set to a final voltage value of 4.2V.
, And then constant current charging with an output voltage of 4.2V.

The charging current at the time of constant current charging differs depending on the capacity of the battery, and a value of 1 C is generally used. Switching from constant-current charging to constant-voltage charging is automatically performed by the circuit shown in FIG. 4, and the logic circuit is not involved.

In the rapid charging, charging is continued until the charging current drops to 0.1C. At this time, the time and battery temperature are monitored to check for any abnormalities. [S4] Time monitoring is performed. If charging is not completed after 180 minutes, the process returns to step S2, and if not, the process proceeds to step S5. [S5] Temperature monitoring is performed. If the temperature is between 0 ° C. and 50 ° C., go to step S7; otherwise, go to step S7.
Go to 6. [S6] If the temperature exceeds 50 ° C. or falls below 0 ° C., charging is temporarily interrupted, and charging is resumed when the temperature returns to an appropriate range. [S7] The charging current is checked. Charge current <0.1C
If so, the process returns to step S8; otherwise, the process returns to step S3. [S8] The process proceeds to the completion of charging, and the charging current is cut off. [S9] Since the battery voltage decreases with time due to self-discharge or the like, the battery voltage is monitored. If it falls below 3.9V,
Returning to step S3, rapid charging is performed again. [S10] Preliminary charging is performed. The pre-charging is performed with a small current of 0.2 C or less, since there is a possibility that the battery has a defect and an explosion may occur if a large current is suddenly applied. Pre-charging is performed until the battery voltage exceeds 3.0 V, during which time
As in the case of quick charging, temperature monitoring and time monitoring are performed. [S11] Temperature monitoring is performed. Temperature from 0 ° C to 50 ° C
If it is within the range, the process proceeds to step S13, and if not, the process proceeds to step S12. [S12] If the temperature exceeds 50 ° C or 0 ° C
If the temperature falls below, the charging is temporarily suspended, and the charging is resumed when the temperature returns to the appropriate range. [S13] If the battery voltage is greater than 3.0 V, the process returns to step S3; otherwise, the process proceeds to step S14. [S14] Time monitoring is performed. If the charging is not completed even after 60 minutes have elapsed, the process returns to step S15; otherwise, the process returns to step S10. [S15] It is determined that the battery is defective.

FIG. 7 is a diagram showing a state of charging. The figure shows
This shows a state in which preliminary charging, constant current charging, constant voltage charging, and charging completion are performed as time passes. Note that the determination values of the charging voltage, the battery voltage, the charging current, the temperature, the time, and the like shown here are examples.

Next, the charge control operation of the charge control device 1a when an abnormality occurs will be described. FIG. 8 is a flowchart showing a charge control operation when an abnormality occurs. [S20] If the charging voltage is greater than 6.0 V, step S31
Otherwise, go to step S21. [S21] If the battery voltage is greater than 4.5V, step S31 is executed.
Otherwise, go to step S22. [S22] If no battery is installed, step S31
If it is, go to step S23. [S23] If the battery voltage is less than 3.0 V, step S24.
Otherwise, go to step S25. [S24] Preliminary charging is performed. [S25] If the charging voltage is less than 3.0 V, step S31
Otherwise, go to step S26. [S26] If the clock is cut off, the process returns to step S27; otherwise, the process returns to step S20. [S27] Recognizing the clock interruption, the charging is stopped. [S28] If the clock has returned, step S29
Otherwise, return to step S27. [S29] Generate an interval until the clock is supplied stably. [S30] After the elapse of the interval, charging is restarted. [S31] Recognizing that a failure other than the clock interruption has occurred, charging is stopped. [S32] When the error condition disappears, the process proceeds to step S33.
Otherwise, the process returns to step S31. [S33] The charging is restarted.

Next, the clock interruption monitoring circuit 206 will be described in detail. The clock cutoff monitoring circuit 206 determines whether the clock for operating the control sequence circuit block 30 is normal, and immediately detects the detection signal 261 if stopped.
Is output to stop charging.

At this time, the detection signal 261 indicates the charging current
The signal is also input to the voltage control gate modulation circuit 203, and in response to this, the Pch-MOSFET 105 is turned off to open the current path.

FIG. 9 is a diagram showing an example of a circuit for detecting a clock stop. FIG. 10 is a diagram showing an operation timing chart. Regarding the connection relationship of each element, the clock CLK
Is input to the gate of the transistor (Pch-MOSFET) P1 and the input terminal of the inverter IC1. The source of the transistor P1 is pulled up, and the drain is connected to one of the capacitors C1, one of the resistors R1, and one of the input terminals of the AND element IC2. The other of the capacitor C1 and the other of the resistor R1 are connected to GND.

Transistor (Pch-MOSFET) P
The second gate is connected to the output terminal of the inverter IC1.
The source is pulled up, and the drain is connected to one of the capacitors C2, one of the resistors R2, and the other input terminal of the AND element IC2. The other of the capacitor C2 and the other of the resistor R2 are connected to GND. Then, the clock VCLK is output from the output terminal of the AND element IC2.

Here, when the clock CLK input is normal, both the transistor P1 directly connected to the clock CLK and the transistor P2 connected via the inverter IC1 repeatedly turn on and off.

The capacitors C are used for both the transistors P1 and P2.
1 and C2 and resistors R1 and R2 as loads, the capacitors C1 and C2 as shown in the timing chart.
2 is charging through a Pch-MOSFET and R1, R2
The discharge through is repeated.

Assuming that the cycle of the clock CLK is T, Pc
The on-resistance of the h-MOSFET is sufficiently smaller than R1 and R2, and the time constant determined by R1, R2 and C1, C2 is T
/ Pch-MOSFET
Assuming that the time constant determined by the on-resistance and C1 and C2 is sufficiently smaller than T / 2, V
1, V2 is obtained.

Here, the threshold voltage at the input of the AND element IC2 is 0.5 × Vcc. Clock CLK
Stops (fixed to 0V), the potential of V2 keeps decreasing,
It can be seen that VCLK becomes 0 V, and that clock disconnection has been detected.

In the present invention, there is no change in the normal charging sequence. However, after detecting the clock disconnection mode, charging is stopped, and after the clock is restored, an interval is set in consideration of a period in which the clock is stabilized. After that, the battery state is checked and charging is restarted.

FIG. 11 is a diagram showing a sequence circuit corresponding to a clock stop. The sequence circuit and the interval generation circuit are included in the control sequence circuit block 30. The sequence circuit performs a normal operation under a normal clock input. In addition, when the clock stops, operation becomes impossible, and the clock waveform may be distorted after the clock returns, so that time is required until the clock becomes stable.

The figure shows a part of the sequence circuit. The combinational circuit IC7 is a circuit that generates a new state based on the signal from the analog circuit block for measurement 20 and the current state and makes a transition.

Regarding the connection relationship of each element, four output signals of the combinational circuit IC7 are D-type flip-flop I
Input to the D terminals of C3 to IC6. The enable signals are input to the E terminals of the D-type flip-flops IC3 to IC6, the VCLK is input to the set terminal, the RESET signal is input to the reset terminal, and the clock CLK is input to the clock terminal. Then, a signal from the Q terminal is input to the combinational circuit IC7, and the current state is fed back.

Four D-type flip-flops IC3 to IC6 with set / reset are registers for holding states. Each output (Q0, Q1, Q2, Q3)
The state is determined by the bit string. For example, it is (0, 0, 0, 0) after reset.

When the clock is cut off, the operation of the D-type flip-flops IC3 to IC6 is stopped.
By inputting CLK to the set terminal and setting it to (1, 1, 1, 1), the state is shifted to the clock cutoff state.

FIG. 12 is a diagram showing an interval generation circuit. The interval generation circuit is a circuit for generating an interval until the clock is stably supplied after the clock is restored. The interval generation circuit includes toggle flip-flops IC8 to IC10,
And a D-type flip-flop IC11.

Regarding the connection relationship between the elements, VCLK is input to the reset terminals of the toggle flip-flops IC8 to IC10 and the D-type flip-flop IC11. The clock CLK is input to the clock terminal of the toggle flip-flop IC8, the inverted signal from the output terminal T1 of the toggle flip-flop IC8 is input to the clock terminal of the toggle flip-flop IC9, and the output terminal of the toggle flip-flop IC9. The inverted signal from T2 is a toggle
The clock signal is input to the clock terminal of the flip-flop IC10, and the inverted signal from the output terminal T3 of the toggle flip-flop IC10 is input to the clock terminal of the D-type flip-flop IC11.

The D-type flip-flop IC11
The terminal is pulled up, and an enable signal is output from the Q terminal. As described above, after the clock recovery, the number of clocks is counted by a ripple counter using a toggle flip-flop, and an interval is obtained.

FIG. 13 is a timing chart showing how the enable signal returns to H after the clock returns. After the enable signal goes high, the sequencer can exit from (1,1,1,1).

When the enable is L, the D-type flip-flops IC3 to IC6 on the right side of FIG. 11 continue to hold the previous state, and therefore cannot move to the next state. Although an example in which three toggle FFs are arranged is shown here, the interval time can be lengthened by increasing the number of the toggle FFs. Also, by using the ripple counter, even if a malfunction occurs due to clock waveform distortion, the count value is not significantly affected.

As described above, the charging control device of the present invention is provided with the means for detecting that the clock has stopped,
This detection signal is set to an input error state as an asynchronous signal with respect to the sequence logic that performs charge control, and the detection signal is used to mask the gate signal of the power transistor that controls the charging current and voltage to charge. The current was cut off.

As a result, when the clock is stopped, the charging current is surely interrupted, and the sequence logic is forcibly kept in the error state during the period when the clock is indefinite, so that a malfunction can be prevented.

In the above description, the secondary battery is a lithium ion battery, but is not limited to a lithium ion battery.
It is also applicable to nickel-based secondary batteries such as nickel-metal hydride.

[0066]

As described above, the charge control device of the present invention detects the clock loss of the clock input to the charge control means for charging the secondary battery, and when the clock loss is detected, the charging control device charges the battery. Is stopped. This allows
It is possible to prevent malfunction when the clock is cut off, and to improve safety and quality of the charging operation.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a charge control device of the present invention.

FIG. 2 is a diagram illustrating a configuration of a charge control device.

FIG. 3 is a diagram illustrating a configuration example of a charging current monitoring circuit.

FIG. 4 is a diagram showing a configuration example of a charging current / voltage control gate modulation circuit.

FIG. 5 is a flowchart showing a normal charge control operation.

FIG. 6 is a flowchart showing a normal charge control operation.

FIG. 7 is a diagram showing a state of charging.

FIG. 8 is a flowchart illustrating a charge control operation when an abnormality occurs.

FIG. 9 is a diagram illustrating an example of a circuit that detects a clock stop;

FIG. 10 is a diagram showing an operation timing chart.

FIG. 11 is a diagram showing a sequence circuit corresponding to a clock stop.

FIG. 12 is a diagram illustrating an interval generation circuit.

FIG. 13 is a timing chart showing how the enable signal returns to H after the clock returns.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Charge control device 2 Charge control means 3 Clock cutoff detection means 4 Charge stop means 5 Clock supply monitoring means B Secondary battery

Claims (3)

[Claims] 1. A charge control device for controlling charge of a secondary battery, comprising: charge control means for logically controlling the charge of the secondary battery; and detecting a clock interruption of a clock input to the charge control means. A charging control device comprising: a clock disconnection detecting unit that generates a detection signal when the clock disconnection occurs; and a charging stop unit that stops charging based on the detection signal. 2. The charge control device according to claim 1, further comprising clock supply monitoring means for stopping charging when said clock is unstablely supplied and charging when said clock is stably supplied. 3. The charging control means stops charging based on an instruction from the charging stopping means or the clock supply monitoring means when the clock is cut off or when the clock is unstablely supplied, and supplies the secondary battery with the charge. 3. The charge control device according to claim 2, wherein the flowing current path is opened.