JP2002009747A - Reference clock controller - Google Patents

Abstract

(57) [Problem] To provide a reference clock control device that performs automatic control of a reference clock with a simple hardware configuration without burdening a central processing unit. SOLUTION: When a PCR extracting unit 901 first extracts a time reference value from a data stream, the value is converted to a PC value.
As the R value, the PCR (t) register 902 and the STC
It is set in the counter 904. The STC counter starts counting the reference clock from the reference clock oscillator 907 using the set PCR value as a start value. Thereafter, every time the PCR extraction unit extracts the time reference value, the value of the STC counter at that time is set in the STC (t) register 903 as the STC value. Comparator 1
At step 08, the magnitude of the PCR value and the STC value are compared, and a predetermined value is output from the PWM register 109 according to the result. The PWM control unit 105 generates a PWM register value by cumulatively adding values from the PWM register,
Controls the oscillation frequency of the reference clock oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference clock control device, and more specifically, to a data clock in which a time reference value is inserted at predetermined intervals, and a time count signal synchronized with the data stream. For generating a reference clock control device.

[0002]

2. Description of the Related Art In an apparatus for receiving a data stream including a time reference value PCR, a synchronization count for synchronizing a reception operation with an input data stream is determined based on a reference clock generated in the apparatus. Done. By the way, for example, the frequency of an MPEG data stream is 27 MHz, but it is actually known that the frequency always slightly fluctuates around 27 MHz. The transmitting side inserts the time reference value PCR into the data stream so that such fluctuations can be recognized on the receiving side. The time reference value PCR is inserted into the data stream at a predetermined interval at the time of transmission, but is received with a slight deviation from a fixed interval due to the fluctuation of the data stream generated on the transmission side. In order for the decoding process or the like to be performed accurately, it is necessary to make the count value based on the reference clock generated inside the receiving device follow the sequentially received time reference value PCR. Therefore, a reference clock control device as described below has been conventionally proposed.

FIG. 7 is a block diagram showing an example of a conventional reference clock control device. The conventional reference clock control device 900 includes a PCR extraction unit 901, a PCR (t) register 902, an STC register 903, an STC counter 904, a PWM control unit 905, an interrupt output unit 906
, Reference clock oscillator 907, central processing unit 910
And switches 911 and 912.

Hereinafter, the operation of the reference clock control device 900 will be described with reference to FIG. PCR extraction unit 90
1 extracts a time reference value PCR (hereinafter referred to as a PCR value) from the input data stream,
It outputs the CR value to the PCR (t) register 902 and notifies the interrupt output unit 906 that the PCR value has been extracted. Accordingly, the PCR (t) register 902 stores
The PCR value output from the CR extraction unit 901 is held.
Further, the interrupt output unit 906 outputs an interrupt signal to the central processing unit 910. Further, the PCR extraction unit 901 outputs an enable signal to the switch 912 to control the opening and closing thereof.

[0005] The switch 911 is closed only when the PCR extraction unit 901 extracts the first time reference value PCR after the input of the data stream is started, and is open otherwise. The opening and closing of the switch 911 is performed by a control unit (not shown). When the switch 911 is closed, the first PCR value extracted by the PCR extraction unit 901 is set in the STC counter 904. When the first PCR value is set, the STC counter 904, which is a synchronous counter, starts an increment operation from the PCR value. The reference clock oscillator 907 is
A 27 MHz reference clock is supplied to the STC counter 904. The STC counter 904 performs an increment operation in synchronization with the reference clock. PCR extractor 9
01 outputs a logic signal “1” to the switch 912 as an enable signal every time the PCR value is extracted. The switch 912 is closed each time the logic signal “1” is output from the PCR extraction unit 901 as an enable signal. As a result, the STC (t) register 903 stores the P
Each time the CR extraction unit 901 extracts the PCR value, the count value of the STC counter 904 at that time (hereinafter, STC counter 904)
Value).

The central processing unit 910 includes an interrupt output unit 906
Outputs an interrupt signal from the PCR (t) register 9
02 and the PC held in the STC register 903
The R value and the STC value are read, and an operation represented by the following equation (1) is executed to obtain a PWM register set value.
The WM register setting value is output to the PWM control unit 905.
However, in the following equation (1), PCR (t) and ST
C (t) is a PCR value and an STC value output in real time, PCR (t-1) is a PCR value input immediately before PCR (t), and α is a predetermined constant value. It is. Note that the PCR (t-1) may be temporarily stored in a memory unit (not shown) included in the central processing unit 910. PMW register set value = register set value + {(PCR (t) -STC (t)) / (PCR (t) -PCR (t-1))} × α (1)

[0007] The PWM control section 905 generates a rectangular wave signal internally and outputs it to the reference clock oscillator 907.
The duty ratio of the rectangular wave signal output from the PWM control unit 905 (in the present specification, it means the ratio between the High section and the Low section of the signal) is changed at any time according to the PWM register setting value given from the central processing unit 910. Is done.

Although not shown, the reference clock oscillator 907 comprises a low-pass filter and a voltage controlled oscillator (VCO). The low-pass filter is P
The rectangular wave signal provided from the WM control unit 905 is smoothed to generate an average voltage. The voltage controlled oscillator receives an average voltage generated by the low-pass filter as a control voltage.

The PWM control unit 905 changes the duty ratio of the output rectangular wave signal based on the PWM register setting value obtained by the above equation (1).
When the duty ratio of the rectangular wave signal increases / decreases,
Accordingly, the frequency of the reference clock output from reference clock oscillator 907 goes up / down. Thereby, the STC counter 904 can perform synchronous counting based on the reference clock that follows the frequency fluctuation of the data stream.

[0010]

As described above, the conventional reference clock control device 900 causes the central processing unit 910 to execute the equation (1) by an interrupt operation every time a PCR value is extracted.
The reference clock is made to follow the frequency fluctuation of the data stream by giving the register value as the calculation result to the PWM control unit 905. The central processing unit 910 mainly performs control associated with decoding processing and the like. However, if an interrupt operation is frequently required to perform the above-described operation, an excessive processing load is imposed. As a result, there is a problem that the decoding process, which is the main operation of the central processing unit 910, is adversely affected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference clock control device which can realize automatic control of a reference clock with a simple hardware configuration without burdening a central processing unit.

[0012]

Means for Solving the Problems and Effects of the Invention The present invention has the following features to achieve the above object.

A first invention is a reference clock control device for receiving a data stream in which a time reference value is inserted at a predetermined interval and generating a time count signal following the data stream. A PCR extraction unit that extracts and outputs a reference reference value, a PCR value holding unit that holds the time reference value output by the PCR extraction unit as a PCR value, and a reference clock oscillator that generates a reference clock according to the oscillation frequency. An STC counter that starts a reference clock counting operation starting from the time reference value initially output by the PCR extraction unit, and a count of the STC counter at that time every time the PCR extraction unit extracts the time reference value. An STC value holding unit that fetches a value and holds the value as an STC value; S held in the STC value holding unit
A comparator for reading the TC value and comparing the magnitude relationship;
A plurality of values are set in advance, and a PWM register value changing unit that selects and outputs one value from the plurality of values according to a comparison result of the comparator, and a reference PWM register value is set in advance. A PWM control unit that cumulatively adds the values output from the PWM register value fluctuations with the reference PWM register value as a start value and controls the oscillation frequency of the reference clock oscillator based on the resulting cumulatively added value. And using the count value of the STC counter as a time count signal.

As described above, according to the first aspect of the present invention, the time synchronized with the data stream can be obtained without adding a simple hardware circuit such as a comparator and a PWM register value changing unit without relying on the CPU software processing. A count signal can be generated.

A second invention is an invention according to the first invention, wherein the PWM register value changing section includes a first value for increasing the cumulative value and a value for decreasing the cumulative value. Are set in advance, and a third value that does not change the current cumulative addition value is set in advance. The PWM register value changing unit stores the PCR value held in the PCR value holding unit.
When the value and the STC value held in the STC value holding unit do not match, one of the first and second values is selected and output, and when the value matches, the third value is selected and output. It is characterized by doing.

As described above, according to the second aspect, the PW
Three types of values are set in the M register value changing section, and an appropriate value is selected from these three types of values in accordance with the comparison result of the comparator and cumulatively added to the reference PWM register value. Therefore, the PWM register value can be changed by a simple comparison operation and a numerical value selection operation, and the configuration of the hardware circuit is simplified.

A third invention is a reference clock control device that receives a data stream in which a time reference value is inserted at a predetermined interval and generates a time count signal that follows the data stream. A PCR extraction unit that extracts and outputs a reference reference value, a PCR value holding unit that holds the time reference value output by the PCR extraction unit as a PCR value, and a reference clock oscillator that generates a reference clock according to the oscillation frequency. An STC counter that starts a reference clock counting operation starting from the time reference value initially output by the PCR extraction unit, and a count of the STC counter at that time every time the PCR extraction unit extracts the time reference value. An STC value holding unit that fetches a value and holds the value as an STC value; S held in the STC value holding unit
A first comparator for reading out the TC value and comparing the magnitude relation between the read value and the PCR value held in the PCR value holding unit;
A subtractor for obtaining the absolute value of the difference from the STC value held in the C value holding unit; a threshold value storage unit for holding a predetermined threshold value; a subtraction result of the subtractor and the threshold value stored in the threshold storage unit A second comparator for reading out the threshold value and comparing the magnitudes thereof, and a plurality of values set in advance, and the plurality of values are set in accordance with the comparison result of the first and second comparators. And a PWM register value changing unit that selects and outputs one value from among the above, and a reference PWM register value is set in advance.
A PWM control unit for cumulatively adding the value output from the PWM register value fluctuation with the WM register value as a start value and controlling the oscillation frequency of the reference clock oscillator based on the cumulatively added value as a result; It is characterized in that the count value is used as a time count signal.

As described above, according to the third aspect, the PC
In consideration of not only the magnitude relationship between the R value and the STC value but also the magnitude relationship between the difference absolute value and the threshold value, the variation of the value selection condition due to the fluctuation of the PWM register value is increased. Compared to the invention, more accurate synchronization control is possible.

A fourth invention is an invention according to the third invention, wherein when arbitrary positive values a and b have a relationship of a <b, the PWM register value changing section includes ,
Values a and b for increasing the cumulative addition value, values -a and -b for decreasing the cumulative addition value, and a value 0 that does not change the current cumulative addition value are set in advance. , The PWM register value changing unit is configured to determine whether the subtraction result of the subtractor is smaller than the threshold value stored in the threshold value storage unit, and the PCR value stored in the PCR value storage unit and the STC value storage unit. STC
When the value does not match, either the value a or -a is selected and output, and the subtraction result of the subtractor is larger than the threshold value stored in the threshold value storage unit,
And the PCR value and the STC held in the PCR value holding unit.
When the STC value held in the value holding unit does not match, either the value b or -b is selected and output, and the subtraction result of the subtractor is compared with the threshold value held in the threshold value storage unit. If the values match and the PCR value held in the PCR value holding unit does not match the STC value held in the STC value holding unit, one of the values a, -a, b or -b is selected. When the PCR value held in the PCR value holding unit matches the STC value held in the STC value holding unit, the value 0 is selected and output.

As described above, according to the fourth aspect, the PC
Since the sequence of selected values is changed depending on whether the absolute value of the difference between the R value and the STC value is larger or smaller than the threshold value, if the time lag of the reference clock with respect to the data stream is large, the reference clock Can be increased. Conversely, when the time lag is small, the frequency variation of the reference clock can be reduced. This allows the frequency of the reference clock to follow the data stream at a higher speed.

According to a fifth aspect of the present invention, there is provided a reference clock control device for receiving a data stream in which a time reference value is inserted at predetermined intervals and generating a time count signal following the data stream. A PCR extracting unit that extracts and outputs a reference reference value, a first PCR value holding unit that holds the time reference value output by the PCR extracting unit as a first PCR value, and a first PCR value holding unit. A second PCR value holding unit for holding the time reference reference value held immediately before the currently held time reference reference value as a second PCR value, and a reference clock for generating a reference clock corresponding to the oscillation frequency An oscillator, an STC counter for starting a reference clock counting operation starting from a time reference value first output by the PCR extraction unit,
Every time the CR extraction unit extracts the time reference value, the current count value of the STC counter is fetched and the first ST
An STC value holding unit that holds the C value, and a second STC value holding unit that holds the count value held immediately before the count value currently held in the first STC value holding unit as the second STC value A first PCR value held in the first PCR value holding unit and a first STC value held in the first STC value holding unit, and a first STC value for comparing the magnitude relationship between the read first PCR value and the first STC value held in the first STC value holding unit A first comparator for calculating an absolute value of a difference between the first PCR value held in the first PCR value holding unit and the first STC value held in the first STC value holding unit; A subtracter, a threshold value storage unit that holds a predetermined threshold value, and a threshold value storage unit that reads out the subtraction result of the first subtractor and the threshold value stored in the threshold value storage unit and compares the magnitude relations. 2
And a first PWM for selecting and outputting one value from the plurality of values according to the comparison result of the first and second comparators. A register value variation unit, and a second PCR value obtained by subtracting the second PCR value held in the second PCR value holding unit from the first PCR value held in the first PCR value holding unit to obtain ΔPCR And the third STC value obtained by subtracting the second STC value held in the second STC value holding unit from the first STC value held in the first STC value holding unit to obtain ΔSTC Subtracters and ΔPCR and ΔST from the second and third subtractors.
A third comparator for reading C and comparing the magnitude relation thereof, and a plurality of values are set in advance, and one of the plurality of values is set according to the comparison result of the third comparator. A second PWM register value changing unit to be selected and output, and a reference PWM register value are set in advance.
The value output from the second PWM register value changing unit is cumulatively added with the M register value as a start value, and the cumulative added value at the time when the comparison result of the third comparator is inverted is provisional PWM.
The value output from the first PWM register value change unit is simply added to the provisional PWM register value to obtain the PWM register value, and the oscillation frequency of the reference clock oscillator is controlled based on the PWM register value. P
And a WM control unit, wherein the count value of the STC counter is used as a time count signal.

According to the fifth invention as described above, first,
Provisional PW that minimizes the difference between ΔPCR and ΔSTC
Since the M register value is obtained, and thereafter the correction is performed so as to eliminate the difference between the first PCR value and the first STC value with the provisional PWM register value as the center, the difference between the data stream and the reference clock is obtained. It is not necessary to correct the generated fixed time lag, and the reference clock can follow the data stream at a higher speed.

A sixth aspect of the present invention is an invention according to the fifth aspect of the present invention, wherein when any positive values a and b have a relationship of a <b, the first PWM register value variation The part includes values a and b for increasing the cumulative addition value,
Values -a and -b for decreasing the cumulative addition value and a value 0 that does not change the current cumulative addition value are set in advance, and the first PWM register value variation unit includes a first PWM register value variation unit.
Is smaller than the threshold value stored in the threshold value storage unit and the first P
If the first PCR value held in the CR value holding unit does not match the first STC value held in the first STC value holding unit, either value a or -a is selected. And the subtraction result of the first subtractor is larger than the threshold value stored in the threshold value storage unit, and the first PCR value stored in the first PCR value storage unit.
Value and the first ST held in the first STC value holding unit.
If the C value does not match, either the value b or -b is selected and output, and the subtraction result of the first subtractor matches the threshold value held in the threshold value storage unit, and The first PCR value held in the first PCR value holding unit and the first PCR value held in the first STC value holding unit.
If the STC values do not match, any one of the values a, -a, b, and -b is selected and output, and the first PCR value held in the first PCR value holding unit and the first PCR value are output. When the first STC value held in the STC value holding unit of the first and second STCs matches, the value 0 is selected and output.

As described above, according to the sixth aspect, the first aspect
The sequence of values to be selected is changed according to whether the absolute value of the difference between the PCR value and the first STC value is larger or smaller than the threshold value, so that the time lag of the reference clock with respect to the data stream is large. In this case, the frequency change width of the reference clock can be increased. Conversely, when the time lag is small, the frequency change width of the reference clock can be reduced. This allows the frequency of the reference clock to follow the data stream at a higher speed.

A seventh invention is an invention according to the fifth or sixth invention, wherein the second PWM register value change section includes a first value for increasing the cumulative addition value, A second value for decreasing the added value and a third value that does not change the current accumulated added value are set in advance, and the second PWM register value changing unit includes ΔPCR and ΔS
When TC does not match, one of the first and second values is selected and output, and when TC matches, the third value is selected and output.

As described above, according to the seventh aspect, the PW
Three types of values are set in the M register value changing section, and an appropriate value is selected from these three types of values in accordance with the comparison result of the comparator and cumulatively added to the reference PWM register value. Therefore, the PWM register value can be changed by a simple comparison operation and a numerical value selection operation, and the configuration of the hardware circuit is simplified.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a configuration of a reference clock control device according to a first embodiment of the present invention. In FIG. 1, the reference clock control device 100 according to the present embodiment includes a PCR extraction unit 901
, A PCR (t) register 902, an STC (t) register 903, an STC counter 904, a reference clock oscillator 907, switches 911 and 912, a comparator 108, a PWM register value variation unit 109, and a PWM
And a control unit 105. Note that the same components as those of the conventional reference clock control device 900 have the same reference numerals, and a detailed description thereof will be omitted.

The data stream received by the PCR extracting unit 901 is sent in a packet format, and the header of each packet contains information indicating the type of actual data stored in the packet. PCR extractor 901
Recognizes whether or not the actual data included in each packet includes the time reference value PCR by referring to the header portion of each packet in the data stream, and includes the time reference value PCR. In this case, the time reference value PCR (hereinafter referred to as a PCR value) is extracted and output to the PCR (t) register 902. PCR
(T) The register 902 temporarily holds the given PCR value. The STC counter 904 inputs a PCR value first extracted from the data stream via the switch 911, and starts an increment operation with the first PCR value extracted as an initial value. Switch 912
Is closed each time a PCR value is extracted by the PCR extraction unit 901. As a result, the STC (t) register 903 stores
An STC counter value (hereinafter, referred to as an STC value) at each time when the PCR value is extracted is input via the switch 912 and is temporarily stored. The reference clock oscillator 907 is
A reference clock of 27 MHz is provided to the STC counter 904.

The comparator 108 stores the PCR (t) register 9
02 and the STC (t) register 903, the PCR value and the STC value are read and compared, and the increase enable signal SI and the decrease enable signal SD
To the PWM register value changing unit 109. As an output state of the increase enable signal SI or the decrease enable signal SD, for example, one of them may be at a high level and the other is at a low level, and both may be at a low level. The PWM register value changing unit 109 includes three types of values a and-as values for changing the PWM register value set in the PWM control unit 105.
a and 0 are held in advance, the value a is output when the increase enable signal is at a high level, and the value -a is output when the decrease enable signal SD is at a high level, and the increase enable signal SI and the decrease enable signal are output. When SD is at a low level, a value 0 is output. Note that the comparator 10
8 and the operation of the PWM register value changing unit 109 will be described later in detail.

The PWM control unit 105 internally generates a rectangular wave signal and outputs it to the reference clock oscillator 907.
Although not shown, the PWM control unit 105 includes an initial value register and a cumulative value register, and a predetermined reference PWM register value is fixedly set in advance in the initial value register. The PWM register value stored in the accumulation value register dynamically changes with the reference PWM register value set in the initial value register as a start value. That is, the accumulated value register is the PWM register value changing unit 10.
Every time a certain value (a, -a or 0) is given from 9, the given value is cumulatively added to the start value, thereby dynamically changing the PWM register value. The duty ratio of the rectangular wave signal generated by the PWM control unit 105 is determined based on the PWM register value stored in the cumulative value register. When the PWM register value stored in the accumulated value register matches the start value, that is, the reference PWM register value set in the initial value register, the duty ratio of the rectangular wave signal output by the PWM control unit 105 is, for example, It becomes 50%. When the PWM register value stored in the accumulation value register increases, the duty ratio of the rectangular wave signal increases, and conversely, when the PWM register value decreases, the duty ratio of the rectangular wave signal decreases.

Next, the comparison operation of the comparator 108 and the PWM
Regarding the relationship with the output signal of the register value changing unit 109,
This is explained below.

(1) When PCR value> STC value In this case, the comparator 108 outputs a high-level increase enable signal SI and a low-level decrease enable signal SD. In response, the PWM register value changing unit 109
Output the value a. As a result, the PWM control unit 105 sets the PWM register value stored in the accumulated value register to a
Are cumulatively added. As a result, the PWM register value stored in the cumulative value register increases, so that the PWM control unit 1
The duty ratio of the rectangular wave signal output from the signal line 05 increases. (2) When PCR Value <STC Value In this case, the comparator 108 outputs a low-level increase enable signal SI and a high-level decrease enable signal SD. In response, the PWM register value changing unit 109
Output the value -a. As a result, in the PWM control unit 105, the value -a is added to the PWM register value stored in the accumulated value register. As a result, the PWM register value stored in the cumulative value register decreases, so that the duty ratio of the rectangular wave signal output from the PWM control unit 105 decreases. (3) When PCR value = STC value In this case, the comparator 108 outputs a low-level increase enable signal SI and a low-level decrease enable signal SD. At this time, since the PWM register value changing unit 109 outputs the value 0, the PWM register value stored in the accumulated value register of the PWM control unit 105 is not changed. Therefore, the duty ratio of the rectangular wave signal output from PWM control section 105 is not changed. The method of determining the value a or -a held by the PWM register value changing unit 109 will be described later.

Next, the relationship between the signal output by the PWM control unit 105 and the PWM register value set in the PWM control unit 105 will be described by way of an example.

Assuming that the accumulated value register provided in the PWM control unit 105 is constituted by a register having a width of 10 bits, the minimum value and the maximum value of the PWM register value stored in the accumulated value register are 10 When expressed in base numbers, they are 0 and 1023, respectively. That is, the PWM register value stored in the cumulative value register is 0 to 1
023. Now, assuming that the operating frequency inside the PWM control unit 105 is 30 MHz, one cycle of the operating frequency is 33.3 nsec. PWM control unit 10
5 is the width of the HIGH portion of the generated rectangular wave signal (3
3.3 nsec × PWM register value) and one wavelength of the rectangular wave signal is set to (33.3 nsec × 102
Set to 4). As described above, the PWM control unit 105
In order to adjust the width of the HIGH portion of the rectangular wave signal based on the PWM register value, H at one wavelength of the rectangular wave signal is adjusted.
The ratio between IGH and LOW (that is, the duty ratio) can be changed in 1024 steps. Note that the initial value register included in the PWM control unit 105 holds 512 as a reference PWM register value in decimal notation, and the accumulated value register stores the reference PWM register value (=
512) is used as an initial value (start value) to perform an accumulative addition operation. When the PWM register value stored in the accumulated value register matches the reference PWM register value (= 512), P
The duty ratio of the rectangular wave signal output from the WM control unit 105 is set to 1: 1 (50%). When the PWM register value stored in the cumulative value register is the minimum value 0, the entire output signal of the PWM control unit 105 is LOW, and when the register value is the maximum value 1023, the PWM signal
The entire output signal of the M control unit 105 is HIGH.

Although not shown, the reference clock oscillator 907 includes a low-pass filter and a voltage controlled oscillator (VCO). The low-pass filter is P
The rectangular wave signal supplied from the WM control unit 105 is smoothed to generate an average voltage. The voltage controlled oscillator receives an average voltage generated by the low-pass filter as a control voltage. Therefore, the reference clock oscillator 907
The reference clock frequency can be moved up and down according to a change in the duty ratio of the rectangular wave signal output from the WM control unit 105. As will be described later, the upper and lower widths of the reference clock frequency (hereinafter, referred to as control widths) are set to appropriate values by assuming in advance the fluctuation width of the input data stream.

Next, an example of a method of determining the values a and -a held by the PWM register value changing unit 109 will be described.
First, an expected frequency variation width of the data stream is defined as a variation width ± X, and a reference clock control width generated by the reference clock control device 100 is defined as a control width ± Y. That is, the data stream has a fluctuation range of about 27 MHz ±
The reference clock fluctuates within X and the reference clock is controlled within a control width ± Y centered at approximately 27 MHz. By the way, in general, the reference clock control device is designed so that the control width ± Y is larger than the fluctuation width ± X in consideration of the frequency fluctuation of the reference clock due to the heat generation of the hardware and the variation of the component performance. Have been. Assuming now that Y = 10X, X corresponds to about 50 in PWM register value conversion.
Therefore, the reference clock control device 100 is the PWM control unit 1
For example, the PWM register value (stored in the accumulated value register) held in the time period 05 is rewritten 10 times (corresponding to the time period for receiving the time reference value PCR 10 times) from + X to -X. Assuming that the fluctuation range is changed up to, the constant value a is about 50 to about −5 of the PWM register value.
Dividing the fluctuation range of about 100 to 0 by 10 gives about 1
Set to 0. Hereinafter, a value obtained by converting the fluctuation range ± X into a register value is referred to as a register value equivalent value.

As described above, the relational expression between the fluctuation width ± X and the control width ± Y is obtained, and the register value equivalent value ± R of the fluctuation width ± X in the relational expression is obtained, and 2R (+ R to -R) is obtained. The value a can be obtained by dividing the change width by the number of times of rewriting of an arbitrary PWM register (corresponding to the number of times of receiving the time reference value PCR).

As described above, the register value changing section 109
Is the value a or-when the PCR value and the STC value are different.
a is output to the PWM control unit 105 when they match. Accordingly, the duty ratio of the signal output from PWM control section 105 is determined. When the duty ratio in the output signal of the PWM control unit 105 is changed, that is, when the HIGH ratio at one wavelength is increased or decreased as compared with the LOW ratio, the oscillation frequency of the reference clock oscillator 907 becomes higher or lower than 27 MHz. . As a result, the reference clock control device 100 can make the oscillation frequency of the reference clock oscillator 907 follow the frequency fluctuation of the data stream. Therefore, based on the reference clock generated by the reference clock oscillator 907, the STC counter 904 can output a synchronous count value that follows a change in the count value of the data stream to a decoder (not shown) or the like.

FIG. 2 is a graph showing an example of a transition of the PCR value-STC value obtained as a result of the control operation by the reference clock control device 100. Ideally, the PCR value-ST
Although the C value is 0, it is impossible to perform control such that the STC value completely follows the extracted PCR values in real time. Therefore, as shown in FIG.
It shows a tendency to fluctuate in the + direction or the − direction around the R value−STC value = 0. As is clear from FIG. 2, the reference clock control device 100 calculates the PCR value -ST
When the C value shows a tendency to deviate from 0, the tendency is gradually reduced, and for example, it tends to converge to 0 around 0.8 seconds and 2.1 seconds. As a result, the reference clock control device 100 performs control so that the PCR value-STC value does not deviate too much from 0.

(Second Embodiment) FIG. 3 is a block diagram showing a configuration of a reference clock control device according to a second embodiment of the present invention. In FIG. 3, the reference clock control device 200 of the present embodiment differs from the configuration of the reference clock control device 100 of the first embodiment in that a PWM register value change unit 209 is used instead of the PWM register value change unit 109.
Is provided, and an adder 210, a comparator 212, and a threshold value storage unit 211 are newly added. The same components as those of the reference clock control device 100 have the same reference numerals, and detailed description thereof will be omitted.

The PCR value held in the PCR (t) register 902 and the STC value held in the STC (t) register 903 are input to the comparator 108 and also to the subtracter 210. Threshold value storage unit 21
1 stores a predetermined threshold value A. An example of a method for determining the threshold value A will be described later in a third embodiment. The operation of the comparator 108 is as already described in the first embodiment. The subtracter 210 calculates the absolute value of the difference between the PCR value and the STC value (= |
PCR (t) -STC (t) |) is obtained and its value is stored. The comparator 212 reads the absolute difference value and the threshold value A from the subtractor 210 and the threshold value storage unit 211, respectively, and compares the magnitude relations. Comparator 212 calculates | PCR (t) -STC
When (t) |> A, the register value selection signal SS is set to a high level, and when | PCR (t) -STC (t) | <A, the register value selection signal SS is set to a low level. When | PCR (t) −STC (t) | = A, it is an arbitrary design matter whether the comparator 212 sets the register value selection signal SS to a high level or a low level. In the embodiment, the level is set to a high level for convenience.

The PWM register value change section 209 is a PWM
The control unit 105 holds five types of values a, -a, b, -b, and 0 as values for changing the PWM register value, and includes a register value selection signal SS, an increase enable signal SI, and a decrease enable signal. The value to be output is switched according to the combination of the logics of SD. That is, when the high-level register value selection signal SS and the high-level increase enable signal SI are given, the PWM register value change unit 209 outputs a positive value a, and outputs the high-level register value selection signal SS and the high level. When the level decrease enable signal SD is applied, a negative value -a is output. The PWM register value change unit 209 outputs a positive value b when the low-level register value selection signal SS and the high-level increase enable signal SI are given, and outputs the low-level register value selection signal SS and the high-level register value selection signal SS. When the level decrease enable signal SD is applied, a negative value -b is output. When the low-level increase enable signal SI and the low-level decrease enable signal SD are given, the PWM register value change unit 209 outputs 0 regardless of the level of the register value selection signal SS. The value b is an arbitrary value that satisfies a <b obtained in the same manner as the value a. Also, the configurations and operations of the PWM control unit 105, the reference clock oscillator 907, and the STC counter 904 are the same as those used in the first embodiment, and thus description thereof will be omitted.

As described above, especially when the absolute value of the difference between the PCR value and the STC value is larger than the threshold value A, the reference clock control device 200
5 by adding the value b or -b to the initial value 512 of the accumulated value register provided in the value a or -a.
Of the PWM register 105 compared to the case where
The register value can be largely changed. Therefore,
The reference clock control device 200 is particularly different from the first embodiment in which the PWM register value of the PWM register value changing unit is controlled by only one series of values a and -a, in particular, the PCR value and the STC
If the difference is large, the frequency of the reference clock can quickly follow the frequency fluctuation of the data stream.

FIG. 4 is a graph showing an example of the transition of the PCR value-STC value obtained as a result of the control operation by the reference clock control device 200. PCR value-ST shown in FIG.
The manner of transition of the C value is similar to FIG. However, comparing FIG. 4 with FIG. 2, the PCR value-STC shown in FIG.
The fluctuation range of the value is smaller than that of FIG. As is clear from FIGS. 4 and 2, the reference clock control device 200 can quickly converge the PCR value−STC value to 0 as compared with the reference clock control device 100.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a reference clock control device according to the embodiment. In FIG. 5, a reference clock control device 300 is different from the configuration of the reference clock control device 200 according to the second embodiment in that
, A PWM register value changing unit 309 is provided.
A PWM control unit 305 is provided instead of the control unit 105, and the PC
R (t-1) register 313, STC (t-1) register 315, subtractors 314 and 316, comparator 317,
PWM register value change section 318, provisional PWM value storage section 3
19 in that switches 320 and 321 are newly provided. Hereinafter, the operation of the reference clock control device 300 will be described with reference to FIG. The same components as those of the reference clock control device 200 have the same reference numerals, and detailed description thereof will be omitted. In addition, PWM
Unlike the first and second embodiments, the PWM register included in the control unit 305 is not provided with an initial value.

The PCR (t-1) register 313 is a PC
The R (t) register 902 holds a PCR value (hereinafter, referred to as a PCR (t-1) value) held immediately before a PCR value (hereinafter, referred to as a PCR (t) value) currently held. . The STC (t-1) register 315 stores the STC (t)
The STC value currently held by the register 903 (hereinafter referred to as S
The STC value (hereinafter referred to as the STC (t-1) value) held immediately before the TC (t) value is held. The subtractor 314 includes a PCR (t) register 902 and a PCR (t) register 902.
(T-1) PCR (t) value and P
Read the CR (t-1) value and calculate the PC from the PCR (t) value.
The difference (hereinafter referred to as ΔPCR value) is obtained by subtracting the R (t−1) value. The subtractor 316 outputs a signal from the STC (t) register 903 and the STC (t−1) register 315 to S
The TC (t) value and the STC (t-1) value are read out and S
The STC (t-1) value is subtracted from the TC (t) value to determine the difference (hereinafter, referred to as the ΔSTC value).

The comparator 317 includes subtractors 314 and 31
Then, the .DELTA.PCR value and .DELTA.STC value are read from No. 6 and their magnitudes are compared. As a result, when ΔPCR value> ΔSTC value, the comparator 317 outputs a high-level increase enable signal SI1 and a low-level decrease enable signal SD1.
Is output, and when ΔPCR value <ΔSTC value, a low-level increase enable signal SI1 and a high-level decrease enable signal SD1 are output, and ΔPCR value = ΔSTC
When the value is a value, a low-level increase enable signal SI1 and a low-level decrease enable signal SD1 are output.

The PWM register value changing section 318 stores the value c,
-C, and outputs a value c when the high-level increase enable signal SI1 and the low-level decrease enable signal SD1 are input, and outputs the low-level increase enable signal SI1 and the high-level decrease enable signal S1.
When D1 is input, it outputs a value -c.

Further, the comparator 317 includes a switch 320
And a switch control signal Sc for controlling the opening and closing of the switch 321. The switches 320 and 321 perform complementary opening and closing operations in response to the switch control signal Sc. That is, when one of the switches 320 and 321 is closed, the other opens. At the start of the operation, if ΔPCR value> ΔSTC value, the comparator 317
Outputs a high-level increase enable signal SI1 and a low-level decrease enable signal SD1. In response, PWM register value changing section 318 outputs value c. On the other hand, at the start of the operation, ΔPCR value <ΔSTC
In the case of the value, the comparator 317 outputs the low-level increase enable signal SI1 and the high-level decrease enable signal S1.
D1 is output. Accordingly, the PWM register value changing unit 31
8 outputs the value -c. Also, at the start of operation,
Regardless of whether the ΔPCR value> ΔSTC value or the ΔPCR value <ΔSTC value, the comparator 317 sets the switch 320
Is closed, and the switch 321 is opened. With this, the provisional PW
At the start of the operation, the M register value storage unit 319 stores
When ΔPCR value> ΔSTC value, the value c is set as the PWM register value, and when ΔPCR value <ΔSTC value, PW
The value -c is input as the M register value. If the magnitude relationship between the ΔPCR value and the ΔSTC value is reversed after the operation starts, the switch 320 is opened and the switch 321 is closed.

The comparator 108, the subtractor 210, the threshold value storage unit 211, and the comparator 212 perform the same operations as those described in the second embodiment. However, the PWM register value change unit 309 holds the values a, -a, and 0 as values for changing the PWM register value. The comparator 212 outputs a high-level register value selection signal SS when the result of the comparison between the subtraction result of the subtractor 210 and the threshold value A held by the threshold value storage unit 211 is larger than the threshold value A. I do. In response, PWM register value changing section 309 outputs value a or −a. On the other hand, when the threshold value A is larger than the subtraction result of the subtractor 210, the comparator 21
2 outputs a low-level register value selection signal SS. In response, PWM register value changing section 309 outputs 0. In addition, the PWM register value changing unit 309 includes the first
As in the case of the second embodiment, the values a and -a are switched and output according to the enable signal output from the comparator 108. That is, when the high-level increase enable signal SI and the low-level decrease enable signal SD are supplied, the PWM register value variation unit 309 outputs a positive value a, and outputs the low-level increase enable signal SI and the high-level increase enable signal SI. When the decrease enable signal SD is given, a negative value -a is output.

Although not shown, the provisional PWM register value storage section 319 includes, for example, an initial value register, a provisional value register, and an addition section. The initial value register holds a reference PWM register value 512 in advance. The provisional value register stores the reference PW while the switch 320 is closed.
PWM register value change unit 3 for M register value 512
The value c or -c output from 18 is cumulatively added and held. Therefore, for example, if the value c is input N times and the value −c is input M times, the value of the provisional value register is 512+
(C × N) + (− c × M). Here, assuming that the value of the temporarily added temporary value register is a provisional PWM register value β, the provisional PWM register value β
Is opened and the switch 321 is closed when it is closed. Thereafter, the provisional PWM register value storage unit 319 stores the P
One of the values a, -a, and 0 is input from the WM register value changing unit 309. At this time, the addition unit in the provisional PWM register value storage unit 319 reads the provisional PWM register value β held in the provisional value register, and simply adds the value a, -a, or 0 to the provisional register value β. And output. Accordingly, the provisional PWM register value storage unit 319
Outputs the PWM register value of any one of β + a, β−a, and β. The PWM control unit 305 determines the provisional PWM
The duty ratio of the generated rectangular wave signal is changed according to the three values output from the register value storage unit 319. Note that the operations of the reference clock oscillator 907 and the STC counter 904 are the same as in the first embodiment, and a description thereof will be omitted.

Here, unlike the first and second embodiments, the reference clock control device 300 sets the PCR value and ST
The reason for using both the C value and the ΔPCR value and the ΔSTC value will be described.

First, the comparator 317 compares the amount of change in the PCR value and the amount of change in the STC value in one PCR extraction interval. By the way, one PCR extraction interval is S
This is naturally equal to the interval at which the STC value is output from the TC counter. Assuming that the time interval is t, the slope of the PCR value and the slope of the STC value are respectively: PCR value change amount / t STC value change amount / t. Therefore, the comparison between the change amount of the PCR value and the change amount of the STC value results in the P value in one PCR extraction interval.
It is a comparison of the slope between the CR value and the STC value. Therefore, P
Correction is performed by the value c or −c output from the WM register value change unit 318 so that the two slopes become equal.

As described above, ΔPC from the start of the operation
An operation to reduce the difference between R and ΔSTC is started, and PW
The value c input from the M register value change unit 318 or −
The provisional PWM register value held in the cumulative value register included in the provisional PWM register value storage unit 319 is continuously updated by c. Thereafter, when the magnitude relationship between ΔPCR and ΔSTC is reversed and the switch 320 is opened and the switch 321 is closed, the operation of the inclination correction ends and the operation of correcting the difference between the PCR value and the STC value is started. At this point, the accumulated value register in the provisional PWM register value storage unit 319 holds the provisional PWM register value β that can correct a fixed time lag that occurs between the data stream and the reference clock. .

When the operation of correcting the difference between the PCR value and the STC value is started, any one of the values a, -a, and 0 is input to the provisional PWM register value storage unit 319 via the switch 321. . Accordingly, from the provisional PWM register value storage unit 319, if the provisional PWM register value is β, β
Any of the PWM register values of + a, β-a, and β is output. At this time, if the difference between the PCR value and the SCT value is smaller than the threshold value A, that is, if the difference is acceptable, the provisional PWM register value β itself becomes the PWM value.
It is supplied to the M control unit 305. In this case, a fixed time lag between the data stream and the reference clock is corrected. On the other hand, when the difference between the PCR value and the SCT value is larger than the threshold value A, that is, when the difference exceeds an allowable level, either β + a or β−a is supplied to the PWM control unit 305. In this case, not only a fixed time lag occurring between the data stream and the reference clock but also other dynamically changing time lags are corrected. As described above, the time lag between the data stream and the reference clock is divided into the fixed lag and the other lag, and is corrected hierarchically, whereby the first and second embodiments are corrected. Compared to, more accurate and agile correction is possible.

FIG. 6 is a graph showing an example of the transition of the PCR value-STC value obtained as a result of the control operation by the reference clock control device 300. PCR value-ST shown in FIG.
The fluctuation range of the C value is very narrow as compared with the fluctuation ranges shown in FIGS. In the actual data prepared for creating FIG. 6, the switch 3 is used until 0.6 seconds after the operation of the reference clock control device 300 starts.
20 is closed, and the value 11 is input from the PWM register value change unit 318 to the temporary PWM register value storage unit 319. During this time, the PCR value-STC value has a relatively large fluctuation range. On the other hand, from 0.7 seconds to 1.4 seconds after the start of the operation of the reference clock control device 300, the switch 321 is closed and the value 10 is input from the PWM register value changing unit 309 to the provisional PWM register value storage unit 319. 1.5 seconds
Up to 3.0 seconds, a value of 0 has been entered. During this time, PC
The R value-STC value gradually converges in the 0 axis direction and becomes slightly negative after 2.7 seconds, but after 3.1 seconds not shown in FIG. 6, after the operation of the reference clock control device 300 starts. It has been confirmed that the variation is much narrower than the period up to 0.6 seconds.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a reference clock control device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a PCR value-STC obtained as a result of a control operation performed by the reference clock control device according to the first embodiment of the present invention.
It is a graph which shows an example of a transition of a value.

FIG. 3 is a block diagram illustrating a configuration of a reference clock control device according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a PCR value-STC obtained as a result of a control operation performed by the reference clock control device according to the second embodiment of the present invention.
It is a graph which shows an example of a transition of a value.

FIG. 5 is a block diagram illustrating a configuration of a reference clock control device according to a third embodiment of the present invention.

FIG. 6 shows a PCR value-STC obtained as a result of a control operation performed by the reference clock control device according to the third embodiment of the present invention.
It is a graph which shows an example of a transition of a value.

FIG. 7 is a block diagram showing a configuration of a conventional reference clock control device.

[Explanation of symbols]

901: PCR extraction unit 902: PCR (t) register 903: STC (t) register 904: STC counter 907: reference clock oscillator 911, 912: switch 105, 305: PWM control unit 108, 212, 317: comparator 109, 209, 309, 318: PWM register value change section 211: threshold value storage section 210, 314, 316: subtractor 313: PCR (t-1) register 315: STC (t-1) register

Claims (7)

[Claims] 1. A reference clock control device for receiving a data stream in which a time reference value is inserted at predetermined intervals and generating a time count signal following the data stream, wherein the time reference reference value is derived from the data stream. A PCR extraction unit for extracting and outputting a value; and a PC that outputs the time reference value output from the PCR extraction unit.
A PCR value holding unit for holding as an R value; a reference clock oscillator for generating a reference clock according to an oscillation frequency; and a count operation of the reference clock starting from a time reference value initially output by the PCR extraction unit. An STC counter to start; an STC value holding unit that takes in the count value of the STC counter at that time and holds it as an STC value each time the PCR extraction unit extracts the time reference value; And a comparator for reading the PCR value held in the STC value and the STC value held in the STC value holding unit and comparing the magnitude relation between them, and a plurality of values are set in advance, and the comparison result of the comparator Accordingly, a PWM register value changing unit that selects and outputs one value from the plurality of values, and a reference PWM register value is set in advance. A PWM control unit that cumulatively adds the values output from the PWM register value fluctuations with the reference PWM register value as a start value, and controls the oscillation frequency of the reference clock oscillator based on the resulting cumulative value. A reference clock control device, comprising: using a count value of the STC counter as the time count signal. 2. The PWM register value change section includes a first value for increasing the cumulative addition value, a second value for decreasing the cumulative addition value, and a current cumulative addition value. A third value that does not fluctuate is set in advance, and the PWM register value fluctuating section includes a PCR value held in the PCR value holding section and an STC value held in the STC value holding section. 2. The method according to claim 1, wherein when the two values do not match, one of the first and second values is selected and output, and when the two values match, the third value is selected and output. Reference clock controller as described. 3. A reference clock control device for receiving a data stream in which a time reference value is inserted at predetermined intervals and generating a time count signal following the data stream, wherein the time reference reference value is derived from the data stream. A PCR extraction unit for extracting and outputting a value; and a PC that outputs the time reference value output from the PCR extraction unit.
A PCR value holding unit for holding as an R value; a reference clock oscillator for generating a reference clock corresponding to an oscillation frequency; and a count operation of the reference clock starting from the time reference value output first by the PCR extraction unit. An STC counter that starts counting, a STC value holding unit that takes in the current count value of the STC counter and holds it as an STC value each time the PCR extraction unit extracts the time reference value, and the PCR value holding. A first comparator for reading out the PCR value held in the section and the STC value held in the STC value holding section and comparing the magnitude relation between the first value and the PCR value held in the PCR value holding section; Said S
A subtractor for obtaining an absolute value of a difference from the STC value held in the TC value holding unit; a threshold value storage unit for holding a predetermined threshold value; and a subtraction result of the subtractor and the threshold storage unit. A second comparator for reading the held threshold value and comparing the magnitude relation between the threshold value and a plurality of values which are set in advance and according to a comparison result of the first and second comparators, A PWM register value changing unit for selecting and outputting one value from a plurality of values; a reference PWM register value is set in advance, and the reference PWM register value is set as a start value and output from the PWM register value change. And a PWM control unit for controlling the oscillation frequency of the reference clock oscillator based on the cumulative addition value as a result of the addition. Characterized by using the count value of data as the time count signal, the reference clock controller. 4. When the arbitrary positive values a and b have a relationship of a <b, the PWM register value change unit includes values a and b for increasing the cumulative addition value. The values -a and -b for decreasing the cumulative addition value and a value 0 that does not change the current cumulative addition value are set in advance, and the PWM register value variation unit includes the subtractor Is smaller than the threshold value held in the threshold value storage section, and the PCR value held in the PCR value holding section is equal to the ST value.
When the STC value held in the C value holding unit does not match, either the value a or -a is selected and output, and the subtraction result of the subtracter is held in the threshold value storage unit. The PCR value larger than the threshold value and the ST value and held in the PCR value holding unit.
When the STC value held in the C value holding unit does not match, either the value b or -b is selected and output, and the subtraction result of the subtracter is held in the threshold value storage unit. Threshold value and the P
When the PCR value held in the CR value holding unit does not match the STC value held in the STC value holding unit,
Any one of the values a, -a, b or -b is selected and output, and the PCR value held in the PCR value holding unit and the S
4. The reference clock control device according to claim 3, wherein when the STC value held in the TC value holding unit matches, the value 0 is selected and output. 5. A reference clock control device for receiving a data stream in which a time reference value is inserted at a predetermined interval and generating a time count signal following the data stream, wherein the time reference reference value is derived from the data stream. A PCR extraction unit for extracting and outputting a value, and a time reference reference value output by the PCR extraction unit as a first value.
A first PCR value holding unit that holds the PCR value as a PCR reference value; and a time reference reference value that is held immediately before the time reference reference value that is currently held in the first PCR value holding unit.
A second PCR value holding unit that holds a PCR value as a reference value; a reference clock oscillator that generates a reference clock according to an oscillation frequency; and a time reference value that is first output by the PCR extraction unit. An STC counter that starts a clock counting operation; and an STC value holding unit that takes in the count value of the STC counter at that time and holds it as a first STC value each time the PCR extraction unit extracts the time reference value. A count value held immediately before the count value currently held in the first STC value holding unit,
A second STC value holding unit for holding as a value, and a first PC held in the first PCR value holding unit.
A first comparator for reading out an R value and a first STC value held in the first STC value holding unit and comparing the magnitude relation between the R value and the first STC value; First PC
R value and the first STC value held in the first STC value holding unit.
A first subtractor for obtaining an absolute value of a difference from the STC value, a threshold value storage unit that holds a predetermined threshold value, and a subtraction result of the first subtractor and stored in the threshold value storage unit. A second comparator for reading out the threshold value and comparing the magnitudes thereof, and a plurality of values set in advance, and the plurality of values are set in accordance with the comparison result of the first and second comparators. A first PWM register value change unit that selects and outputs one value from the values of the first and second PCR values, and a first PC that is stored in the first PCR value storage unit.
A second subtractor for subtracting the second PCR value held in the second PCR value holding unit from the R value to obtain ΔPCR; and a first subtractor held in the first STC value holding unit. ST
A third subtractor for subtracting the second STC value held in the second STC value holding unit from the C value to obtain ΔSTC; and ΔPCR and ΔST from the second and third subtractors.
A third comparator for reading C and comparing the magnitude relation thereof; and a plurality of values set in advance, one of the plurality of values being set according to the comparison result of the third comparator. And a second PWM register value changing section for selecting and outputting a reference PWM register value which is set in advance, and the second PWM
The value output from the M register value changing unit is cumulatively added, and the cumulative added value at the time when the comparison result of the third comparator is inverted is used as a provisional PWM register value.
The value output from the WM register value changing unit is set to the temporary PW
The PWM register value is obtained by simply adding to the M register value,
A PWM control unit for controlling an oscillation frequency of the reference clock oscillator based on the PWM register value, wherein a count value of the STC counter is used as the time count signal. 6. When the arbitrary positive values a and b have a relationship of a <b, the first PWM register value change unit includes a value a for increasing the cumulative addition value. And b, values -a and -b for decreasing the cumulative addition value, and a value 0 that does not change the current cumulative addition value are preset, and the first PWM register value variation The unit, a subtraction result of the first subtractor is smaller than a threshold value held in the threshold value storage unit,
When the first PCR value held in the first PCR value holding unit does not match the first STC value held in the first STC value holding unit, the value a or-
a is selected and output, and a subtraction result of the first subtractor is larger than a threshold value held in the threshold value storage unit;
And when the first PCR value held in the first PCR value holding unit does not match the first STC value held in the first STC value holding unit, the value b or-
b, and outputs the selected value. The subtraction result of the first subtractor matches the threshold value held in the threshold value storage unit, and is held in the first PCR value holding unit. The first PC that is
R value and the first STC value held in the first STC value holding unit.
If the STC value does not match any one of the values a, -a, b, or -b, the selected value is output, and the first PC held in the first PCR value holding unit is output.
R value and the first STC value held in the first STC value holding unit.
6. The reference clock control device according to claim 5, wherein a value 0 is selected and output when the STC value of the reference clock signal coincides with the STC value. 7. The second PWM register value change section includes a first value for increasing the cumulative addition value, a second value for decreasing the cumulative addition value, and a current accumulation value. A third value that does not fluctuate the addition value is set in advance, and the second PWM register value fluctuation unit sets the first and second PWM registers when the ΔPCR and the ΔSTC do not match.
7. The reference clock control device according to claim 5, wherein one of the values is selected and output, and when the values match, the third value is selected and output.