JP2002094238A - Multilayer wiring board and its method of manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board with a buildup structure and a method for manufacturing it by which connection between the first layer and the third layer and between the nth layer and the (n-1)th layer can be performed in high density and with a small number of steps and a structure of the multilayer wiring board which causes no blowing up of solder can be obtained. SOLUTION: With respect to the multilayer wiring board which has n layers more than two and in which connection is made between layers 1 and 2, 1 and 3, 2 and 3, n and (n-1), n and (n-2) and (n-1) and (n-2), holes 8 of a diameter of 40 μm or less are formed in the insulating layers between the layers 2 and 3, and (n-1) and (n-2) and are filled with copper plating 9 and the layers are connected between 1 and 2, 2 and 3, n and (n-1) and (n-1) and (n-2) respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having three or more n-layers capable of high-density wiring and a method of manufacturing the same, and more particularly to a multilayer wiring board having a build-up structure and a method of manufacturing the same. It is.

[0002]

2. Description of the Related Art In recent years, with higher performance and higher densities of electronic devices, higher densities of wiring boards such as printed wiring boards have been demanded. As a method for increasing the wiring density of such a wiring board, the following method is considered to be effective. (1) Reduce the wiring width, wiring interval, and land diameter. (2) To increase the number of layers by increasing the number of layers. (3) The diameter (via diameter) of a via hole serving as a conductive path between layers is reduced. (4) Eliminate the penetrating via hole.

However, in the current wiring board, in the case of an area array type package (BGA) for mounting the back surface of an LSI in which terminals of solder balls are arranged in a lattice on the lower surface,
When the through via is used, there is a problem that the wiring cannot be drawn out. Therefore, a wiring board having a build-up structure as shown in FIGS. 4 to 6, which can reduce a via diameter without using a through via hole, has been used. Since the wiring board having the build-up structure literally has a multi-layered build-up layer, if the number of the build-up layers increases, the number of steps inevitably increases.

The following is an example of the steps of a build-up method in which build-up layers are stacked in multiple layers. (1) Pretreatment step for improving the adhesion between resin and pattern (2) Application step of adhesive (insulating layer) (3) Curing step (4) Drilling step by laser (5) Desmearing step (6) Chemistry Copper process (7) Electroplating process (8) DF laminating process (9) Exposure, etching, DF peeling process

[0005] The build-up method is a method of plating a bottomed via hole. In order to apply plating to the bottomed via hole, the bottomed via hole is set to “hole depth / hole diameter ≦ 1”. In the case where one layer and three layers must be connected, the hole diameter must be equal to or larger than the distance between the insulating layers, and this is an obstacle to further increase in the density. In addition, when mounting a CSP, which is a small semiconductor package having the same size or slightly larger size as the BGA or the chip described above, if the through via hole is clear, solder may enter the via hole during mounting and short-circuit may occur. In such a case, the through-hole is closed with a resin or a conductive paste.

FIGS. 4 to 6 show a multi-layer wiring board having a build-up structure manufactured by the above-mentioned build-up method.
This is a method by which a connection can be established between the first and second layers and the second and third layers. FIG. 4 shows that the manufacturing process is shortened by simultaneously performing the drilling of one layer and three layers and the drilling of one layer and two layers. However, the drilling of one layer and three layers is performed by plating. Is required to be 1 or less, which is an aspect that can be provided, and the diameter of the via hole 5 becomes large, which is an obstacle to high density.

On the other hand, the one shown in FIG. 5 uses the connection area 6 more than necessary because the via hole 5 cannot be formed on the via hole 1 when connecting between one layer and three layers. Therefore, it is an obstacle to high density. On the other hand, the one shown in FIG. 6 allows the via hole 5 to be formed on the via hole 5 by filling the bottomed via hole 5, and the hole diameter is within the diameter defined between the first and second layers. Although it is formed, there are problems that the number of steps for filling the via hole 5 increases, and that filling the bottomed via hole 5 is technically difficult. This uses an insulating or conductive paste 7 when filling the bottomed via hole 5.
This is because the deeper the hole is, the harder it is for the air that has entered to escape, and the air accumulates, and even if it escapes, a dent remains.

Further, according to the multilayer wiring board formed by the above-described build-up method, since the holes in the surface layer and the layer under the surface layer are not filled, the solder balls are trapped in the holes at the time of mounting, and the amount of solder decreases. I do. For this reason, it is difficult to bring a via hole into the pad portion of the BGA, and it is necessary to provide connection lands between the lands of the BGA. However, this becomes a bottleneck in wiring and makes it difficult to realize a high-density wiring board. ing.

Further, in a multilayer wiring board having a build-up structure, a surface layer (one layer) and a third layer from the surface layer (three layers)
When the connection is attempted, the number of steps is increased to 27 (three times as large as the above nine), which causes a problem of an increase in manufacturing cost. This process is repeated, which causes a problem in that distortion due to heat during processing occurs in the resin and dimensional accuracy cannot be maintained.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to address the above-mentioned problems. The first object of the present invention is to provide a multi-layer wiring board having a build-up structure with one and three layers, and n layers. It is an object of the present invention to provide a multilayer wiring board and a method for manufacturing the multilayer wiring board, in which connection between layers and the (n-1) layer can be performed at a high density and with a small number of steps. Another object of the present invention is to provide a multilayer wiring board having a structure in which plating can be applied at the same time as plating by a build-up method, and soldering does not occur even without providing a separate filling step. It is an object of the present invention to provide a multi-layer wiring board and a method of manufacturing the same.

[0011]

In order to solve the above-mentioned problems, a multilayer wiring board according to the present invention has three or more layers, one layer and two layers, one layer and three layers, and two layers. And three layers, n and (n-1) layers, n and (n-2) layers, and (n-1) and (n-2) layers.
A hole having a diameter of 40 μmφ or less is formed in the insulating layer between the two layers and the three layers and the (n-1) layer and the (n-2) layer, and the hole is filled with copper plating. It is characterized in that two layers and three layers, n layer and (n-1) layer, and (n-1) layer and (n-2) layer are connected, respectively.
A hole having a diameter of 40 μm or less is formed in the insulating layer between each of the layers (n-1) and (n-2), and the holes are filled with copper plating to form the first and second layers. , Two layers and three
Layer, n layer and (n-1) layer, and (n-1) layer and (n-2)
Since the layers can be connected to each other, one layer and two layers, n
The connection can be made in a single step by drilling and copper plating for each overlapped wiring layer between the layer and the (n-1) layer.

Further, in the multilayer wiring board according to the present invention, in the multilayer wiring board described above, the two layers, the three layers, the (n-1) layer, and the (n-
2) laser drilling on the connection between the layers,
A connection between one layer and two layers, an n layer and (n−1) layers is formed, and
And three layers, and between the n layer and the (n−2) layer, wherein each of the connected wiring layers is further laminated, and a desired wiring layer already connected is formed. The connection can be made possible by laser drilling.

Further, the multilayer wiring board according to the present invention is characterized in that, in the multilayer wiring board described above, the shape of the hole is elliptical or elliptical, and the hole shape is elliptical or elliptical. By doing so, the resistance value of the filling portion can be made equal to the resistance value of the circuit portion.

In order to solve the above-mentioned problems, a method for manufacturing a multilayer wiring board according to the present invention comprises three or more layers, one layer and two layers, one layer and three layers, and two layers and three layers. , N layers and (n
-1) layer, n layer and (n-2) layer, (n-1) layer and (n-
2) In the method for manufacturing a multilayer wiring board in which the layers are connected to each other, the above-mentioned one layer and two layers, one layer and three layers, two layers and three layers, n layers and (n-1) layers, and n layers and (n- 2) a step of forming holes in the insulating layer between the layers to connect the (n-1) layer and the (n-2) layer, and a conductive substance contributing to the holes formed in the above steps; Filling a hole by electroplating; forming a circuit on the insulating material filled in the above step; and forming the circuit on the insulating material.
Layer, three layers, (n-1) layer, and (n-2) layer, the one layer, n
Laminating a wiring layer composed of a layer and other layers with an insulating adhesive; and, after the lamination, forming a hole in an insulating layer between each of one layer and two layers, and n layers and (n-1) layers. And a step of applying an electroplating by applying a conductive substance to the holes between the first and second layers and the n-layer and the (n-1) layer formed in the above step, and performing electroplating. According to such a method, the holes formed in the insulating layers between the layers can be filled at the same time as the electroplating is applied, so that there is no need to provide a separate hole filling step, and the number of steps is smaller than that of the conventional build-up method. And a multilayer wiring board having a structure in which solder does not bleed up can be obtained.

In the method for manufacturing a multilayer wiring board according to the present invention, in the method for manufacturing a multilayer wiring board described above, the drilling between the first and second layers and the n-layer and the (n-1) -layer may be performed by laser processing. By performing the drilling by laser processing, an elliptical or elliptical hole can be easily drilled.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram of a multilayer wiring board according to a first embodiment of the present invention, FIGS. 2A and 2B are configuration diagrams each showing a shape of a hole, and FIG. It is a block diagram of such a multilayer wiring board.

As shown in FIG. 1, there are three or more n layers,
1 layer and 2 layers, 1 layer and 3 layers, 2 layers and 3 layers, n layer and (n−
1) layer, n layer and (n-2) layer, (n-1) layer and (n-
2) The multi-layer wiring boards each connecting the layers are laminated using an insulating adhesive. As this insulating adhesive,
Glass-epoxy resin, glass-BT resin, glass-polyimide resin, polyimide film, epoxy film, liquid crystal polymer fiber impregnated with epoxy, liquid crystal polymer impregnated with BT, etc. are used. Is cured after heat treatment to form an insulating layer between the layers. Note that a metal such as a copper wiring is used as the wiring.

In the connection between the two layers and the three layers and between the (n-1) layer and the (n-2) layer, the hole 8 formed in the insulating layer is formed by drilling or laser processing. Laser processing is desirable from the surface, and the diameter of the hole 8 is desirably 40 μmφ or less in consideration of circuit formation and hole filling. When the hole diameter becomes large, the thickness of the plating applied for filling the hole becomes large, so that a fine line cannot be formed when a wiring pattern is formed. When the hole diameter is 40 μmφ or more, a target fine line pattern cannot be obtained.

Further, when the resistance of the hole filling portion is 40 μmφ, the resistance value is higher than the resistance value of the circuit portion. Therefore, it is desirable to make the resistance values equal to each other, and the hole shape is elliptical as shown in FIGS. 2A and 2B. The resistance value is made equal to that of the circuit section as the shape 8a or the oval 8b. When a conductive substance is adsorbed to the hole 8, Pd, carbon, a conductive polymer, or the like is used, and then electroless plating may be performed. Further, instead of adsorbing the above substance, a thin conductive film may be formed by a vapor deposition method or the like.

On the other hand, plating 9 applied for filling holes
May be a copper plating 9 used for a normal printed wiring board, and the hole can be filled by applying a plating 9 of 20 μm or more. This plating may be performed by electroless plating, or there is no problem if a negative pattern of the wiring is formed on the above-described insulating material, and the filling of the holes and the plating on the circuit portion are simultaneously performed by the electrolytic copper plating method.

The wiring formed here is a subtrust method in which an etching mask is formed on the surface on which the wiring is to be formed by using the above-described insulating layer covered with copper foil, and the copper foil other than the wiring pattern portion is removed. Can be formed. As the etching resist, any of a liquid, a film, and an electrodeposition resist may be used.

As a method of laminating the material on which the copper wirings are formed, a method of adjusting the positions of the wirings between the respective layers and joining them with an adhesive can be used. The laser used for drilling the connection between the two and three layers and the (n-1) layer and the (n-2) layer by laser processing includes a carbon dioxide gas laser, a YAG laser, and a UV-YAG laser.
It can be performed by any of a laser and an excimer laser. Hereinafter, specific examples will be described.

Example 1 (see FIG. 1) First, a copper-clad laminate (R-170 manufactured by Matsushita Electric Works, Ltd.)
5: base material thickness 0.06 mm, copper foil thickness 12 μm)
A hole 8 having a diameter of 20 μm was formed by a V-YAG laser. Then, after treatment with a Pb catalyst solution, chemical copper plating was applied. Thereafter, 20 μm of electrolytic copper plating was applied to the surface, and as shown in FIG.

By laminating a resist (AQ-2588 manufactured by Asahi Kasei Corporation) on the surface of the copper-plated laminate, exposure and development were performed to form a resist film in a circuit pattern. Next, the exposed portion of the copper foil is etched with a cupric chloride solution to obtain a line width of 40 μm and a wiring gap 40.
A μm copper wiring was formed. A film adhesive was interposed between the copper-clad laminate and the surface on which the copper wiring was formed, and after positioning, the laminate was pressed to obtain a six-layer laminate.

A via hole 5 is formed by using a UV-YAG laser having a beam diameter of 80 μm to form a laser hole from both sides of the copper wiring portion on the upper surface and connecting portions between the first and second layers and the sixth and fifth layers. Was. Next, after treatment with a Pb catalyst solution, electroless plating was performed, and further, electrolytic plating was performed. A circuit was formed by laminating a dry film resist (AQ-2588 manufactured by Asahi Kasei Corporation) on the copper surface, performing exposure and development.

As described above, 220 mm ×
A multilayer wiring board of 220 mm × 0.6 mm in thickness and 6 layers in total was prepared. Using this multilayer wiring board, −65 degrees⇔1
25 degree heat cycle test (MIL-STD-202)
Was performed for 1000 cycles, but no delamination or cracking of the substrate occurred. The obtained multilayer wiring board was able to improve the circuit density about four times as compared with the conventional through-hole board, and was able to increase the mounting density. In addition, the number of processes is one compared to the conventional build-up method.
It could be manufactured in as few as eight steps.

Example 2 (see FIG. 3) First, a copper-clad laminate (R-170 manufactured by Matsushita Electric Works, Ltd.)
5: base material thickness 0.06 mm, copper foil thickness 12 μm)
A hole 8 having a diameter of 25 μm was formed by a V-YAG laser. Then, after treatment with a Pb catalyst solution, chemical copper plating was applied. After that, electrolytic copper plating was applied to the surface by 20 μm, and the holes 8 were filled with the copper plating.

By laminating a resist (AQ-2588 manufactured by Asahi Kasei Corporation) on the surface of the copper-plated laminate, exposure and development were performed to form a resist film in a circuit pattern. Next, the exposed portion of the copper foil is etched with a cupric chloride solution to obtain a line width of 40 μm and a wiring gap 40.
A μm copper wiring was formed. A prepreg (material thickness: 0.06 mm) manufactured by Matsushita Electric Works Co., Ltd. and a copper foil (thickness: 12 μm) manufactured by Nikko Gould Co., Ltd. were superposed on the front and back sides of the copper-clad laminate and laminated by pressing, as shown in FIG. Two sets of four-layer laminates were prepared.

A via hole 5 was formed in a connection portion between the third, fourth, fifth, and sixth layers from the copper wiring portion on the upper surface by a UV-YAG laser having a beam diameter of 80 μm. Next, after treatment with a Pb catalyst solution, electroless plating was performed, and further, electrolytic plating was performed. A dry film resist (AQ-2 manufactured by Asahi Kasei Corporation)
588) were laminated, exposed and developed to form fourth and fifth layer circuits.

A prepreg manufactured by Matsushita Electric Works, Ltd. was laminated by pressing so that two sets of four-layer plates were patterned on the fourth and fifth layers, as shown in FIG. An eight-layer printed wiring board was prepared. Further, a via hole 5 is formed between one layer and two layers, and between the n layer and the (n-1) layer, and plated by chemical copper plating or electrolytic copper plating.
After laminating the resist, exposure and development etching were performed to form a circuit pattern.

Thus, as shown in FIG. 3, one layer and two layers,
1 and 3 layers, 1 and 4 layers, 2 and 3 layers, 2 and 4 layers, 3
Layer and four layers, n layer and (n-1) layer, n layer and (n
-2) layer, n layer and (n-3) layer, (n-1) layer and (n-
2) layer, (n-1) layer and (n-3) layer, (n-2) layer and (n-3) layer can be connected, and a high-density wiring board having very high degree of freedom in wiring can be provided. I got it. In addition, a heat cycle test at −65 ° C.⇔125 ° C. was performed 1000 times using the multilayer wiring board, but no delamination or cracking of the board was observed.

[0032]

As described above in detail, according to the multilayer wiring board and the method of manufacturing the same according to the present invention, a multilayer wiring board having three or more n layers has one layer, three layers, and n layers. (N-1) It is possible to obtain a multilayer wiring board having a build-up structure in which connection between layers can be performed at high density and with a small number of steps. Further, since the filling can be performed at the same time as the plating is applied by the build-up method, it is possible to obtain a multilayer wiring board having a structure in which the solder does not blow up without providing a separate filling step.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multilayer wiring board according to a first embodiment of the present invention.

FIGS. 2A and 2B are configuration diagrams each showing a shape of a hole.

FIG. 3 is a configuration diagram of a multilayer wiring board according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of an example of a conventional multilayer wiring board.

FIG. 5 is a configuration diagram of a second example of a conventional multilayer wiring board.

FIG. 6 is a configuration diagram of a third example of a conventional multilayer wiring board.

[Explanation of symbols]

1,2,3,4 ... layers, n, (n-1), (n-2),
(N-3): layer, 5: via hole, 8, 8a, 8b: hole, 9
… Plating filling

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E317 AA24 BB01 BB11 CC33 CC53 CD32 GG16 5E346 AA43 CC04 CC09 CC10 CC32 FF03 FF07 FF15 GG15 GG18 HH32

Claims (5)

[Claims] 1. An apparatus comprising three or more n layers, one layer and two layers,
Layer and three layers, two layers and three layers, n layers and (n-1) layers, n layers and (n-2) layers, and multilayer wirings connecting (n-1) and (n-2) layers, respectively. In the substrate, a hole having a diameter of 40 μmφ or less is formed in an insulating layer between the two layers and the three layers and the (n-1) layer and the (n-2) layer, and the hole is filled with copper plating. A multilayer wiring board, wherein two layers, two layers and three layers, n layers and (n-1) layers, and (n-1) layers and (n-2) layers are connected. 2. A laser drilling is performed on a connection portion between the two and three layers and between the (n-1) layer and the (n-2) layer, which is filled with the copper plating, thereby forming one and two layers. 2. The multilayer wiring board according to claim 1, wherein a connection between the n layer and the (n-1) layer is formed, and a connection between the first layer and the three layers and a connection between the n layer and the (n-2) layer are achieved. 3. The multilayer wiring board according to claim 1, wherein the shape of the hole is an ellipse or an ellipse. 4. There are three or more n layers, one layer and two layers,
Layer and three layers, two layers and three layers, n layers and (n-1) layers, n layers and (n-2) layers, and multilayer wirings connecting (n-1) and (n-2) layers, respectively. In the method for manufacturing a substrate, the one layer and two layers, the one layer and three layers, the two layers and three layers, the n layer and (n
-1) layer, n layer and (n-2) layer, (n-1) layer and (n-
2) a step of drilling holes in the insulating layer between the layers to connect the layers, and a step of filling the holes drilled in the step with a conductive material and performing electroplating, Forming a circuit on the insulating layer in which the holes have been filled in the step; and forming the circuit on the two, three, or (n-1) layers;
(N-2) a step of laminating a wiring layer composed of the one layer, the n layer, and the other layer with an insulating adhesive, and after the lamination, one layer and two layers, and n layer and (n-1) Drilling holes in the insulating layer between the layers, and electroplating by applying a conductive substance to the holes between the one and two layers and between the n layer and the (n-1) layer. A method for manufacturing a multilayer wiring board, comprising: 5. The method for manufacturing a multilayer wiring board according to claim 4, wherein the drilling between the first and second layers and between the n-layer and the (n-1) -layer is performed by laser processing.