JP2002091625A - Bus reset processing method, information processing apparatus, and recording medium - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent a process executed when a bus reset occurs from abnormally stopping when a bus reset occurs continuously. When a bus reset occurs at a timing T25 during execution of an application program 13a, an interrupt handler is activated and a first interrupt routine is executed. At timing T26, the first
Of the interrupt routine is terminated, the execution of the application program 13a is resumed, and the timing T27
, A second interrupt routine is executed. When the bus reset occurs again at the timing T28, the interrupt handler is activated again, and the first interrupt routine is executed. At a timing T29, the execution of the application program 13a is resumed, and thereafter, each interrupt routine and the execution of the application program 13a are repeated, and the application program 13a is executed.
Return to execution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus reset processing method in an information processing device to which an electronic device is connected via a predetermined bus, and to this information processing device.
An electronic device is connected via a predetermined bus, and an operation evaluation device that performs an evaluation process of a communication operation on the bus is
The present invention relates to a bus reset processing method in an information processing device connected via an interface other than the bus.

[0002]

2. Description of the Related Art In recent years, with the advent of digital video devices for home use, it has become necessary to transfer data with a large amount of information such as moving image data and audio data in real time. As a standard of a serial interface capable of transferring such a large amount of data at high speed, IEEE (the Instit
ute of Electrical and Electronic Engineers) 139
Four interfaces are known. This IEEE139
The 4 interface can be widely used for connection between home electric appliances such as digital video devices, as well as peripheral devices for existing personal computers, LANs, internal buses of personal computers, and the like.

An IEEE 1394 serial bus (hereinafter, 1)
In a network system configured using a 394 bus, each device (node) is connected by a twisted pair cable for a 1394 bus. Each node has an ID, and by recognizing the ID with each other, one network is configured in a range connected by the 1394 bus. The 1394 bus is plug /
It has the function of automatically recognizing a node and recognizing the connection status only by connecting a cable to the node. For example, when a node is removed from the network or newly added, etc., the configuration information of the previous network is automatically reset (bus reset) to reconstruct a new network. Specifically, for all connected nodes, I
Reissue D. With this function, it is possible to always set and recognize the configuration of the network at that time.

Here, a process at the time of bus reset in a node connected by a 1394 bus will be described. FIG.
FIG. 9 shows a flowchart of a process at the time of bus reset in the node.

At the start of the flowchart shown in FIG. 5, the node constantly monitors the bus reset signal. Here, when there is a change in the network configuration, for example, when the number of nodes increases or decreases due to connection / disconnection of the node, power on / off, etc., a bus reset signal is output by the node that detects the change in the network configuration. Is sent. In step S501, the transmitted bus reset signal is detected. When the node receives the bus reset signal in the physical layer, the node informs the link layer of the occurrence of the bus reset and relays the bus reset signal to another connected node. Such processing is performed in each node, and when the bus reset signal is finally detected in all nodes, the network rebuilding processing starts.

In step S502, a parent-child relationship is declared between nodes directly connected to each other. In each node, if there is only one node whose parent-child relationship is undefined among other connected nodes, a declaration is made that the other node is a parent. Such a declaration is first made from a leaf node in which only one node is actually connected, and in other nodes, the number of undefined nodes connected as the parent-child relationship is determined is determined. Decreases,
When this number becomes 1, a similar parent-child relationship declaration is made for the remaining undefined nodes. In step S503, as a result of the declaration of the parent-child relationship performed at each node,
The only node where the connected undefined node has become 0,
In other words, the parent node of all connected nodes is determined as the root node. In step S504, an ID is set for each node by the root node. The ID is set for the leaf node first, and then for the branch node and the root node. At this time, the numerical values of the IDs are set in descending order, and the lowest numerical ID is given to the root node. When the IDs are set for all the nodes, the new network configuration is recognized for all the nodes, the bus reset processing ends, and the bus reset signal is again monitored.

[0007]

When a bus reset signal is detected at each node, an interrupt handler is activated, and the above-described interrupt routine for reconfiguring the network is read and executed. If another process is being executed when this bus reset signal is detected, the execution of the interrupt routine interrupts the previous process, and after the bus reset process ends,
The original processing is resumed. For example, if a bus reset signal is detected while a certain application program is being executed on the CPU, an interrupt is generated in the CPU and the execution of the application program is stopped.
FIG. 6 is a time chart showing the operation of the CPU at this time.

FIG. 6 shows processing executed by the CPU along the flow of time t. The arrow 60 indicates the occurrence of a bus reset. In this CPU, an application program is executed until timing T61. When a bus reset occurs at timing T61, a bus reset signal is detected, an interrupt handler is activated, and an interrupt routine is read and executed. The above-described network reconfiguration is performed by this interrupt routine, and when all processes are completed at timing T62, the CPU resumes execution of the application program.

However, at timings T63, 64 and 6
When the bus reset occurs again before the execution of the interrupt routine ends, as shown in 5, an interrupt is generated each time and the interrupt routine is executed. Therefore, the execution of the application program cannot be resumed. At this time, the system operated by the application program is stopped.For example, if the execution of the application program is interrupted and the execution is not resumed for a certain period of time or more, a timeout error occurs and the system operation is forcibly terminated. May be done. Also, RS (Recommended Standard) -232C
The PC is connected to another PC (personal computer) using an interface other than the IEEE 1394 standard. For example, an evaluation application is executed on the connected PC to evaluate the operation of the 1394 serial bus.
If a bus reset occurs while performing data transmission / reception processing by communicating with the PC, communication with the PC is interrupted, and the system on the application side is in a state as if it has failed.

The present invention has been made in view of such a problem, and when a bus reset occurs continuously,
An object of the present invention is to provide a bus reset processing method capable of preventing a process executed when a bus reset occurs from being abnormally stopped.

Another object of the present invention is to provide an information processing apparatus capable of preventing a process executed at the time of occurrence of a bus reset from abnormally stopping when a bus reset occurs continuously. That is.

[0012]

According to the present invention, there is provided a bus reset processing method in an information processing apparatus to which an electronic device is connected via a predetermined bus. Is detected,
A bus reset processing method is provided, wherein a plurality of interrupt routines for performing recognition processing of the electronic device, which are divided for each predetermined processing, are executed at intervals.

In such a bus reset processing method, processing executed when a bus reset occurs is divided into a plurality of interrupt routines, each of which is executed at intervals. If another process is being executed at the time of the bus reset, this process is interrupted by the occurrence of the bus reset, but the previous process is suspended between the end of the processing of each divided interrupt routine and the execution of the next interrupt routine. Can be continuously executed. This makes it possible to prevent the processing interrupted by the occurrence of the bus reset from abnormally stopping.

According to the present invention, there is provided an information processing apparatus to which an electronic device is connected via a predetermined bus, and an operation evaluation device for performing an operation evaluation process of the bus is connected via an interface other than the bus. In the bus reset processing method according to the above, when a bus reset signal is detected via the bus during a communication process of transmitting data indicating an operation state of the bus in response to a transmission request signal from the operation evaluation device, A plurality of interrupt routines for performing the recognition process of the electronic device divided for each process are executed at intervals, and during the transition from the end of the execution of each interrupt routine to the execution of the next interrupt routine, A bus reset processing method is provided, wherein the communication processing is performed again.

In such a bus reset processing method, the processing executed when a bus reset occurs is divided into a plurality of interrupt routines, each of which is executed at intervals. Although the communication processing with the operation evaluation device is interrupted by the occurrence of the bus reset, the communication processing can be executed again in the time from the end of the processing of each divided interrupt routine to the execution of the next interrupt routine. This makes it possible to prevent the communication process from abnormally stopping due to the occurrence of the bus reset.

Further, according to the present invention, in an information processing apparatus to which an electronic device is connected via a predetermined bus, when a bus reset signal is detected via the bus, a recognition process of the electronic device connected to the bus is performed. And a recognition processing unit that divides each recognition process for each predetermined process, and executes each recognition process by the recognition processing unit at a fixed time interval. When the execution of each recognition process is completed, the execution of the next recognition process is started. And a control unit for performing control so as to execute a process which has been performed when the bus reset signal is detected until the bus reset signal is detected.

In such an information providing apparatus, the recognition processing means divides the recognition processing executed when a bus reset occurs into a plurality of pieces, and each of them is executed at regular intervals. If another process is being executed when the bus reset occurs, this process is interrupted by the occurrence of the bus reset.However, the time from the end of execution of each of the divided recognition processes to the start of the next recognition process is determined by the control unit. , The previous processing can be continued. This makes it possible to prevent the processing interrupted by the occurrence of the bus reset from abnormally stopping.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration diagram of an information processing apparatus to which the bus reset processing method of the present invention can be applied.

The information processing apparatus 1 shown in FIG. 1 is connected to a bus 3 to perform an interface (I /
F) 11, when a bus reset signal is detected via the bus 3, a recognition processing means 12a for performing recognition processing of a device (node) connected to the bus 3, and a plurality of divided recognition processing and other processing. It comprises a CPU 12 that realizes a function as a control means 12b for controlling execution and controls the entire apparatus, and a storage device 13 in which application programs and the like are stored. The information processing device 1 executes various processing programs stored in the storage device 13 and the like by the CPU 12,
It is a computer device that realizes the processing. The recognition processing unit 12a and the control unit 12b are realized by being stored in a storage device 13 or a ROM (not shown) as a processing program for performing these processes, and executed by the CPU 12, for example. The information processing device 1
May include an interface 14 for communication using a communication method different from that of the bus 3. This interface 14
Is based on, for example, the RS-232C standard, and is connected to a personal computer (PC) 4. The interface 14 and the personal computer 4 will be described later.

The bus 3 is, for example, an IEEE 1394 serial bus. A node ID is set to each node of the electronic device 2 or the like connected to the bus 3, and when a configuration change of the connected node occurs, the node ID is automatically set to that value. Is reset, the node ID is reset, and each node has a bus reset function of re-recognizing the network configuration. The flow of the node recognition processing at the time of this bus reset is as follows. First, the detected bus reset signal is relayed to other nodes, and when the bus reset signals are detected in all the nodes, they are directly connected to each other. A parent-child relationship is declared between nodes. In each node, if only one of the other connected nodes has an undefined parent-child relationship, a declaration is made that the other node is a parent. This process is performed on all nodes except the root node from the leaf node where only one node is connected. At this time, the only node that finally became the parent of all nodes connected to itself is determined as the root node. Next, when the ID is set for each node by the root node and the setting for all the nodes is completed, the new network configuration by the bus 3 is recognized for all the nodes, and the bus reset processing ends.

In the information processing apparatus 1, when a bus reset occurs, a bus reset signal is detected by the interface 11, and the recognition processing of the node by the recognition processing means 12a is started. Specifically, an interrupt routine for performing recognition processing stored in a ROM or the like is read out,
The processing is executed in the CPU 12. By the way, when another process such as execution of the application program 13a is performed in the CPU 12 when the bus reset occurs, the CPU 12 detects the bus reset signal and executes the process.
12 is interrupted, and C is used to execute the interrupt routine.
Since the PU 12 is occupied, the previous processing is interrupted. For this purpose, the recognition processing unit 12a divides the above-described recognition processing into predetermined processings whose execution is completed in a short time, and sequentially executes the processing at intervals. Each of the divided recognition processes is read and executed by the CPU 12 at regular intervals, for example, by executing a timer handler.

FIG. 2 is a time chart showing the operation of the CPU 12 when a bus reset occurs. In FIG. 2, as an example, the application program 13a
Is performed along the flow of time t when a bus reset occurs during the execution of. Note that arrow 2
0 means that a bus reset has occurred. In the CPU 12, the application program 13a is executed until the timing T21. When a bus reset occurs at the timing T21, a bus reset signal is detected, an interrupt handler is activated, and an interrupt routine for performing network recognition processing is read. Issued and executed. Here, it is assumed that the bus reset processing routine is divided into four. At the timing T22, when the execution of the first interrupt routine ends, the processing is re-executed from the processing routine of the application program 13a that was being executed at the timing T21. At timing T23, the second interrupt routine is read and executed, and the execution of the application program 13a is interrupted. Hereinafter, similarly, the second interrupt routine, the application program 13a, the third
Interrupt routine, application program 13
a, a fourth interrupt routine is sequentially executed, and at a timing T24, the node recognition processing by the interrupt routine ends, and the application program 1
3a is executed.

As described above, when the application program 13a is being executed at the time of occurrence of the bus reset, the recognition processing by the divided recognition processing means 12a is sequentially executed, and the application program 13a is executed between the recognition processing. Is controlled by the control means 12b. As a result, even during the recognition processing due to the occurrence of the bus reset, the application program 13a that has been executed can shift to the next processing.

Next, the operation of the CPU 12 when bus resets occur continuously at short intervals will be described. In FIG. 2, when a bus reset occurs at a timing T25 while the application program 13a is being executed, a bus reset signal is detected, an interrupt handler is activated, and a first interrupt routine is read and executed. You. At timing T26,
When the execution of the first interrupt routine ends, the execution of the application program 13a is restarted. At timing T27, the second interrupt routine is read and executed. Here, if the bus reset occurs again at the timing T28, the interrupt handler is activated again and the first interrupt routine is executed. At a timing T29, the execution of the first interrupt routine ends, and the application program 13a
Is executed, and thereafter, the respective interrupt routines and the execution of the application program 13a are similarly repeated, and after the recognition processing is completed, the normal application program 13a is executed.
Return to the execution of a.

As described above, even if the bus reset occurs again before the completion of the node recognition processing by the interrupt routine, the control of the execution of the routine by the control means 12b causes the plurality of divided recognition processing to be performed during the recognition processing.
The application program 13a is always executed.
For this reason, even if the bus reset occurs continuously before all the recognition processes are completed, the application program 13a that has been executed up to that point does not stay in the stopped state for a long time, and shifts to the next process. It is possible to prevent the execution of the application program 13a from abnormally stopping due to, for example, a timeout error.

Incidentally, the processing at the time of such a bus reset can be applied even during the processing of communication with another device. Returning to FIG. 1, the information processing apparatus 1
Is provided with an interface 14 using a communication system different from that of the bus 3, and an external personal computer 4 is connected via the interface 14. For example, when the personal computer 4 executes an evaluation program for monitoring the operation status of the nodes connected to the interface 11 and the bus 3 of the information processing apparatus 1 and displaying and evaluating these data, In step 1, communication request data is received from the personal computer 4, and various data held or received by the interface 11 is read out by the processing of the CPU 12 and transmitted to the personal computer 4. Processing is performed. The data transmitted to the personal computer 4 is, for example, the number of nodes connected to the bus 3, the register data of the interface 11, the contents of communication data, and the like. For example, the status of the interface 11 is displayed in real time using display means (not shown).

In such a system, since the data displayed on the personal computer 4 is updated in real time, it is necessary that the personal computer 4 and the information processing apparatus 1 communicate with each other one by one. In such a system, when a bus reset is caused by a node connected to the bus 3, the execution of each interrupt routine for the divided node recognition processing is performed similarly to the case where the application program 13a is being executed. To
Communication processing with the personal computer 4 can be performed. Therefore, even if a bus reset occurs continuously before all the recognition processes are completed, the communication process does not stop for a long time due to the execution of the interrupt routine, and the display is abnormally stopped on the personal computer 4 side. However, it does not appear as if the system has failed.

If a bus reset occurs while a communication process is being performed with a node such as the electronic device 2 connected to the bus 3, all recognition processing by the interrupt routine ends. Until this time, the communication process cannot be resumed because the connected node cannot be recognized. However, during the execution of the divided interrupt routine, the CPU 12 can perform processing for displaying, for example, that the bus reset processing is being performed by a display device (not shown). Thus, the user of the information processing apparatus 1 can recognize that the communication processing with the electronic device 2 is temporarily stopped, and that the cause is a bus reset.

Next, as a specific embodiment of the present invention, an operation evaluation system for the bus 3 for monitoring and evaluating the operation status of the bus 3 will be used, and a bus reset process in this system will be described. FIG. 3 shows a schematic configuration example of the operation evaluation system.

The operation evaluation system 10 is based on IEEE 139
4 serial bus (hereinafter abbreviated as 1394 bus) 3a
Target device 5 to which electronic devices 2a and 2b are connected via the target device 5 and the target device 5 and the IEEE 13
It comprises a personal computer (PC) 4 connected using a communication interface other than the 94 standard. In the operation evaluation system 10, by executing an operation evaluation program in the personal computer 4, the 1394 bus 3 in the target device 5 is executed.
a) to control the communication process with a to monitor the operation status and enable evaluation. The connection between the target device 5 and the personal computer 4 is, for example, RS-23 as an example here.
A communication interface conforming to the 2C standard is used, but is not limited to this.

The target device 5 is a 1394 bus 3
a, an IEEE 1394 interface (hereinafter abbreviated as 1394 interface) 51 for transmitting and receiving data, a CPU 52 for controlling the target device 5, a ROM 53 for storing various control programs for operating the CPU 52, and a CPU 52. Is composed of a RAM 54 in which data and programs necessary for executing various processes are appropriately stored, and an RS-232C interface 55 connected to the RS-232C cable 6 to transmit and receive data. The target device 5 executes the control program stored in the ROM 53 by the CPU 52, thereby
An information processing device that performs processing such as communication with external devices via the interface 51 and the RS / 232C interface 55. For example, home electric appliances such as digital video devices and optical disk devices, and sets that integrally control these devices A top box and a computer device such as a personal computer.

The 1394 interface 51 is implemented by a layer structure, and includes a port 51a having a connector for the 1394 bus 3a and a PHY (Physical Layer Protocol) 5 for encoding and decoding input / output signals.
LINK 51c for transmitting and receiving packet data
Composed of PHY 51b is 1394 bus 3
a, decodes the packet data received through the port 51a, outputs the decoded data to the LINK 51c,
The packet data supplied from the K51c is encoded and transmitted to the port 51a. LINK 51c is a PHY
The data included in the packet data supplied from 51b is extracted and output to the CPU 52, and the transmission data is packetized and output to the PHY 51b. The electronic devices 2a and 2b connected via the port 51a are, for example, home appliances such as digital video devices and optical disk devices, set-top boxes for integrally controlling these devices, computer peripheral devices such as printers, and personal computers. And the like, each of which has a communication interface conforming to the IEEE 1394 standard.

On the other hand, the personal computer 4 has a CPU 41 for controlling the personal computer 4.
And a ROM 42 storing various control programs for operating the CPU 41, a RAM 43 storing data and programs necessary for the CPU 41 to execute various processes, and the RS-232C cable 6 An RS-232C interface 44 for transmitting and receiving data, a monitor 45 for displaying various data received from the target device 5, and an auxiliary storage device for storing various processing programs and data such as an operation evaluation program of the 1394 bus 3a. It is constituted by a certain hard disk 46.

The personal computer 4 communicates with the target device 5 by executing the operation evaluation program of the 1394 bus 3 a stored in the hard disk 46 by the CPU 41, and executes the communication processing via the 1394 bus 3 a by the 1394 interface 51. Perform control. Thereby, in the personal computer 4, the register data in the target device 5,
It receives data such as the number of devices such as the electronic devices 2a and 2b connected to the 1394 bus 3a and the contents of communication with these devices. The monitor 45 includes a GUI capable of performing a data transmission / reception operation with the target device 5 together with the data received from the target device 5.
(Graphical User Interface) image is displayed. Communication with the target device 5 is performed one by one, and the content of the received data on the monitor 45 is updated in real time according to the communication status of the target device 5 via the 1394 bus 3a. The communication status of the bus 3a can be monitored and evaluated.

In the target device 5, RS-232
The personal computer 4 communicates with the personal computer 4 via the C interface 55 one by one. Based on a control signal transmitted from the personal computer 4, a communication control program for the 1394 bus 3 a stored in the ROM 53 is transmitted to the CPU 5.
2, the communication using the 1394 bus 3a is controlled. In the 1394 interface 51,
Based on a data transmission request from the personal computer 4, data relating to its own transmission / reception status and connection status with other devices are output under the control of the CPU 52, and these data are transmitted to the personal computer 4.

Here, when a bus reset occurs due to a change in the network configuration of the 1394 bus 3a,
In the target device 5, the interrupt handler stored in the ROM 53 is activated, and the bus reset processing program
The processing is executed by the PU 52 to recognize the nodes on the 1394 bus 3a as described below, and the network is reconfigured. That is, when a bus reset occurs,
When a bus reset signal is transmitted from the 1394 bus 3a, the CPU 52 receives the bus reset signal and relays it to another connected device (node). When a bus reset signal is detected in all nodes, a parent-child relationship is then declared between the nodes directly connected to each other.
In each node, if only one of the other connected nodes has an undefined parent-child relationship, a declaration is made that the other node is a parent. This is performed on all nodes except the root node from the leaf node where only one node is set.
At this time, the only node that finally became the parent of all nodes connected to itself is determined as the root node. Next, this root node communicates with each node,
Set. When the setting for all the nodes is completed, the network configuration on the 1394 bus 3a is re-recognized, and the processing for the bus reset ends.

While the interrupt routine according to the bus reset processing program is being executed, the communication with the personal computer 4 is temporarily stopped. In the operation evaluation system 10, the bus reset processing program is divided into a plurality of interrupt routines for each predetermined processing, and the interrupt handler executes the communication processing routine with the personal computer 4 during the execution of each interrupt routine. Is controlled to be restarted. The interrupt handler reads out and executes each interrupt routine at regular intervals. Thus, if bus resets occur continuously on the 1394 bus 3a before all the bus reset processes are completed, the updating of the communication status data displayed on the monitor 45 of the personal computer 4 is stopped, and the operation is stopped. The evaluation system 10 is prevented from being in an abnormal stop state.

FIG. 4 is a flowchart showing the operation of the target device 5 when a bus reset occurs. In step S401, the CPU 52 executes an arbitrary communication processing routine according to a communication control program with the personal computer 4, and performs communication based on a control signal from the personal computer 4. At the same time, the 1394 interface 51
, The bus reset signal is constantly monitored. In step S402, a bus reset signal is received from the 1394 bus 3a. In step S403, the CP
U52 activates the interrupt handler to start the node recognition process. Here, assuming that n = 0, the reading process of the interrupt routine for performing the node recognition process by the interrupt handler is initialized. Here, it is assumed that the interrupt routine is divided into stages a. Step S4
In step 04, n = n + 1, and in step S405, the n-th interrupt routine for performing the node recognition processing is read out and executed. In step S406, when the processing by the n-th interrupt routine is completed, the execution is resumed from the communication processing routine executed when the bus reset signal was received in step S402, and the communication processing with the personal computer 4 is performed. At this time, first, data for notifying the occurrence of the bus reset may be transmitted to the personal computer 4, and then the communication processing routine may be executed.

In step S407, when the bus reset signal is received again at the time of execution of the communication processing, the flow returns to step S403, where the interrupt handler is activated again to perform the node recognition processing from the beginning. Step S40
If the bus reset signal is not received at the time of 7, the process proceeds to step S408, and it is determined whether or not n is equal to or larger than the number of divisions a of the interrupt routine. If n <a, since all the interrupt routines have not been completed, the process proceeds to step S404, where 1 is added to the value of n, and step S4 is performed.
In steps 05 to 407, execution of the interrupt routine of the next stage, restart of the communication processing routine with the personal computer 4, and detection of the bus reset signal are performed. These processes are repeated until the a-th interrupt routine is executed in step S405. When n ≧ a in step S408, the node recognition process by executing the interrupt routine has been completed. Proceeding to S409, the communication processing routine is continuously executed.

As described above, in the node recognition processing at the time of occurrence of a bus reset in the operation evaluation system 10 for the 1394 bus 3a, from the end of execution of each of the plurality of divided interrupt routines to the start of execution of the next interrupt routine. In the meantime, communication processing with the personal computer 4 is always executed. Therefore, if a bus reset occurs continuously before all the node recognition processes by the interrupt routine are completed, the communication process with the personal computer 4 is continued even during the execution of the node recognition process, and the personal computer 4 139 displayed on the monitor 45 of
The communication status data on the four buses 3a is continuously updated. As a result, it is possible to prevent the personal computer 4 from abnormally stopping communication with the target device 5 for a long time and causing a system breakdown. In addition, data for notifying the occurrence of a bus reset can be transmitted to the personal computer 4 during execution of each interrupt routine. By displaying this data on the monitor 45, the user of the personal computer 4 can display the data. This makes it possible to clearly recognize that even if the communication with the target device 5 is temporarily stopped or the data update speed is reduced, the cause is bus reset generation processing.

The contents of the above bus reset processing can be described in a program recorded on a computer-readable recording medium. Then, by executing this program on a computer, the above processing is realized on the computer. Examples of the computer-readable recording medium include a magnetic recording device and a semiconductor memory. When the program is distributed to the market, the program is stored and distributed in a portable recording medium such as a CD-ROM or a floppy (registered trademark) disk, or stored in a storage device of a computer connected via a network. And transfer it to another computer over the network. When running on a computer,
The program is stored in a hard disk device or the like in the computer, loaded into the main memory and executed.

[0042]

As described above, according to the bus reset processing method of the present invention in an information processing apparatus to which an electronic device is connected via a predetermined bus, a plurality of processes are executed when a bus reset occurs. It is divided into interrupt routines, each of which is executed at intervals. If another process is being executed at the time of the bus reset, this process is interrupted by the occurrence of the bus reset, but the previous process is suspended between the end of the processing of each divided interrupt routine and the execution of the next interrupt routine. Can be continuously executed. This makes it possible to prevent the processing interrupted by the occurrence of the bus reset from abnormally stopping.

Also, the present invention relates to an information processing apparatus in which an electronic device is connected via a predetermined bus, and an operation evaluation device for evaluating communication operation on the bus is connected via an interface other than the bus. In the bus reset processing method, the processing executed when a bus reset occurs is divided into a plurality of interrupt routines, each of which is executed at intervals. Although the communication processing with the operation evaluation device is interrupted by the occurrence of the bus reset, the communication processing can be executed again in the time from the end of the processing of each divided interrupt routine to the execution of the next interrupt routine. This makes it possible to prevent the communication process from abnormally stopping due to the occurrence of the bus reset.

Further, in the information providing apparatus according to the present invention, the recognition processing executed when the bus reset occurs is divided into a plurality of pieces by the recognition processing means, each of which is executed at regular intervals. If another process is being executed when the bus reset occurs, this process is interrupted by the occurrence of the bus reset.However, the time from the end of execution of each of the divided recognition processes to the start of the next recognition process is determined by the control unit. , The previous processing can be continued. This makes it possible to prevent the processing interrupted by the occurrence of the bus reset from abnormally stopping.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an information processing apparatus to which a bus reset processing method of the present invention can be applied.

FIG. 2 is a time chart illustrating an operation of a CPU when a bus reset occurs.

FIG. 3 is a diagram illustrating a schematic configuration example of an operation evaluation system.

FIG. 4 is a flowchart illustrating an operation in a target device when a bus reset occurs.

FIG. 5 is a flowchart illustrating a process at the time of a bus reset in a node.

FIG. 6 is a time chart illustrating an operation of a CPU when a bus reset signal is detected during execution of an application program.

[Explanation of symbols]

1 ... information processing device, 2, 2a, 2b ... electronic device, 3
…… Bus, 3a …… IEEE1394 serial bus, 4
...... personal computer, 5 ... target device, 6 ... RS-232C cable, 10 ... operation evaluation system, 11 ... interface, 12 ... CPU,
12a ... recognition processing means, 12b ... control means, 13 ...
... storage device, 13a ... application program,
14 interface 41 CPU 42 R
OM, 43 ... RAM, 44 ... RS-232C interface, 45 ... Monitor, 46 ... Hard disk,
51: IEEE 1394 interface, 51a ...
Port, 51b PHY, 51c LINK, 52
… CPU, 53… ROM, 54… RAM, 55…
... RS-232C interface

Claims (12)

[Claims] 1. A bus reset processing method in an information processing apparatus to which an electronic device is connected via a predetermined bus, wherein when the bus reset signal is detected via the bus, the electronic device is divided for each predetermined process. A bus reset processing method comprising: executing a plurality of interrupt routines for performing a recognition process at intervals with respective intervals. 2. A process which has been executed when the bus reset signal is detected is continuously executed during a transition from the end of execution of each of the divided interrupt routines to execution of the next interrupt routine. The bus reset processing method according to claim 1. 3. The bus reset processing method according to claim 1, wherein each of said interrupt routines is executed at regular time intervals. 4. The bus reset according to claim 1, wherein when the bus reset signal is detected again before all the processes in the interrupt processing routine are completed, the bus reset is executed again from the initial processing of the interrupt routine. Processing method. 5. The bus reset processing method according to claim 1, wherein said bus is a serial bus conforming to the IEEE 1394 standard. 6. A bus reset in an information processing device to which an electronic device is connected via a predetermined bus and an operation evaluation device for performing an evaluation process of a communication operation on the bus is connected via an interface other than the bus. In the processing method, when a bus reset signal is detected via the bus during a communication process of transmitting data indicating an operation status of the bus in response to a transmission request signal from the operation evaluation device,
A plurality of interrupt routines for performing recognition processing of the electronic device that are divided for each predetermined process are executed at intervals, and during a transition from the end of execution of each interrupt routine to execution of the next interrupt routine. And performing the communication process again. 7. The bus reset processing method according to claim 6, wherein each of the interrupt routines is executed at regular time intervals. 8. The bus reset according to claim 6, wherein if the bus reset signal is detected again before all the processes in the interrupt processing routine are completed, the process is executed again from the initial processing of the interrupt routine. Processing method. 9. The bus reset processing method according to claim 6, wherein said bus is a serial bus conforming to the IEEE 1394 standard. 10. The interface is RS-232C.
7. The bus reset processing method according to claim 6, wherein the interface conforms to a standard. 11. An information processing apparatus to which an electronic device is connected via a predetermined bus, wherein when a bus reset signal is detected via the bus, recognition processing of the electronic device connected to the bus is performed by a predetermined process. A recognition processing unit that divides each process, and executes each recognition process by the recognition processing unit at fixed time intervals. When the execution of each of the recognition processes is completed, the recognition process unit starts executing the next recognition process. Control means for controlling so as to execute processing which has been executed at the time of detection of the bus reset signal. 12. In a computer-readable recording medium recording a bus reset processing program in an information processing device to which an electronic device is connected via a predetermined bus, when a bus reset signal is detected via said bus, A recognition processing unit that performs recognition processing of the electronic device connected to the processing unit by dividing the recognition processing for each predetermined processing, causing each recognition processing by the recognition processing unit to be executed at fixed time intervals, and when the execution of each recognition processing ends. A bus reset processing program characterized by causing a computer to function as control means for performing control so as to execute processing that was being performed when the bus reset signal was detected until the next execution of the recognition processing was started. Computer readable recording medium.