JP2002090421A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an economical semiconductor testing device which can obtain a higher degree of freedom than in conventional techniques and which can easily deal with a device under test (DUT) using an asynchronous signal. SOLUTION: The semiconductor testing device is constituted in such a way that a plurality of per-pin-type electronics parts which output a required test pattern to the DUT and which are equipped with a decision function to compare a response output from the DUT by the test pattern with a reference voltage so as to be decided are formed as an independent pin electronics group on which a reference signal generator to generate individual reference signals and a pattern generator to individually generate the test pattern are mounted individually and in which the respective pin electronics parts can execute pattern generation sequences different at independently different timings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for performing a logical function test of a device under test, and more particularly to the generation of a test pattern.

[0002]

2. Description of the Related Art Conventionally, semiconductor test equipment (hereinafter referred to as tester)
In the device under test (hereinafter referred to as DUT)
As a typical configuration of a device for performing a logic function test (hereinafter referred to as “test”), there are a shared type, a per-pin type, and an intermediate type. FIG. 9 shows a configuration example of a shared type tester, and FIG. 10 shows a configuration example of a perpin type tester.

In FIG. 9, a shared type tester is:
A controller 1 for controlling each part of the tester main body 30, a RATE generator 2 for generating a reference signal RATE, a sequence control unit 3 of a pattern generator (hereinafter referred to as PG) for generating a test pattern in synchronization with the reference signal RATE, a reference signal R
A PG timing generator (TG) 4 for generating a plurality of timings synchronized with the ATE, a plurality of reference voltage generators 5, a PG pattern memory 6 for storing a test pattern for each pin, and finally a signal to the DUT 8 Apply D
A pin electronics (hereinafter referred to as PE) group 7 containing a plurality of pin groups for comparing and determining the response from the UT 8.

In FIG. 10, a perpin type tester is
A controller 1 that controls each part of the tester main body 31, a RATE generator 2 that generates a reference signal RATE, a sequence control unit 3 of a PG that generates a test pattern in synchronization with the reference signal RATE, and a PG that stores a test pattern for each pin And a PE 7 containing a plurality of pin groups that finally apply a signal to the DUT 8 and compare and determine the response from the DUT 8. The TG 4 in the shared tester and the reference voltage generator 5 are included in each PE in the per-pin tester.

[0005]

Generally, a per-pin type tester has a TG and a reference voltage generator for each PE as compared with a shared type tester, so that the degree of freedom and expandability is high, and the test speed is high. Although it is easy to implement, there is a disadvantage that it is expensive. In any type of tester, the RATE generator 2 and the PG sequence control unit 3
The test pattern is common to a plurality of PEs, and the test pattern has to be similarly divided for all pins in the time axis direction. Therefore, when the number of pins of the DUT 8 increases, the combination of pin patterns increases exponentially, and the capacity of the pattern memory 6 becomes enormous.

Further, in the DUT 8 having pins whose timing change points of the input pattern change in a complicated manner, it is difficult to equally divide the test patterns of all pins in the time axis direction. High operating speed is required, and at the same time, PE requires several waveform modes and multiple timing edges. For each timing edge, it is possible to eliminate dead band over multiple cycles and make comparison judgment. In addition, a circuit such as a plurality of counters and delay lines, which seem to be redundant at first glance, is required, and there is a disadvantage that the circuit scale becomes complicated and large.

FIG. 11 shows each pin electronics body 9-1 to 9 of a conventional per-pin type pin electronics group 9.
The configuration example of -n is shown about the typical example 9-1. FIG.
A driver 10 for applying an input waveform to the DUT 8; a comparator 11 for outputting a comparison result of comparing the output waveform from the DUT 8 with a reference voltage from the reference voltage generator 5 to capture the output waveform from the DUT 8; 4 is a timing generator (T) that generates a plurality of timing edges based on the reference signal RATE.
G), 12 are 1/0 signal to driver 10 and ON / O
A waveform generating unit for generating an FF signal;
The comparison determination unit 5 for determining the comparison result of 1 is the reference voltage generator 5 described above. In general, two or three timing edges to generate a 1/0 signal to the driver 10 and one or two timing edges to generate an ON / OFF signal to the driver 10 are used to make a comparison judgment. One to two timing edges are required, for a total of four to seven timing edges.

FIG. 12 shows a method of forming a pattern using a conventional tester. In FIG. 12, the target DU
T indicates that pin 1 is 80 ns, pin 2 is 100 ns, pin 3
Is the case of a device having 16 input pins, such as 120 ns, in which the cycle of the input pattern of each pin differs every 20 ns. In the case of such a DUT, as shown in FIG.
.. must be separated by the RATE cycle of z (= 10 ns cycle), the patterns differ one by one, and at pin 1, pin 2,. , 6, ... 18, it is difficult to compress repeats and loops,
The depth is about 510 k steps (the least common multiple of (4, 5, 6,... 18)).

In general, a PG sequence control unit has a control memory of several tens of bits per cycle, and executes one instruction per cycle. FIG. 13 shows a configuration example of a sequence control unit 3 of a conventional PG. In FIG. 13, 14 is R
A program counter (hereinafter, PC) 15 that operates in synchronization with the ATE signal is a control memory that uses the count value of the PC 14 as an address. The bit configuration of the control memory 15 is divided into "instruction code" and "operand", and "real-time control" such as real-time timing switching, and one address has a bit width of several tens of bits. 16
Is an instruction decoder for analyzing the instruction code of the control memory,
Reference numeral 7 denotes a counter used for repeat or loop.
Since the count value of the PC 14 is used as an address of the pattern memory 6, pattern sequence control (compression of a pattern by repeat, loop, or the like) is performed by operating the PC 14 according to an instruction code. That is, when creating a test pattern, all the pins of the DUT 8 are synchronized with the pin that operates at the highest speed because all the pins are divided in the time axis direction in the same manner in accordance with the pin that operates at the highest speed. A major drawback is that only tests can be performed, and DUTs 8 having asynchronous signal pins cannot be tested.

An object of the present invention is to provide an economical semiconductor test apparatus which can provide a higher degree of freedom than the prior art and can easily cope with a DUT using an asynchronous signal.

[0011]

The semiconductor test apparatus according to the present invention can realize a more flexible and inexpensive tester by including the RATE generator and the PG in the PE of the perpin type tester. That is, the main feature of the present invention is that the RATE generator and the PG are mounted on the PE of the perpin type tester. In other words, the semiconductor test apparatus according to the present invention has a plurality of determination functions that output a necessary test pattern to the device under test and determine a response output from the device under test based on the test pattern by comparing the response output with the reference voltage. Each of the per-pin type pin electronics has a reference signal generator for generating an individual reference signal and a pattern generator for individually generating the test pattern based on the individual reference signal. Are configured to be a group of independent pin electronics that can execute different sequences of pattern generation at different independent timings.
With this method, it is possible to create an inexpensive tester by preventing an increase in the pattern memory, which is a drawback of the conventional device, and by reducing the circuit scale of the TG of the perpin type PE. Testing of DUTs with asynchronous signal pins is also possible.

[0012]

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, each PE can operate independently at an individual frequency, and can cooperate if necessary. That is, the sequence of the individual pattern generation at the individual timing is
The independent pin electronics group may include a coordination control unit for operating in synchronization with each of the pin electronics, and the independent pin electronics group may be configured as an independent cooperative pin electronics group. Furthermore, the pattern generator in each of the pin electronics includes a sequence control unit that controls generation of the necessary test pattern in synchronization with a reference timing of the reference signal, and the sequence control unit includes
A program counter for counting the pulses of the reference timing, and the necessary pattern is selected by using the count value of the program counter as an address so that the sequence of the required pattern generation is controlled for each pin. Can be configured. The cooperative control unit includes a scan pattern generation synchronization control unit that generates a scan pattern at a pin electronics designated as a scan pin among the pin electronics and holds other pin electronics not designated at the scan pin in a hold state. Can be provided. The coordination control unit sends a loop instruction for inquiring whether or not a match with the pattern has been obtained for each of the pin electronics, and allows the corresponding pin electronics to reply that the match has been made, and a match to be taken. Means can be provided.

[0013]

FIG. 1 shows an example of the structure of an independent and cooperative pin electronics body 19 in a device according to the present invention. In FIG. 1, reference numeral 10 denotes a driver bar for applying an input waveform to the DUT 8,
11 is the DUT for taking in the output waveform from the DUT 8
A comparator that outputs a comparison output by comparing an output waveform from the UT 8 with a reference voltage from the reference voltage generator 5, 2 is a RATE generator, 4 is a TG timing generator, and 3a controls a sequence of generating a pattern for each pin. 6 is a pattern memory storing a “pattern” for each pin, and 12 is a 1
Waveform generation unit for generating a / 0 signal and an ON / OFF signal,
Reference numeral 3 denotes a comparison / judgment unit for judging a comparison output from the comparator 12, and reference numeral 5 denotes the above-described reference voltage generator. As described above, the RATE timing generated by the RATE generator 2 is supplied to the sequence control unit 3a, and the RATE timing is generated.
The sequence control unit 3a operates in synchronization with the timing. "Address" output from the sequence control unit 3a
The signal is supplied to the pattern memory 6, and the pattern memory 6
It is possible to control the sequence of pattern generation from each pin. At the same time, the TG timing generated by the timing generator 4 and the “pattern data” output from the pattern memory 6 are compared with the waveform generation unit 12 and the comparison determination unit 13.
To generate a pattern at a different frequency for each pin.

FIG. 2 shows a cooperative control unit 23 in the apparatus of the present invention.
The following shows an example. The cooperative control unit 23 is prepared separately from the sequence control unit 3a of each of the independent cooperative pin electronics main bodies 19-1 to 19-n, and operates in cooperation with the sequence control unit 3a. In FIG.
2 is a RATE generator for operating the coordination control unit 23, 3b is a sequence control unit for controlling the operation sequence of the coordination control unit 32, 15 is a control memory storing a "control code" of the sequence control unit 3b, and 20 is a control memory. A SCAN pattern generator that generates a SCAN pattern in accordance with an instruction from the sequence control unit 3b, 22 is a simultaneous measurement match control unit that controls the measurement and match function of a plurality of DUTs 8, 21 is a synchronization control unit, and 19 is an independent cooperative pin electronics. Group. The RATE generator 2, the sequence control unit 3b, and the control memory 15 are configured by diverting the control code of the RATE generator 2, the sequence control unit 3a, and the control memory 15 of the independent cooperative pin electronics bodies 19-1 to 19-n as they are. can do.

FIG. 3 shows an embodiment of a tester main body composed of independent cooperative pin electronics according to the present invention. In FIG. 3, 1 is a controller for controlling each part of the tester, 23 is a cooperative control unit, 19 is an independent cooperative pin electronics group, 6 is a pattern memory for storing a pattern for each pin, and 8 is a DUT.

RATE generator 2 and T in the apparatus of the present invention
G4 and the operations of the waveform generation unit 12 and the comparison determination unit 13 will be described first. In the device of the present invention, the RATE generator 2 and the TG 4 mounted on the PE can use the TG of the PE of the conventional perpin type tester, whereas the conventional PE needs to generate a plurality of timings. Therefore, since the PE in the device of the present invention can operate independently of the other PEs, only the timing of one change point needs to be generated for each pin, and the time between the change points is changed. If it is one cycle, it is impossible to extend over a plurality of cycles, and the circuit scale can be significantly reduced. For example, in the PE of the present invention, the RATE generator 2 and 1 to 2
Just by having TG4s, it is possible to perform pattern generation and comparison judgment equivalent to those of the conventional PE. Here, input pins, output pins, and bidirectional pins of the DUT 8 in the case where one TG 4 is provided and the pattern memory 6 has 3 bits per PE will be described sequentially.

FIG. 4 shows the case of an input pin. The input pattern of the pin 1 is only a repetition of 1/0, and the reference signal RA of the RATE generator 2 is
An input waveform is generated by adjusting the timing of TE. Further, in a standard input pattern of the pin 2 such as a clock input of the DUT 8, an RZ waveform or the like can be generated at the RATE timing and the TG timing. At this time, two bits of the 3-bit pattern data are RATE and T, respectively.
Used as 1/0 data at G timing.

FIG. 5 shows the case of an output pin. The output pattern of pin 1 is merely a repetition of the comparison and determination with respect to the response timing from DUT 8,
The comparison determination is performed by adjusting the timing of the reference signal RATE of the ATE generator 2. Also, like pin 2, RATE
Window comparison is also possible between timing and TG timing. At this time, two bits of the pattern memory 6 are used as expected value (H, L, Z, X) data.

FIG. 6 shows the case of a bidirectional pin. The input / output pattern of the pin 1 at this time includes input / output switching timing, 1/0 switching timing at the time of input, and comparison determination timing at the time of output. In this case, the reference signal R of the RATE generator 2 is set at the input / output switching timing.
The TG timing TG1 is used as the 1/0 switching timing at the time of input and the comparison / determination timing at the time of output by adjusting the ATE timing. At this time, one bit of the pattern data is used for switching input / output at the RATE timing, and the remaining two bits are used as 1/0 data or expected value data as described above.

In any case, in the first cycle of the test, the RATE generator 2 is synchronized with the 1/0 switching timing, the comparison / determination timing, and the input / output switching timing. Has offset timing. This can be achieved by using the real-time timing switching (timing on the fly) function of the conventional TG of the perpin-type PE as it is. Further, the offset timing is also used to correct the variation (SKEW) in the timing of each PE.

In general, the logic circuit portion of the PE is often constructed by developing a custom LSI. In particular, the PE of a per-pin type tester requires a high timing accuracy of the TG, so that the circuit configuration of the TG section is complicated. It is also subtle and large-scale, and consumes a lot of power. In the present invention, by reducing the number of circuits in the TG section, a custom L
Critical timing paths can be reduced in the creation of SI, accuracy can be easily increased, and the circuit scale can be reduced, which is advantageous in terms of cost. In addition, there is an advantage that power consumption during operation can be reduced.

Next, compression of a test pattern will be described. FIG. 7 shows a pattern creation method according to the present invention. If a repeat or a loop is used by setting RATE at 1/0 timing for each pin, each pin can be controlled by repeating 1/0 two steps. it can. That is, in the apparatus of the present invention, the PG mounted on the PE only needs to operate independently for each pin, irrespective of the other pins. Therefore, NOP (increment of pattern), repeat (repetition of the same pattern), A simple function such as a loop (repetition of a plurality of patterns) is sufficient. Further, pattern compression can be sufficiently expected, and the pattern memory 6 requires much smaller capacity than a conventional tester. The overall compression ratio is several tens to several hundredths.

Further, even if the conventional RATE division method as shown in FIG. 12 is used, the pattern can be compressed for each PG according to the present invention. For example, the pin 1 in FIG. It is only necessary to loop the repeat of the section "1" and the repeat of the four "0" sections, and to loop the five sections of "1" and "0" at the pin 2, respectively. By preparing a simple conversion tool, it is possible to easily cope with pattern resources created by a conventional method. Similarly, in a DUT having an input pin (such as an address pin of a memory IC) that doubles the frequency of an input pattern, a conventional specialized PG function such as an ALPG (algorithmic PG) is used. However, the PE of the present invention can easily cope with the ALP.
G is unnecessary.

In many cases, the creation of a test pattern requires C
It is necessary to convert the pattern generated from the AD system according to the function unique to the tester. However, the pattern generated from the general CAD system is in the form of a timing description of a change point for each pin. The pattern generation scheme in is very well adapted and requires no conversion.

The operation of the PG sequence control section 3a will be described. In the present invention, one object is to reduce the size of the pattern memory and reduce the cost. If the control memory 15 of the PG has a bit width of several tens of bits for each PE as in the related art, This object of the invention cannot be achieved. Therefore, the PG is configured to execute one instruction in a plurality of cycles, and the size of the control memory 15 is reduced by transferring, for example, the contents stored in the control memory 15 one bit at a time.

FIG. 8 shows an example of the configuration of the PG sequence control section 3a in the apparatus of the present invention. In FIG. 8, 14 is RA
A program counter (hereinafter, PC) 15 that operates in synchronization with the TE signal is a control memory that uses the count value of the PC 14 as an address. The bit structure of the "control code" is 1 bit, and the instruction code and operand of the conventional control memory and "real-time control" data corresponding to real-time timing switching are sequentially output. Reference numeral 16 denotes an instruction decoder for analyzing the instruction code of the "control code" converted in parallel, reference numeral 17 denotes a counter used for loops and repeats used for repeats and loops, and reference numeral 18 denotes a serial / parallel converter.

The SCAN test and the match function by the coordination control unit 23 will be described. For many DUTs, the DUT
It is also true that each of the pins operates in synchronization with a clock applied to a certain pin.
Each PE also needs to be able to operate in a coordinated manner, such as a match function that generates a pattern in response to the response of the UT. In the present invention, by setting the RATE generator 2 of all PEs to the same setting, each PE can operate in synchronization.

In the case of the SCAN test, pins other than those designated as the SCAN pins hold the state of 1/0. In the present invention, the cooperative control unit 23 is used for all PEs.
Send HOLD instruction signal from other than SCAN pin to HOLD
Set to D state. Next, in case of match function, DU
The group of PEs assigned for each T repeats the pattern loop until a match is obtained. In the present invention, DU
Whether or not a match has been obtained for each T is collected from each PE.
A loop instruction signal will be sent to each PE group assigned to each UT. In the conventional match function, since the PG is common, when a plurality of DUTs are matched, a clock is stopped in the matched DUTs, and a wait is performed until all DUTs can be matched. Although a circuit or the like was required, such control of queuing is not required in the present invention.

When the SCAN pattern is used, all the PEs operate in a coordinated manner, the sequence control as the master is a repetition of a repeat command except for the instruction of the SCAN pattern, and the pattern for each pin is the sequence control for each PE. Individual compression is performed in the unit 3a. Sequence control unit 3b
Sends an instruction to generate a SCAN pattern,
From the N pattern generator 20, the SCAN pattern and HOL
D instruction is sent to each PE, and P
In E, the pattern data held for each PE is switched to SCAN pattern data to generate a pattern, and SCAN is performed.
PEs other than pins are in the HOLD state.

From the group of PEs assigned to each DUT 8, PASS / FAIL signals are collected by the match measurement control unit 22, and a PASS / FAIL determination for each DUT 8 is performed. For match function, match P for each DUT
The ASS / FAIL signals are similarly collected, and a match loop instruction is sent to each PE from the simultaneous measurement match control unit 22 for each DUT. In such a case, the PEs perform a cooperative operation within the group of PEs for each DUT.

Also, the sequence control unit 3a of each PE can hold HOLD until all the PEs operate in cooperation with each other until they are synchronized with each other.
A HOLD signal is supplied to each PE from the synchronization control unit 21,
A flag indicating the HOLD state is sent from each PE to the synchronization control unit 21. When all the PEs are in the HOLD state, the synchronization control unit 21 lowers the HOLD instruction signal, and the PEs can start individual operations again.

[0032]

As described in detail above, the tester composed of PE according to the present invention can obtain much higher degree of freedom than the prior art because each pin electronics can operate completely independently. DUT with asynchronous signal
Can be easily dealt with. Further, it is possible to flexibly cope with a conventional test method. The ability to compress the test pattern for each pin can prevent an increase in pattern memory capacity and can be expected to have a significant effect on cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an independent cooperative pin electronics main body used in a device of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a cooperative control unit used in the device of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a tester configured by using an independent cooperative pin electronics group and a cooperative control unit according to the apparatus of the present invention.

FIG. 4 is a time chart showing an example of input pin pattern generation in the device of the present invention.

FIG. 5 is a time chart illustrating an example of output pin pattern generation in the device of the present invention.

FIG. 6 is a time chart showing an example of generation of a bidirectional pin pattern in the device of the present invention.

FIG. 7 is a time chart showing how to divide a pattern used in the apparatus of the present invention.

FIG. 8 is a block diagram illustrating a configuration example of a sequence control unit used in the device of the present invention.

FIG. 9 is a block diagram showing a configuration example of a conventional shared tester.

FIG. 10 is a block diagram showing a configuration example of a conventional perpin type tester.

FIG. 11 is a block diagram showing a configuration example of a pen electronics body of a conventional perpin type tester.

FIG. 12 is a time chart showing how to divide a pattern in a conventional method.

FIG. 13 is a block diagram illustrating a configuration example of a sequence control unit used in a conventional method.

[Explanation of symbols]

Reference Signs List 1 controller 2 RATE generator 3, 3a, 3b sequence controller 4 timing generator (TG) 5 reference voltage generator 6 pattern memory 7 shared pin electronics group 8 DUT 9 per pin type pin electronics group 9-1 to 9-n Par pin type pin electronics body 10 Driver 11 Comparator 12 Waveform generation unit 13 Comparison judgment unit 14 Program counter (PC) 15 Control counter 16 Instruction recorder 17 Loop, repeat counter 18 Serial / parallel converter 19 Independent coordination pin electronics group 19-1 19-n Independent cooperative pin electronics main unit 20 SCAN pattern generator 21 Synchronous control unit 22 Synchronous match control unit 23 Cooperative control unit 30 Shared type tester main unit 31 Per pin type Star body

Claims (5)

[Claims] 1. A plurality of per-pin type pin elects having a determination function of outputting a required test pattern to a device under test and comparing a response output from the device under test with the test pattern with a reference voltage. For each of the nics, a reference signal generator for generating an individual reference signal and a pattern generator for individually generating the test pattern based on the individual reference signal are individually mounted, and each pin electronics has independent timing. A semiconductor test apparatus configured to be a group of independent pin electronics that can execute different pattern generation sequences. 2. The independent pin electronics device according to claim 1, further comprising: a coordinating control unit configured to cause the individual pattern generation sequence of the individual timing to operate in synchronization with each pin electronics of the independent pin electronics group. The semiconductor test apparatus according to claim 1, wherein the electronics group is configured to be an independent cooperative pin electronics group. 3. The pattern generator in each of the pin electronics includes a sequence control unit that controls generation of the necessary test pattern in synchronization with a reference timing of the reference signal. A program counter for counting the pulses of the reference timing, and the necessary pattern is selected by using the count value of the program counter as an address, so that the sequence of the required pattern generation is controlled for each pin. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is configured as follows. 4. The scan control unit according to claim 1, wherein a scan pattern is generated in the pin electronics specified as the scan pin among the pin electronics, and the other pin electronics not specified in the scan pin are set to the hold state. 3. The semiconductor test apparatus according to claim 2, further comprising a pattern generation synchronization control unit. 5. The cooperative control unit sends a loop instruction for inquiring whether or not a match with the pattern has been obtained for each of the pin electronics, and allows the corresponding pin electronics to reply that a match has been obtained. 3. The semiconductor test apparatus according to claim 2, further comprising a matching means for performing a match.