JP2002083976A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of preventing electric field concentration near a breakdown voltage structure, securing a stable breakdown voltage, and reducing the resistance of a trench. A pn diode section and an anode electrode are provided.
And a Schottky diode portion B formed of an n ⁻ drift layer 3 and a semiconductor rectifying element having an MPS structure arranged in parallel, the end portion of the innermost circumference of the guard ring facing the trench groove 4 of the p ⁺ layer 8. , P of the trench groove 4 formed on the outermost periphery
^When the distance between the ⁺ layer 8 and the opposite end is W1 and the distance between the trenches is L1, W1 ≦ L1 ensures a stable breakdown voltage. Further, the trench groove is formed in a ring shape so that no void is generated in the polysilicon filling the trench groove, so that the resistance of the trench groove portion is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as a power semiconductor rectifier (power diode).

[0002]

2. Description of the Related Art Power diodes have been used for various purposes. In recent years, power diodes of several kHz to several tens of kHz have been used in inverter circuits operating at relatively high frequencies. Was. There is a strong demand for power diodes used in such high-frequency operation to have a high switching speed. A conventional power diode is mainly a pn diode, and this diode secures a breakdown voltage at a pn junction, compared to a Schottky diode that secures a breakdown voltage at a Schottky junction.
Low leakage current. However, a pn diode is
During the ON operation, the minority carriers are excessively accumulated in the n-base layer, and the accumulated carriers need to be swept out during the reverse recovery operation. This takes time to sweep out the carriers, and the switching speed is reduced. In order to speed up the process, a lifetime killer is introduced into the n-base layer by diffusing heavy metals such as gold atoms and platinum atoms or by irradiating an electron beam to increase the speed of the device.

Recently, an MPS (Merg) in which a pn diode and a Schottky diode are arranged in parallel in one chip.
2. Description of the Related Art A power semiconductor rectifier (power diode) having an ed pin / Schottky Diode structure has been disclosed. In this MPS structure, JP-A-60-31
In the planar type disclosed in Japanese Patent No. 271, the leakage current increases because the electric field intensity at the Schottky junction cannot be suppressed sufficiently low. In order to solve this problem, a structure in which a trench is formed, a pn junction is formed at the bottom of the trench and, in some cases, a side surface, and a Schottky junction is formed at the surface between the trenches is disclosed in Japanese Patent Application Laid-Open No. HEI 9-64139. 5-
No. 63184, JP-A-5-110062, and JP-A-5-226638.

A trench groove is formed in the active region of the power diode having the trench type MPS structure, a pn junction is formed at the bottom of the trench groove, an insulating film is formed on the side surface, and a mesa (convex portion) is formed. ) Discloses that a Schottky diode is formed, but does not discuss the relationship between the breakdown voltage structure and the active region. Usually, a guard ring or a field plate is employed for a breakdown voltage structure arranged so as to surround the active region.

When a reverse bias is applied to the trench type power diode having the MPS structure, the portion between the trenches in the active region is depleted, and the breakdown voltage is secured.
In order for the depletion layer to reach the breakdown voltage structure and for the breakdown voltage structure to work effectively, the distance between the breakdown voltage structure and the trench adjacent to the breakdown voltage structure is important.

[0006]

If the distance between the trench and the withstand voltage structure (guard ring or field plate) is too large, the depletion layer will not easily reach the withstand voltage structure, and the electric field intensity will increase at this point. Will be destroyed. Also, the planar shape of the trench groove is circular and narrow,
If the depth is too deep, cavities are generated in the polysilicon filling the trench, and the resistance of the trench is increased.

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device capable of preventing a concentration of an electric field near a breakdown voltage structure and securing a stable breakdown voltage, or a semiconductor device capable of reducing the resistance of a trench. Is to do.

[0008]

In order to achieve the above object, a plurality of trenches are formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, and a plurality of trenches are formed in a bottom portion of the trench. A second conductivity type anode layer, a Schottky junction formed on the surface of the semiconductor substrate sandwiched between the trench grooves, and a breakdown voltage structure formed on the periphery of the semiconductor substrate.
In a semiconductor device having a cathode layer formed on a surface layer of a second main surface of a semiconductor substrate, a longest interval between an inner end of the breakdown voltage structure and the trench groove arranged on the outermost periphery is set to be equal to or less than the trench groove interval. Configuration.

A plurality of trenches formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, an anode layer of a second conductivity type formed at the bottom of the trench, and A semiconductor having a Schottky junction formed on a surface of a semiconductor substrate sandwiched therebetween, a breakdown voltage structure formed on a peripheral portion of the semiconductor substrate, and a cathode layer formed on a surface layer of a second main surface of the semiconductor substrate In the apparatus, the longest distance between the inner end of the pressure-resistant structure and the anode layer disposed on the outermost periphery is set to be equal to or less than the anode layer distance.

A trench groove selectively formed in a surface layer of the first main surface of the semiconductor substrate of the first conductivity type; an anode layer of a second conductivity type formed at the bottom of the trench groove; A Schottky junction formed on the surface of the island-shaped semiconductor substrate surrounded by the trench groove, a breakdown voltage structure formed on a peripheral portion of the semiconductor substrate, and a surface layer formed on the second main surface of the semiconductor substrate; In a semiconductor device having a cathode layer,
The longest distance between the inner end of the pressure-resistant structure and the anode layer disposed on the outermost periphery is set to be equal to or less than the anode layer distance.

It is preferable that the width of the anode layer is wider than the width of the trench. Further, the pressure-resistant structure may be a guard ring or a field plate. Further, the diffusion depth of the p ⁺ layer is equal to the first depth of the bottom of the anode layer.
It should be deeper than the depth from the main surface. A plurality of trenches formed in the surface layer of the first main surface of the semiconductor substrate of the first conductivity type, an anode layer of the second conductivity type formed at the bottom of the trench, and sandwiched between the trenches; In a semiconductor device having a Schottky junction formed on a surface layer of a semiconductor substrate and a cathode layer formed on a surface layer of a second main surface of the semiconductor substrate, the planar shape of the trench is ring-shaped. Good.

[0012]

1A and 1B show a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line XX of FIG. FIG. In the following description of a series of figures, the plan views are all views on the semiconductor surface, and the anode electrode 10 and the metal film 11 are not shown.

[0013] The semiconductor rectifier element to form an intermediate layer 2 of n-type is epitaxially grown on the n ⁺ cathode layer 1, as a little lower than the concentration of n intermediate layer 2, was further epitaxially grown, n ^- drift layer Get 3.
Here, the presence or absence of the n intermediate layer 2 is not important, and only the n ⁻ drift layer 3 may be used. Trench grooves 4 are formed at equal intervals in the n ^- drift layer 3, and an oxide film (an oxide film 5 on the side wall is shown in the figure) is formed on the side wall and bottom of the trench groove 4. The oxide film is removed.

Thereafter, the polysilicon 6 is filled, and an oxide film in which a portion of the polysilicon 6 (not shown) is opened is used as a mask to pass through the polysilicon 6 at 100 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . Boron is implanted and heat-treated to form a p ^- anode layer 7. An anode electrode 10 is formed on the surface. The anode electrode 10 and the surface of the n ^- drift layer 3 are formed such that a Schottky junction is formed. At this time, the surface of the polysilicon 6 and the anode 1
0 makes ohmic contact.

In this way, p^-Anode layer 7 and n^-
A pn diode portion A formed by the drift layer 3;
Electrode 10 and n^-Shot formed by drift layer 3
Half of the MPS structure in which the key diode portions B are arranged in parallel
A conductor rectifier is formed. Here are the specifications of the element
explain. Trench depth 3μm, trench groove width 3μ
m, mesa width L1 (portion forming Schottky junction 16)
Is 5 μm, p ^-The diffusion depth of the anode layer 7 is 0.5
μm, n^-The concentration of the drift layer 3 is 1 × 10¹⁴cm^-3, N
⁺The concentration of the cathode layer 1 is 1 × 10¹⁸cm^-3It is. this
A guard ring, which is a breakdown voltage structure 14, is provided around the active region 13.
P⁺A plurality of layers 8 are formed, and the junction depth
Is about 8 μm.

The distance between the end of the innermost p ⁺ layer 8 of the guard ring facing the trench groove 4 and the end of the outermost trench groove 4 facing the p ⁺ layer 8 is W1. And when the interval between the trench grooves is L1, W1 ≦ L1
By doing so, the withstand voltage can be ensured as described later with reference to FIG. At this time, it is desirable that the diffusion depth (junction depth) of the p ⁺ layer 8 be deeper than the depth of the trench groove 4 in order to ensure the withstand voltage. This is because if the depth of the trench groove 4 is shallow, if the diffusion depth of the p ⁺ layer 8 is reduced as well as the depth of the shallow trench groove 4, there is a possibility that the breakdown voltage in the guard ring portion may not be secured.

The width of the p ^- anode layer is substantially the same as the width of the trench. If the trench groove intervals L1 are not equal, L1 is the longest interval. In the figure, 9 is an insulating film, and 11 is a metal film. still,
As a pressure-resistant structure, a field plate may be arranged outside the illustrated guard ring. FIG. 2 is a diagram showing a case where the trench groove 4 is in contact with the p ⁺ layer 8 and W1 = 0, and FIG.
FIG. 14 is a diagram showing a case where a part of the layer enters a ⁺ layer 8. Also in this case, W1 ≦ L1 is satisfied, so that the withstand voltage can be secured.

The diffusion depth of the p ⁺ layer 8 is
Is deeper than the depth of the bottom of the p ⁻ anode layer 7 formed at the bottom of the substrate (the depth of the mesa from the surface of the n ⁻ drift layer 3), the trench groove 4 and the p ⁻ anode layer 7 are in the p ⁺ layer 8. , The distance between the trench groove adjacent to the trench groove 4 and the p ⁺ layer 8 is equal to or less than W1 so that the breakdown voltage can be ensured.

[0019] Figure 4, in the semiconductor device of FIG. 1, p ⁺
FIG. 5 is a diagram showing a relationship between a distance W1 between a layer 8 and a trench groove 4 and a breakdown voltage. When W1 is larger than the trench interval L1, the breakdown voltage decreases. This is because the trench 4 located at the outermost periphery
This is because the depletion layer extending from the p ⁻ anode layer 7 to the n ⁻ drift layer 3 at the bottom of the layer does not easily reach the p ⁺ layer 8, and the electric field intensity increases at this point. From this, as described above, it is understood that the withstand voltage is ensured when the distance W1 between the p ⁺ layer 8 and the trench groove 4 arranged on the outermost periphery is equal to or less than the trench groove distance L1.

FIGS. 5A and 5B show a semiconductor device according to a second embodiment of the present invention. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view of an essential part taken along line XX of FIG. FIG. The difference from FIG. 1 is that the p ⁻ anode layer 7 protrudes wider than the width of the trench groove 4. Also in this case, the end of the p ⁺ layer 8 arranged on the innermost periphery facing the trench groove 4 and the p ⁺ layer of the p ⁻ anode layer 7 formed on the bottom of the trench groove 4 arranged on the outermost periphery By setting the distance W2 between the gate electrode 8 and the opposite end to be equal to or less than the p ^- anode layer distance L2, the withstand voltage can be ensured. Further, when the diffusion depth of p ⁺ layer 8 is made deeper than the depth of the bottom of p ⁻ anode layer 7, more stable breakdown voltage can be secured.

FIGS. 6A and 6B show a semiconductor device according to a third embodiment of the present invention. FIG. 6A is a plan view, and FIG. 6B is a sectional view of a main part taken along line XX of FIG. FIG. Trench groove 24
Is a circular shape. Also in this case, by setting the distance W3 between the p ⁺ layer 8 and the outermost trench groove 24 to be equal to or less than the trench groove interval L3, the same effect as in FIG. 1 can be expected. Note that the trench groove interval L3 is equal to the trench groove 2
4, the distance between the most distant portions, and the distance between the trench grooves 24 arranged diagonally in the drawing corresponds to this distance.
The planar shape of the trench 24 is not limited to a circle, but may be a polygon or a band.

7A and 7B show a semiconductor device according to a fourth embodiment of the present invention. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view of a main part taken along line XX of FIG. FIG. The difference from FIG. 6 is that the p ⁻ anode layer 7 protrudes wider than the width of the trench 24. Also in this case, the breakdown voltage is secured by setting the distance W4 between the p ⁺ layer 8 and the p ⁻ anode layer 7 formed at the bottom of the trench groove 4 arranged at the outermost periphery to be equal to or less than the p ⁻ anode layer 7 distance L4. can do.

8A and 8B show a semiconductor device according to a fifth embodiment of the present invention. FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view of a main part taken along line XX of FIG. FIG. This is a case where the mesa portion 31 forming the Schottky junction 16 is formed in an island shape. By setting the distance W5 between the p ⁺ layer 8 and the mesa portion 31 disposed at the outermost periphery to be equal to or less than the width L5 of the mesa portion, the withstand voltage can be ensured. The planar shape of the island may be circular or polygonal.

FIG. 9 shows a semiconductor device according to a sixth embodiment of the present invention.
(A) is a plan view, and (b) of FIG.
It is principal part sectional drawing cut | disconnected by XX. Difference from Fig. 8
Is p ^-Anode layer 47 protrudes wider than trench groove
That is the point. Again, p⁺Layer 8 and outermost layer
Formed at the bottom of the trench groove 44 to be placed.^-Anneau
The distance W6 with the doped layer 47 is p^-Anode layer 47 interval L6 or less
If it is below, the same effect as in FIG. 1 can be expected.

FIGS. 10A and 10B show a semiconductor device according to a seventh embodiment of the present invention. FIG. 10A is a plan view and FIG.
It is principal part sectional drawing cut | disconnected by XX of FIG. Pressure resistant structure 14
Is a field plate, in this case, W7
Denotes a field plate end (an end of the insulating film 51 facing the trench groove 4: corresponds to an inner end of the insulating film 51);
L7 is the interval between four trenches. Also in this case, W7 ≦ L7
Then, the pressure resistance can be secured. Further, p corresponding to FIG.
^- When the width of the anode layer 7 is wider than the trench width, described since it is similar to that of FIG. 5 will be omitted.
In the figure, reference numeral 52 denotes the potential of the n ⁻ drift layer
In the n ⁺ layer tell, the metal film 53 becomes the low potential side of the field plate.

FIGS. 11A and 11B show a semiconductor device according to an eighth embodiment of the present invention. FIG. 11A is a plan view, and FIG.
It is principal part sectional drawing cut | disconnected by XX of FIG. The difference from FIG. 10 is that the arrangement of the trench grooves 24 is a regular triangular arrangement. With this arrangement, the distances between adjacent trench grooves 24 are all equal. As a result, the distances L8 between adjacent p ^- anode layers are all equal, so that the pinch-off voltages between the cells are equal, and the electric field intensity is reduced. Further, by setting the distance W8 between the p ⁺ layer 8 and the p ⁻ anode layer 7 formed at the bottom of the trench groove 24 arranged at the outermost periphery to be equal to or less than the p ⁻ anode layer 7 distance L8, as in FIG. Withstand voltage can be ensured. The cell refers to a unit including the trench 24 and the p-anode layer 7.

FIG. 12 shows a semiconductor device according to a ninth embodiment of the present invention. FIG. 12A is a plan view of a cell, and FIG.
FIG. 4 is a cross-sectional view of a cell cut by X-rays. The difference from the trench groove described above is that the trench groove has a ring shape. In the circular trench 24 shown in FIG. 7, a cavity may be formed in the filled polysilicon 6, but the formation of the cavity can be prevented by forming the trench 24a in a ring shape.

This is because, in the circular trench 24, the amount of polysilicon deposited on the upper portion of the side wall is larger than the amount of polysilicon deposited on the bottom portion. In such a case, a state where the cavity is not filled occurs. On the other hand, in the stripe-shaped trench groove, the side walls are elongated and parallel to each other, and when the upper part is closed, the lower part is also closed, and no cavity is generated. Ring-shaped trench 2
4a is also similar to the striped trench groove, and the side walls are opposed to each other. Therefore, it is difficult to form a cavity as compared with the circular trench groove 24.

By preventing the generation of cavities, the resistance of the polysilicon 6 can be reduced. As a result, a semiconductor device with low on-voltage can be obtained. In this ring-shaped trench groove 24a, as the depth T of the trench groove 24a increases, as the outer diameter D1 decreases, and as the inner diameter D2 decreases, the width ((D1-D2) / 2) of the trench increases. As the size is smaller, voids are more likely to be generated in the filled polysilicon 6. For example, when T is several μm and D2 is about 1 μm,
By setting D2 / D1 ≦ 0.5, it is possible to prevent a cavity from being generated in the polysilicon to be filled.

The p ^- anode regions 7 formed at the bottom of the ring-shaped trench 24a are formed so as not to contact each other. The ring-shaped trench 2
By arranging 4a as shown in FIG. 7, it goes without saying that the same effect as in FIG. 7 can be obtained. Even in the case of a stripe-shaped trench groove, by forming the curved portions at both ends into a semicircular ring shape, it is possible to prevent the occurrence of a cavity at this portion.

[0031]

According to the present invention, the relationship between the distance W between the breakdown voltage structure and the p ^- anode layer formed at the trench or the bottom of the trench and the distance L between the p ^- anode layers is set to W ≦ L. Electric field concentration near the structure can be prevented, and stable breakdown voltage characteristics can be obtained.

Further, by arranging the trench grooves in an equilateral triangle, the pinch-off voltage between the cells is made equal, the electric field intensity is reduced, and stable breakdown voltage characteristics can be obtained. Furthermore, the planar shape of the trench is changed to a ring shape (ring-shaped cell).
To fill the trench trench with polysilicon,
The generation of a cavity is prevented, and the resistance in the trench can be reduced.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, in which (a)
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 2 is a diagram showing a case where W1 = 0 when trench 4 in FIG. 1 is in contact with p ⁺ layer 8;

FIG. 3 is a diagram showing a case where the trench 4 of FIG. 1 partially enters the p ⁺ layer 8;

FIG. 4 is a diagram showing a relationship between a distance W1 between a p ⁺ layer 8 and a trench groove 4 and a breakdown voltage in the semiconductor device of FIG. 1;

FIG. 5 shows a semiconductor device according to a second embodiment of the present invention;
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 6 shows a semiconductor device according to a third embodiment of the present invention;
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 7 shows a semiconductor device according to a fourth embodiment of the present invention;
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 8 shows a semiconductor device according to a fifth embodiment of the present invention;
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 9 shows a semiconductor device according to a sixth embodiment of the present invention;
Is a plan view, and (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 10 shows a semiconductor device according to a seventh embodiment of the present invention;
(A) is a plan view, (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 11 shows a semiconductor device according to an eighth embodiment of the present invention;
(A) is a plan view, (b) is a cross-sectional view of a main part taken along line XX of (a).

FIG. 12 shows a semiconductor device according to a ninth embodiment of the present invention;
(A) is a plan view of the cell, and (b) is a cross-sectional view of the cell taken along line XX of (a).

[Explanation of symbols]

Reference Signs List 1 n ⁺ cathode layer 2 n intermediate layer 3 n ⁻ drift layer 4, 24 trench groove 5 oxide film 6 polysilicon 7 p ⁻ anode layer 8 p ⁺ layer 9 insulating film 10 anode electrode 11 metal film 12 cathode electrode 13 active region 14 , 51 Withstand voltage structure 16 Schottky junction 24a Ring-shaped trench groove 31 Mesa portion A pn diode portion B Schottky diode portion

Continued on the front page (72) Inventor Masato Otsuki 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Michio Nemoto 1-1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture Fuji Electric Co., Ltd.

Claims (7)

[Claims] 1. A plurality of trenches formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, an anode layer of a second conductivity type formed at a bottom of the trench, and the trench. A Schottky junction formed on the surface of the semiconductor substrate sandwiched between the grooves, a breakdown voltage structure formed on the periphery of the semiconductor substrate, and a cathode layer formed on the surface layer of the second main surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein a longest interval between an inner end of the breakdown voltage structure and the trench disposed at an outermost periphery is equal to or less than the trench interval. 2. A plurality of trench grooves formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, an anode layer of a second conductivity type formed at a bottom of the trench groove, and the trench. A Schottky junction formed on the surface of the semiconductor substrate sandwiched between the grooves, a breakdown voltage structure formed on the periphery of the semiconductor substrate, and a cathode layer formed on the surface layer of the second main surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein a longest distance between an inner end of the breakdown voltage structure and the anode layer disposed at the outermost periphery is equal to or less than the anode layer distance. 3. A trench selectively formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type; an anode layer of a second conductivity type formed at a bottom of the trench; A Schottky junction formed on the surface of the island-shaped semiconductor substrate surrounded by the trench groove, a breakdown voltage structure formed on a peripheral portion of the semiconductor substrate, and a surface layer formed on the second main surface of the semiconductor substrate; A semiconductor device having a cathode layer, wherein a longest distance between an inner end of the breakdown voltage structure and the anode layer disposed at the outermost periphery is equal to or less than the anode layer distance. 4. The semiconductor device according to claim 2, wherein a lateral width of said anode layer is wider than a width of said trench groove. 5. The device according to claim 1, wherein said pressure-resistant structure is a guard ring or a field plate.
The semiconductor device according to any one of the above. 6. The semiconductor device according to claim 1, wherein a diffusion depth of said p ⁺ layer is greater than a depth of said anode layer bottom from said first main surface. 7. A plurality of trenches formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, an anode layer of a second conductivity type formed at a bottom of the trench, and the trench. In a semiconductor device having a Schottky junction formed in a surface layer of a semiconductor substrate sandwiched between grooves and a cathode layer formed in a surface layer of a second main surface of the semiconductor substrate, the trench groove has a planar shape. And a ring-shaped semiconductor device.