JP2002082898A - Signal processor and signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performance of a signal processing by DMA transfer using an external bus without preventing a memory access operation using an internal bus of a processor. SOLUTION: This microprocessor is provided with connection switching units SA1, SD1 to cut off the external bus 600 consisting of an address bus 400, a data bus 500 from the internal bus consisting of an internal address bus 106, an internal data bus 107, an arithmetic unit 101, an internal memory 300 connected with the external bus 600 via the connection switching units SA1, SD1 and connected with the arithmetic unit 101 via the internal buses 106, 107 and an instruction decoder 105 to analyze an instruction code to be given to the arithmetic unit 101, to judge propriety of use of the external bus 600 and to output a bus free information signal to indicate a judgment result and performs control to cut off the internal buses 106, 107 from the external bus 600 by the connection switching units SA1, SD1 when the instruction decoder 105 judges that the external bus 600 is not used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device such as a microprocessor and a DSP (digital signal processor), and a signal processing system including the signal processing device and a direct memory access control device.

[0002]

2. Description of the Related Art A basic system of a signal processing apparatus using a conventional direct memory access controller (hereinafter, DMA controller) includes a processor such as a CPU (central processing unit) or a DSP, and an address bus and a data bus. It comprises a memory and a peripheral device connected to the processor via an external bus, and a DMA controller for controlling direct access to the memory by the peripheral device not controlled by the processor. In such a system, at the time of data transfer under the control of the processor other than the DMA control, the peripheral device is disconnected from the external bus, and data transfer processing is performed between the processor and the memory via the external bus. On the other hand, at the time of DMA data transfer under the control of the DMA controller, the processor is disconnected from the external bus, and data transfer is performed between the peripheral device and the memory. In this case, at the time of DMA data transfer, the processor disconnected from the external bus must temporarily suspend the processing, and therefore, there has been a problem that the processing efficiency of the processor deteriorates.

[0003] An example of a system which has improved the above-mentioned problems is described in Japanese Patent Application Laid-Open No. Hei 5-204831, "Microcomputer and Microcomputer System Having Direct Memory Access Function Using It". In the system described in this publication, a means for decoding an instruction code in a microprocessor to detect whether or not to use a bus and a means for notifying a peripheral device of a detection result are provided. DM by peripherals when the microprocessor does not need to use the bus
A data transfer is performed. This gives D
The transmission and reception of a signal for acquiring a bus right when executing MA data transfer is not required, and the DMA data transfer can be performed by using a period in which the microprocessor does not use the bus, so that the processing of the processor can be performed. Improving efficiency.

[0004]

However, even in a system utilizing the decoding result of an instruction code as described in the above-mentioned publication, once DMA transfer is started, the use of the bus by peripheral devices is restricted. The processor cannot start using the bus until after the processing for stopping the processing is completed. Therefore, there is a problem that the processing efficiency of the processor is reduced when the DMA data transfer is stopped.

On the other hand, in recent years, signal processing devices such as microprocessors as described above, in which a cache memory such as a system cache memory or a data cache memory is mounted inside a chip or an instruction Some of them have a built-in memory for a program for storing and a memory for data for storing data. In such a signal processing device, generally, an internal bus including an address bus and a data bus connected to a memory inside the chip is connected to an external address bus and a data bus via a predetermined interface circuit (connection circuit). Have been. When performing DMA data transfer using such a signal processing device, when the internal bus is used by the processor, the external bus is also occupied by the processor, and during that time, the peripheral device performs the DMA transfer. If the DMA transfer using the external bus is being executed, the DMA transfer is stopped and the external bus is released, as described above. Access to memory could not be performed.

The present invention has been made in view of the above circumstances, and has been made in consideration of the above problems.
It is an object of the present invention to provide a signal processing device and a signal processing system capable of improving the processing efficiency of a signal processing device such as an SP, as compared with the related art. More specifically, it is an object of the present invention to provide a signal processing device and a signal processing system capable of executing signal processing by DMA transfer using an external bus without hindering a memory access operation using an internal bus of a processor. With the goal.

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a connection section for an external bus comprising an address bus and a data bus, an operation section, and a connection section to the external bus via the connection section. In a signal processing device having an internal memory connected to an operation unit via an internal bus consisting of an address bus and a data bus, an instruction code given to the operation unit is analyzed, and whether an external bus is used or not is analyzed. An analysis unit that determines whether the external bus is not used, a bus connection switching unit that disconnects the internal bus from the external bus when the analysis unit determines that the external bus is not used, and a signal generation unit that generates a signal indicating a determination result of the analysis unit. It is characterized by having.

According to a second aspect of the present invention, there is provided an external memory connected to the external bus, the signal processing apparatus according to the first aspect, and a signal processing unit which is built in or external to the signal processing apparatus and which is generated by the signal generation unit. And a direct memory access control device having a signal input unit for inputting the input signal and a direct memory access control circuit for controlling access to the external memory in accordance with the input signal. The invention according to claim 3 is characterized in that the direct memory access control device includes a temporary storage circuit for data read / written from / to the external memory under the control of the direct memory access control circuit. I do.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a signal processing apparatus and a signal processing system according to the present invention; FIG. 1 is a block diagram showing a configuration of an embodiment of a signal processing device and a system therefor according to the present invention. The signal processing system shown in FIG.
(A signal processing device) 100 such as
I / O (Input / Output) for performing data input / output between the MA controller 200 and a memory such as a RAM (random access memory) or a peripheral device (not shown).
A memory (or I / O device) 300 (hereinafter, referred to as a memory 300), which is a device,
An external bus 600 including an address bus 400 and a data bus 500 shared between the MA controller 200 and the memory 300 is provided. In this case, the external bus 600 includes the microprocessor 100,
Alternatively, the I / O device 30 is directly connected to the external bus 600 or
0 (including other I / O devices not shown) to be used exclusively by any of the peripheral devices (not shown) connected thereto.

The microprocessor 100 includes an arithmetic unit 10
1, a register 102, an address generator 103, and R
It has an internal memory 104 such as an AM and a ROM (Read Only Memory) and an instruction decoder 105 for analyzing an instruction code executed by the arithmetic unit 101. The address generator 103 generates and outputs an address signal composed of a plurality of bits output to the address bus 400 via the internal address bus 106 or the connection switch SA1. The register 102 is connected to the data bus 500 via the internal data bus 107 or the connection switch SD1, and inputs / outputs a data signal composed of a plurality of bits via those data buses. In this case, the connection switch SA1 and the connection switch SD1 are on / off controlled by the bus switching signal on the bus switching signal line 108, and follow predetermined input / output specifications with respect to the address bus 400 and the data bus 500. It functions as an interface (connection part) having the above performance.

The instruction decoder 105 is provided in the internal memory 10
4. The instruction read from a predetermined storage device such as the memory 300 and executed by the arithmetic unit 101 is analyzed, and the arithmetic unit 101 and the register 102 or the internal memory 104 are analyzed.
When an instruction that does not use the external bus 600 including the address bus 400 and the data bus 500 is detected, such as data transfer between the two, the bus switching signal on the bus switching signal line 108 causes the connection switch SA1 and the connection switch SD1 to be switched. In addition to controlling to the off state, a bus empty information signal indicating that the address bus 400 and the data bus 500 are empty is generated and output on the bus empty information signal line 109. When the instruction decoder 105 detects an instruction using the address bus 400 and the data bus 500 as a result of analyzing the instruction, the instruction decoder 105 outputs a bus empty information signal indicating that the address bus 400 and the data bus 500 are in use. The connection switch SA1 and the connection switch SD1 are generated and output by the bus switching signal when the external bus 600 is not used by another device.
Is turned on.

On the other hand, the DMA controller 20 shown in FIG.
0 is the DMA control circuit 201 and the data buffer 202
, A transfer data number counter 203, a transfer source address generator 204, a transfer destination address generator 205, a selector 206, a connection switch SA2, and a connection switch SD2. The DMA control circuit 201 controls a control signal input / output to / from a peripheral device by using a plurality of control signal lines (not shown). Based on the count value of the number counter 203, the selector 206,
It controls each unit such as the connection switch SA2 and the connection switch SD2. The data buffer 202 stores data written to the memory 300 from the peripheral device via the data bus 500, data read from the memory 300 to the peripheral device, data copied in the memory 300, and the like.
The data transferred under the control of 00 is temporarily stored.

The transfer data number counter 203 is a subtraction counter whose count value is initialized by the microprocessor 100. Each time data transfer is performed, the count value is decreased by the number of data transfers, and the count value becomes "0". "
Then, the data transfer by the DMA control device 201 is stopped. The transfer source address generator 204 includes an address counter that increases or decreases a value indicating a transfer source address every time data is transferred. The transfer destination address generator 205 includes an address counter that increases or decreases an address value indicating a transfer destination address every time data is transferred. The initial value of each address counter of the transfer source address generator 204 and the transfer destination address generator 205 is set by the microprocessor 100 together. The selector 206 is provided for the transfer source address generator 204 or the transfer destination address generator 20.
5 is alternately switched as an input with the count value of each address counter and output to the connection switch SA2. The connection switch SA2 outputs the output of the selector 206 to the address bus 400.
And a switch group for switching between a connected state (on state) and a disconnected state (off state). The connection switch SD2 is configured by a switch group that switches the input / output line group of the data buffer 202 to a connection state or a non-connection state to the data bus 500.

In the present embodiment, as shown in FIG. 2, the microprocessor 100 performs arithmetic processing by a three-stage pipeline architecture of instruction / data fetch, instruction decode, and instruction execution. The instruction decoder 105 determines whether an instruction located before the instruction execution stage illustrated in FIG. 2, for example, the instruction being decoded in the instruction decode stage uses the external bus 600, and based on the determination result, The signal states of the bus switching signal on the bus switching signal line 108 and the bus empty information signal on the bus empty information signal line 109 are switched and controlled. In this case, for example, when an instruction not using the external bus 600 is detected in the instruction decode stage,
In the instruction execution stage, the connection switch SA1 and the connection switch SD1 are controlled to be in the off state, and the external bus 600 is disconnected from the internal buses 106 and 107.
01 is capable of executing the instruction even when the external bus 600 is being used by a peripheral device. Here, FIG. 2 shows a sequence of instructions a, b,
This shows a temporal change in the processing content of each stage executed in each of the instruction cycles 1 to 4 when processing c and d.

Next, the operation of the signal processing system shown in FIG. 1 will be described with reference to FIG. When the instruction decoder 105 in the microprocessor 100 analyzes a new instruction (S100), it is determined whether the instruction code is an instruction using the external bus 600 (S101).
When it is determined that the instruction uses the external bus 600, the instruction decoder 105 outputs a signal indicating a use state as a bus empty information signal (S102). After confirming that the external bus 600 is not being used by another device, the instruction decoder 105 controls the connection switch SA1 and the connection switch SD1 to be in an on state by a bus switching signal (S103). On the other hand, when the DMA control circuit 204 in the DMA controller 200 detects that the bus empty information signal is controlled to indicate the use state, the DMA control circuit 204 controls the connection switch SA2 and the connection switch SD2 to the off state (S103). ). In this case, when the DMA controller 200 is performing the DMA data transfer, the count value of the transfer data number counter 203, the address counter value of the transfer source address generator 204, the address counter value of the transfer source address generator 205, and the data buffer The data 202 is held at the value at that time. Connection switch SA1 and connection switch SD1
Is turned on and the connection switch SA2 and the connection switch SD2 are turned off, the external bus 600 can be used by the microprocessor 100. For example, the external bus 600 is connected between the microprocessor 100 and the memory 300. The used data transfer is executed (S104).

On the other hand, when it is determined in step S101 that the analyzed instruction does not use the external bus 600, the instruction decoder 105 outputs a signal indicating an empty state (non-use state) as a bus empty information signal. It is output (S105). The instruction decoder 105 further controls the connection switch SA1 and the connection switch SD1 to be turned off by the bus switching signal in the next command cycle (S106). Further, the DMA control circuit 201 sends a DMA request from the peripheral device in a state where the bus free information signal indicates a free state.
When execution of the data transfer is requested, the connection switch SA2 and the connection switch S
D2 is turned on (S106). Connection switch S
When A1 and connection switch SD1 are turned off and connection switch SA2 and connection switch SD2 are turned on, internal address bus 106 and internal data bus 107 in microprocessor 100 are disconnected from external bus 600. , Arithmetic unit 101 and register 10
2 enables data transfer via the internal buses 106 and 107 even when the external bus 600 is used by another device. At the same time, the external bus 600
Becomes available for DMA transfer. Therefore, for example, the microprocessor 100
00, local signal processing in the microprocessor 100 can be performed between the arithmetic unit 101 and the register 102 or between the arithmetic unit 101 and the register 102 and the internal memory 104 (S107). Data transfer using the external bus 600 with the memory 300 can be executed (S108).

The processing of the DMA transfer is executed as follows. The procedure for reading data is (1), (2),
, (5), and the procedure for writing data is (1),
(2a),..., (5a).

(1) The microprocessor 100 sets a transfer source address, a transfer destination address, and the number of data to be transferred.
That is, the microprocessor 100 initializes the transfer source address generator 204, the transfer destination address generator 205, and the transfer data number counter 203.

In the case of data reading, next, (2) when a bus empty information signal comes, the switches SA2 and SD
2 is turned on, switch SA1 and switch SD
1 is turned off. (3) Address data is output from the source address generator 204 to the address bus 400 (the source address counter is advanced). (4) Data is output from the device (memory or I / O device 300) to the data bus 500. (5) Data bus 500
Is extracted from the data buffer 202 and stored in the data buffer 202.

On the other hand, in the case of data writing, following the procedure (1), when (2a) a bus empty information signal comes,
The switches SA2 and SD2 are turned on,
The switches SA1 and SD1 are turned off. (3a) Address data is output from the destination address generator 205 to the address bus 400 (the destination address counter is advanced). (4a) Data buffer 202
Output data to the data bus 500. (5a)
Data is taken out from the data bus 500 and stored in a device (memory or I / O device 300).

Each of the above procedures (3) to (5) or (3)
After the processing of a) to (5a), the number of transferred data is written to the transfer data number counter 203 (the remaining data number is managed). Then, each procedure is repeated, and the process stops when the counter becomes “0”.

In the above DMA transfer, even if the external bus 600 is used, that is, the operation side (microprocessor 100 side) occupies the DMA,
Information for transfer is held in a transfer data number counter 203, a transfer source address counter, and a transfer destination address counter, and data is also stored in the data buffer 202. Therefore, when the external bus 600 is switched from the DMA transfer, it is not necessary to perform a special evacuation process for interrupting (a process for interrupting a process such as holding a transfer address and temporarily holding transfer data).

As described above, in the present embodiment,
When the microprocessor 100 does not use the external bus 600, the connection switches SA1 and SD1 enable the internal buses 106 and 10 in the microprocessor.
7 is disconnected from the external bus 600, and a signal indicating that the bus is idle is generated and output.
Local processing in the microprocessor 100 and DMA transfer using the external bus 600 can be executed simultaneously. Further, during the DMA transfer processing using the external bus 600, the internal buses 106, 1
When it becomes necessary to execute an instruction using the 07, a waiting time until the external bus 600 is released is conventionally required, but this can be eliminated.

Note that the embodiment of the present invention is not limited to the above-described embodiment.
It is possible to appropriately change the way of combining the system and each component and the operation thereof, for example, by incorporating the DMA controller 200 therein. For example, the memory 104 in the microprocessor 100 includes RAM, RO
The memory 104 is not limited to a memory M or the like, and may be composed of a nonvolatile memory such as an EEPROM (Electrically Erasable Programmable ROM) or a combination thereof, or the memory 104 may be a cache memory such as a program cache memory or a data cache memory. Alternatively, a memory for storing instructions and data may be provided together with the memory. Further, a configuration in which the memory 104 is divided into a plurality of systems, that is, a plurality of systems of internal address buses and internal data buses may be provided so that the memory can be accessed independently for each system. For example, when the microprocessor is divided into two systems and provided with two sets of address buses and data buses corresponding to the respective memories, and the microprocessor accesses only one of the two systems, the other system memory is used. The switching control of the bus connection that can be accessed from outside may be performed.

[0025]

As described above, according to the present invention, since the bus connection switching unit for disconnecting the internal bus from the external bus when the external bus is not used is provided, the memory access using the internal bus of the microprocessor is provided. Signal processing by DMA transfer using an external bus can be executed without hindering the operation. Therefore, a microprocessor in a system for performing DMA data transfer,
The processing efficiency of a signal processing device such as a DSP can be improved as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing system according to the present invention.

FIG. 2 is an explanatory diagram illustrating a pipeline processing method for each instruction code in the microprocessor 100 shown in FIG. 1;

FIG. 3 is a system flow chart showing the operation of the system of FIG. 1;

[Explanation of symbols]

100: microprocessor, 101: arithmetic unit, 102
... register, 103 ... address generator, 104 ... memory, 105 ... instruction decoder, 106 ... internal address bus, 107 ... internal data bus, 108 ... bus switching signal line, 109 ... bus empty information signal line, 200 ... DMA controller, 202 data buffer, 203 address generator, 201 DMA control circuit, 300 memory (or I / O device), 400 address bus, 500 data bus, 600 external bus, SA1, SD1, SA2
SD2: Connection switcher.

Claims (3)

[Claims] A connection unit for an external bus comprising an address bus and a data bus; a calculation unit; and a connection unit to the external bus via the connection unit and to a calculation unit via an internal bus comprising an address bus and a data bus. In a signal processing device having a connected internal memory, an analysis unit that analyzes an instruction code given to an arithmetic unit and determines whether to use an external bus, and determines that the analysis unit does not use an external bus A signal processing device comprising: a bus connection switching unit that disconnects an internal bus from an external bus in a case; and a signal generation unit that generates a signal indicating a determination result of the analysis unit. 2. The external memory connected to the external bus; the signal processing device according to claim 1; and a signal which is built in or external to the signal processing device and receives a signal generated by the signal generation unit. A signal processing system comprising: a direct memory access control device including an input unit and a direct memory access control circuit that controls access to the external memory according to the input signal. 3. The direct memory access control device according to claim 1, further comprising: a temporary storage circuit for data read / written to / from the external memory under the control of the direct memory access control circuit. 3. The signal processing system according to 2.