JP2002074961A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a defective memory cell caused by less read-out margin can be easily relieved, and improvement of the yield can be realized. SOLUTION: A mode register set 60 generates signals CL2, CL3 for controlling CAS latency in accordance with a control signal externally given. A control circuit 22 changes timing from activation of word lines to activation of a sense amplifier in accordance with that which CAS latency is selected. This timing is adjusted by cutting of a fuse element in the control circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a configuration of a semiconductor memory device, and more particularly, to a configuration of a data read circuit of the semiconductor memory device.

[0002]

2. Description of the Related Art A semiconductor memory device, for example, a dynamic random access memory (hereinafter referred to as DRAM).
In, the timing for activating the sense amplifier activating signal, that is, the signal for activating the sense amplifier after the word line is activated, is previously set to a constant value by simulation in the design stage.

In testing the characteristics of a DRAM, some of the defective memory cells are caused by the fact that the read margin is small with respect to the predetermined timing. . In other words, since it takes time until the data of the memory cell is read to the bit line after the activation of the word line, the data transfer is not sufficiently performed during the predetermined timing, and an accurate value cannot be read. May cause failure.

In such a case, it is possible to remedy a defect by finely adjusting the activation timing of the sense amplifier activation signal. Further, by finely adjusting the activation timing of the sense amplifier activation signal, it is possible to improve the margin of the read operation for the data of the memory cell.

[0005]

However, conventionally,
In order to finely adjust the activation timing of the sense amplifier activation signal, it is necessary to adjust the number of delay stages by revising the mask, and the time and cost required for the adjustment become unnecessarily large. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to easily remedy a defective memory cell caused by a small read margin. Another object of the present invention is to provide a semiconductor memory device that can improve the yield.

Another object of the present invention is to provide a semiconductor memory device capable of operating with an optimum read margin according to an operation mode.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix; and a data output from a read command in response to an externally applied control signal. Mode setting means for selectively setting the delay period to any of a plurality of predetermined periods, a plurality of word lines provided corresponding to rows of the memory cell array, and a plurality of word lines provided corresponding to columns of the memory cell array. A plurality of bit lines, a row selecting means for selectively activating a word line in accordance with an address signal, and data read from a memory cell connected to the activated word line via the bit line. And a plurality of sense amplifiers for amplifying memory cells, and a timing from word line activation to sense amplifier activation depending on which predetermined period is selected. And a control circuit for changing the.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the control circuit includes:
A timing setting means for generating a sense amplifier activation signal instructing activation of the sense amplifier after the activation of the word line, wherein the timing setting means is provided corresponding to each of a plurality of predetermined times; And a selecting means for selectively operating a corresponding one of the plurality of delay circuits in accordance with which predetermined period is selected.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, each delay circuit includes a fuse element for changing a delay time, and the fuse element is cut by laser blowing. It is possible.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the second aspect, each of the delay circuits includes a fuse element for changing a delay time, and the fuse element has an external voltage. It can be cut by application.

[0012]

[First Embodiment] FIG. 1 is a schematic block diagram showing a configuration of a semiconductor memory device 1000 according to a first embodiment of the present invention.

Referring to FIG. 1, semiconductor memory device 1000
Is externally supplied with an external chip select signal Ext. / C
S, external row address strobe signal Ext. / RA
S, external column address strobe signal Ext. / CA
S, the external write enable signal Ext. / WE and other control signal input terminal groups for receiving control signals such as / WE
, An address input terminal group 8, a data input / output terminal group 9 for transmitting and receiving data signals, a ground terminal 12 to which a ground potential Vss is applied, and a power supply potential ext. And a power supply terminal 10 to which Vcc is applied.

Semiconductor memory device 1000 further receives a control signal to generate an internal control signal for controlling the internal operation of semiconductor memory device 1000, and receives an external address signal to receive an internal address signal. A row and column address buffer 24 for generating a signal, and a row predecoder 26 for receiving a signal from row and column address buffer 24 and generating a signal for selecting a row
, Column predecoder 28 for receiving a signal from row and column address buffer 24 and generating a signal for column selection, sense amplifier + input / output control circuit 40, memory cell array 42, data input / output buffer 44.

The control circuit 22 has a chip select signal Ext. /
CS, external row address strobe signal Ext. / RAS and external column address strobe signal Ext. / CAS, generates a control clock corresponding to a predetermined operation mode based on / CAS, for example, sense amplifier activation signals SON, SOP, etc.
The operation of the entire semiconductor memory device is controlled. The control circuit 22 further controls another control signal and the external write enable signal Ext. In response to the combination with / WE, a signal for controlling the operation of data input / output buffer 44 in the write operation and the read operation is generated.

The row and column address buffer circuit 24
An internal address signal generated based on externally applied address signals A0 to Ai (i is a natural number) is applied to row predecoder 26 and column predecoder 28.

The memory cell array is divided into a plurality of memory cell blocks MCB0 to MCBn. In each memory cell block, a row decoder 27 for selecting a row (word line) in the corresponding memory cell block based on a row predecode signal from a row predecoder 26, and a column predecode from a column predecoder 28 Based on the signal
A column decoder 100 for selecting a column (bit line pair) in a corresponding memory cell block, a sense amplifier SA and a column decoder provided corresponding to each bit line pair for amplifying data stored in the selected memory cell. And an I / O circuit for selectively transmitting data from the bit line pair selected by 100 to data input / output buffer 44. In FIG. 1, for convenience, a column decoder (YD) 1
00, the sense amplifier and the I / O circuit 40 are collectively represented by one block.

That is, the row decoder 27 and the column decoder 10
The memory cells in the memory cell array 42 designated by "0" exchange data with the outside through the input / output terminal group 9 through the sense amplifier + I / O circuit 40 and the data input / output buffer 44.

Semiconductor memory device 1000 further includes an external power supply potential Ext. An internal power supply circuit 38 receiving Vcc and ground potential Vss to generate internal power supply potentials Vccp and Vccs is provided.

The semiconductor integrated circuit 1000 further includes a control signal Ext. / CS, Ext. / RAS, E
xt. / CAS, ext. / WE based on internal chip select signal CS0, internal row address strobe signal RAS0, internal column address strobe signal CAS0, internal write enable signal WE0, row and column address buffer 2
4 based on the internal address signal, for example, a CAS latency control signal CL described later.
2, mode register set 6 for generating CL3, etc.
0.

The semiconductor memory device 100 shown in FIG.
The configuration of 0 is only a typical example, and the present invention is more generally applicable to other configurations of the dynamic semiconductor memory device. For example, the way of dividing the memory cell array is not particularly limited to the example of FIG. 1, and the semiconductor memory device 1000 itself may be configured to be integrated with other circuits on one chip. .

FIG. 2 is a diagram showing a configuration of the sense amplifier section shown in FIG. FIG. 2 representatively shows a configuration of one sense amplifier and parts related thereto.

The sense amplifier 17 has a sense node SNa
Channel having a gate having a conduction node coupled to sense node SNb and a conduction node coupled to sense node SNb
P-channel MOS transistor PQb having an OS transistor PQa, a gate having one conduction node coupled to sense node SNb and a gate coupled to sense node SNa, one conduction node and sense node coupled to sense node SNa N-channel MOS transistor NQa having a gate having a gate coupled to SNb, and N-channel MOS transistor N having a gate having a conduction node coupled to sense node SNb and a gate coupled to sense node SNa.
Qb.

The sense amplifier 17 is turned on in response to a sense amplifier activating signal SOP from a sense activating circuit 35 included in the control circuit 22, and is connected to the other conductive node of the P channel MOS transistors PQa and PQb. P-channel MOS transistor PQc for supplying power supply potential Vccs, and sense activation circuit 35
In response to sense amplifier activating signal SON from N-channel MOS transistors NQa and NQb.
N-channel MOS transistor NQc for supplying ground potential GND to the other conduction node. Array power supply potential Vccs is supplied to substrate regions (regions which are well regions or semiconductor layers and function as substrates) of P-channel MOS transistors PQa, PQb and PQc. Sense activation circuit 35 operates using peripheral circuit power supply potential Vccp as one operation power supply potential.

Sense nodes SNa and SNb are connected to bit lines BLL and / BLL of one memory cell block, respectively.
Are connected to bit lines BLR and / BLR of the memory cell block via bit line separation transistors 32a and 32b, respectively.
Bit line isolation control signals BLIL are applied to the gates of bit line isolation transistors 30a and 30b, and bit line isolation control signal BLIR is applied to the gates of bit line isolation transistors 32a and 32b.

When a selected memory cell MC is connected to one of bit lines BLL, / BLL and bit lines BLR, / BLR, of the bit line isolation control signals BLIL and BLIR, the selected memory cell is connected. Only the bit line isolation signal corresponding to one bit line pair is set to the "H" level (normally, a potential level higher than the array power supply potential Vccs), and the bit line isolation signal for the other bit line pair is set to the "L" level. You.

Sense nodes SNa and SNb and sub-I
Between O lines SIO and / SIO, conduction is performed in response to a column selection signal CSL transmitted from column decoder 30, and sense nodes SNa and SNb are connected to sub IO lines SIO and / SI.
IO gate transistors 34a and 34 connected to O
b is provided.

FIG. 3 is a timing chart showing the relationship between the activation timing of the word line WL and the activation timing of the sense amplifier activation signal.

At time t1, after the potential level of word line WL is activated by row decoder 27, at time t2 after a lapse of time ΔT, signal SON from sense activation circuit 35 is activated (“H”). "Level). Further, the signal SOP (not shown) is also in an active state ("
L "level).

In the present invention, this time ΔT can be adjusted after the semiconductor memory device 1000 is manufactured.

FIG. 4 is a circuit diagram showing a configuration of the timing adjustment circuit 200 included in the sense activation circuit 35.

The timing adjustment circuit 200 operates upon receiving a signal SON which becomes active at a predetermined timing determined at the time of design from activation of a word line. FIG.
In the above, the timing adjustment circuit 200 that receives the signal SON and generates the signal SON is provided with only one stage, but may be provided with a plurality of stages as necessary.

Referring to FIG. 4, timing adjustment circuit 20
0 is a P-channel MOS provided between power supply potential Vccp and output node n1, and receiving signal SON at its gate.
Transistor PQ10, node n1 and ground potential GND
Resistors R10 and R12 and an N-channel MOS transistor NQ10 provided in series between
2 and a fuse element F10 coupled in parallel.

By blowing the fuse element F10 with a laser, the delay time from the activation of the signal SONT to the activation of the signal SON can be increased.

Therefore, even after the manufacture of semiconductor memory device 1000, during the wafer process, the activation timing of the sense amplifier activation signal can be adjusted by blowing the fuse element, thereby improving the read margin of the memory cell. It is possible to do. Further, it becomes possible to relieve a memory cell that has become defective due to a shortage of a read margin.

[Second Embodiment] FIG. 5 is a circuit diagram showing a configuration of a timing adjustment circuit 300 according to a second embodiment.
Timing adjustment circuit 200 according to the first embodiment shown in FIG.
The differences are as follows.

That is, in the timing adjustment circuit 300, the fuse element F10 is connected to the pad PD1 and the pad PD2 so that the fuse element F10 can be electrically disconnected.
10 is configured to be able to apply a voltage. In other respects, the configuration is the same as that of the timing adjustment circuit 200. Therefore, the same portions are denoted by the same reference characters, and description thereof will not be repeated.

With this configuration, after the manufacture of the semiconductor memory device 1000 and after the end of the molding process, the activation timing of the sense amplifier activation signal can be adjusted by blowing the fuse element. It is possible to improve the read margin of the memory cell. Further, it becomes possible to relieve a memory cell that has become defective due to a shortage of a read margin.

[Embodiment 3] Semiconductor memory device 1000
Is a synchronous dynamic random access memory (hereinafter, SDRAM), the read data is
It is output after a lapse of a predetermined clock period (CAS latency) after the application of the read command.

The magnitude of the CAS latency is specified by a mode register set command according to the operating frequency and the like. At this time, the signal CL2 or CL3 output from the mode register 60 is activated. For example, the magnitude of the CAS latency is set to 1.5 clocks, 2.0 clocks, 2.5 clocks, or the like according to the combination.

For example, if the SDRAM operates at an operating frequency of 100
At the time of MHz operation, CL = 2 is set, and 133 MHz is set.
In z, CL = 3 is set.

If the activation timing of the sense amplifier activation signal is designed based on the case where CL = 2, then CL = 3
In the case of operating the SDRAM, there is a margin in the read timing. In each case of CL = ２, the read margin can be set to an optimum value for each operation mode by changing the timing of the sense amplifier activation signal.

FIG. 6 shows such a control circuit 22.
3 is a circuit diagram showing a configuration of a timing setting circuit 400 included in FIG.

Referring to FIG. 6, timing setting circuit 40
0 is an inverter INV10 receiving the signal SON,
NAND circuit GN receiving the output of inverter INV10 at one input node and receiving signal CL2 at the other input node
A1 and a NAND receiving the output of inverter INV10 at one input node and receiving signal CL3 at the other input node
A circuit GNA2, a delay circuit DL1 receiving the output of the NAND circuit GNA1, delaying the output by a predetermined time, and outputting the delayed signal;
A delay circuit DL2 that receives an output of the D circuit GNA2 and delays the output by a predetermined time and outputs the same, and a NOR circuit GN that receives outputs from the delay circuits DL1 and DL2 and outputs a signal SON
R1.

With the above-described configuration, the timing from activation of the word line WL to activation of the sense amplifier activation signal is changed according to the magnitude of the CAS latency. In the mode, a read margin can be secured.

[Modification 1 of Third Embodiment] Delay circuits DL1 and DL2 in timing setting circuit 400 shown in FIG. 6 are replaced with timing adjustment circuit 200 shown in FIG.
It is possible.

In this case, in each operation mode, fine adjustment of the timing becomes possible during the wafer process, and the read margin can be adjusted. Therefore, the yield for each operation mode can be improved.

[Modification 2 of Third Embodiment] Delay circuits DL1 and DL2 in timing setting circuit 400 shown in FIG. 6 are replaced with timing adjustment circuit 200 shown in FIG.
It is possible.

In this case, in each operation mode, the timing can be finely adjusted after the completion of the molding process, and the read margin can be adjusted. Therefore, the yield for each operation mode can be improved.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0051]

According to the semiconductor memory device according to the first and second aspects,
In each operation mode, fine adjustment of the timing becomes possible after manufacturing, and the read margin can be adjusted. Therefore, the yield for each operation mode can be improved.

In the semiconductor memory device according to the third and fourth aspects, the activation timing of the sense amplifier activation signal can be adjusted by cutting the fuse element even after the semiconductor memory device is manufactured, and the read margin of the memory cell can be adjusted. Can be improved. Further, it becomes possible to relieve a memory cell that has become defective due to a shortage of a read margin.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device 10 according to a first embodiment of the present invention.
It is a schematic block diagram which shows the structure of 00.

FIG. 2 is a diagram illustrating a configuration of a sense amplifier unit illustrated in FIG. 1;

FIG. 3 is a timing chart showing the relationship between the activation timing of a word line WL and the activation timing of a sense amplifier activation signal.

FIG. 4 is a circuit diagram showing a configuration of a timing adjustment circuit included in a sense activation circuit.

FIG. 5 is a circuit diagram showing a configuration of a timing adjustment circuit 300 according to the second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a timing setting circuit 400.

[Explanation of symbols]

1, 2, 4, 6 control signal input terminal, 8 address signal input terminal group, 9 data input / output terminal group, 10 power supply input terminal, 12 ground potential input terminal, 18 gate circuit, 2
2 control circuit, 24 rows and address buffer, 26 rows predecoder, 28 columns predecoder, 4
0 sense amplifier + input / output control circuit, 42 memory cell array, 44 data input / output buffer, 60 mode register set, 100 column decoder, 200, 300
Timing adjustment circuit, 400 timing setting circuit, 1
000 Semiconductor integrated circuit device.

Claims (4)

[Claims] 1. A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in a matrix; and a plurality of delay periods from a read command to a data output according to a control signal supplied from outside. Mode setting means for selectively setting any one of the predetermined periods, a plurality of word lines provided corresponding to a row of the memory cell array, and a plurality of word lines provided corresponding to a column of the memory cell array. A row selection means for selectively activating the word line according to an address signal; and amplifying data read from the memory cell connected to the activated word line via the bit line. A plurality of sense amplifiers for activating the word lines and activating the sense amplifiers depending on which of the predetermined periods is selected. And a control circuit for changing the timing in a semiconductor memory device. 2. The control circuit further comprises: timing setting means for generating a sense amplifier activating signal for instructing activation of the sense amplifier after activating the word line, wherein the timing setting means comprises: A plurality of delay circuits which are provided corresponding to time and adjust the output timing of the sense amplifier activating signal; and a plurality of delay circuits corresponding to the predetermined period are selected. 2. The semiconductor memory device according to claim 1, further comprising: a selection unit that selectively operates a delay circuit that performs the operation. 3. Each of the delay circuits includes a fuse element for changing a delay time, wherein the fuse element can be cut by a laser blow.
The semiconductor memory device according to claim 2. 4. The semiconductor memory device according to claim 2, wherein each of said delay circuits includes a fuse element for changing a delay time, and said fuse element can be cut off by applying a voltage from outside.