JP2002064751A - Solid-state imaging device - Google Patents

Abstract

(57) [Problem] In a solid-state imaging device having a pixel configuration including one photodiode, four transistors, and one capacitor, only one of a field shutter function and a kTC noise cancellation function is used. Can not. SOLUTION: A capacitor Ce by a transistor M1 is provided.
After resetting, the charge transfer transistor M5 is turned on to transfer the charge photoelectrically converted by the photodiode PD to the capacitor Ce for accumulation. Subsequently, turning off the transistor M5 is performed for all pixels at the same time, and then the transistors M1 and M3 of the pixels in the same row are turned on to output a predetermined potential to the CDS circuit 5. Subsequently, the transistor M6 is turned on, and the transistor M3 is turned on to output a signal corresponding to the electric charge by the field shutter function accumulated in the capacitor Ce to the CDS circuit 5. Thereby, the CDS circuit 5 has kT
C noise can be canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device, and more particularly to a CMOS image sensor having a storage and transfer unit in a pixel.

[0002]

2. Description of the Related Art Conventional solid-state imaging devices are roughly classified into two types, a CCD system and a CMOS sensor system. The difference between the two is not the photodiode that converts light into electric charge, but how the information on the electric charge of the photodiode is transmitted outside each light receiving element.

In the CCD system, charges generated in a photodiode are transferred to a charge transfer device (CCD).
e) Transfer directly to the outside. On the other hand, in the CMOS sensor system, information on the potential due to the charge generated in the photodiode is output to the outside of the element through an amplifier provided for each photodiode. Since the pixel structure of the CMOS sensor system can be formed by almost the same process as a normal CMOS-LSI process, the CMOS-LSI
There is an advantage that an area sensor and other CMOS circuits can be mixed.

On the other hand, the CMOS sensor system has a problem that fixed pattern noise is larger than that of the CCD system. The fixed pattern noise is mainly caused by variation in the threshold voltage of the amplifier transistor.

FIG. 7 is a block diagram showing an example of a conventional solid-state imaging device. This conventional solid-state imaging device is the most common CM
Shows the OS image sensor are arranged in the pixel 2 _{11-2 33} like a two-dimensional matrix, the pixel 2
Of _{11-2 33,} a vertical shift register 1, each row of (are arranged in the horizontal direction) operation of a plurality of pixels, for each row (usually toward the bottom line from the top line) is controlled, signals from the pixels 2 _{11-2 33} is input to the load and the noise canceller 3, after being noise canceling operation, sequential transistor T1~T3 by the horizontal shift register 4 is turned on, the signal of each column as an imaging signal Is output. In normal processing, processing proceeds from the right column to the left column. Note that the rows and columns can be arranged in reverse. It is also possible to arrange the pixels not in a two-dimensional matrix but in a one-dimensional one-dimensional line.

This conventional solid-state imaging device, that is, a conventional CMOS image sensor has a noise canceller called a CDS circuit together with pixels. This is to remove background noise (mainly variation in threshold voltage of the amplifier transistor of the pixel) when no signal is input from the output signal of the pixel.

FIG. 8 is an equivalent circuit diagram of an example of one pixel of a conventional solid-state imaging device called a CMOS image sensor. 7, the same components as those in FIG. 7 are denoted by the same reference numerals. In FIG. 8, one pixel 2a includes one photodiode PD, a reset transistor M1 having a source connected to the N-type layer of the photodiode PD, and an amplifying transistor having a gate connected to the N-type layer of the photodiode PD. It comprises a transistor M2 and a transfer transistor M3. The transistors M1, M2 and M3 are MOS type field effect transistors (FETs), which are usually n-channel F-channel transistors.
ET.

The source of the transistor M2 is connected to a double correlation sampling (CDS) circuit 5 and a load 6 through a transistor M3 having a switching function, and the transistor M3 operates as a source follower circuit. CD
The S circuit 5 includes two capacitors C1 and C2 and two switches S1 and S2. The non-ground terminal of the capacitor C1 is a switch S1, a capacitor C2.
Are connected in series to the source of the transistor M3,
The switch S1 side terminal C2a of the capacitor C2 is connected to the reference voltage Vref via the switch S2, and the switch S1 side terminal C1b of the capacitor C1 is connected to the signal output line via the switch S3.

The CDS circuit 5 and the load 6 are circuit components of one column of the pixel in the load and noise canceller 3 of FIG. The CDS circuit 5 has a state in which only the signal voltage from the pixel and the background noise on which no signal voltage is applied are included.
The sampler serves as a noise canceller that removes noise by sampling the two and taking the difference. The load 6 usually uses a constant current circuit.

Next, the operation of the conventional device will be described. Now, the pixel 2a in FIG. 8 is not the top row and the bottom row,
It is assumed that the pixel is somewhere in the middle row. First, the transistor M1 is turned on, the transistor M3 is turned off, and the terminal T1 on the N-type layer side of the photodiode PD is reset. At this time, the potential of the terminal T1 is set to the reset voltage (Vdd-Vthrst). Where Vd
d is a power supply voltage, and Vthrst is a threshold voltage of the transistor M1. In this reset state, since the transistor M3 is off, there is no output from the pixel 2a on the column signal line.

Next, with the transistor M1 turned off, light from a subject is incident on the photodiode PD to perform photoelectric conversion. Thereby, the photodiode P
In D, charges corresponding to the amount of incident light are accumulated. The capacitance Cpxl at the terminal T1 is equal to the capacitance Cpd of the photodiode PD.
, The gate capacitance Camp of the transistor M2, the diffusion capacitance Crst of the transistor M1, and the floating capacitance Cf of the wiring.
Consists of When the total charge Q occurs in the photodiode PD, a potential change of ΔV = Q / Cpxl occurs at the terminal T1. Meanwhile, the CDS circuit 5 is processing the output signals of the pixels in the other rows during that time.

When the CDS circuit 5 finishes processing the output signal of the pixel (not shown) in the row before the pixel 2a of interest and outputs the processing result through the switch S3 closed by the horizontal shift register 4, Subsequently, the CDS circuit 5 starts processing the pixel 2a of interest. The CDS circuit 5
First, it performs its own reset operation.

That is, the switches S1 and S2 are closed, and the potentials of the terminals C2a and C1b are changed to the reference potential Vr.
ef. In this state, when a high-level voltage is applied to the gate of the transistor M3 to turn on M3, the potential of the terminal T1 of the photodiode PD (Vdd-Vthrs)
t + △ V) is amplified by the transistor M2, and further (Vdd−V) through the drain and source of the transistor M3.
The potential of (thrst−Vthamp + ΔV) is output to the column signal line (that is, the terminal C2b). As a result, (Vdd-Vthrst-Vtam) is stored in the capacitor C2.
(p + △ V−Vref). Where Vt
hamp is the threshold voltage of the transistor M2.

Subsequently, the switch S2 is opened, and a reset voltage is applied to the gate of the transistor M1 to turn on M1. Then, the potential of the terminal T1 of the photodiode PD becomes (Vdd-Vthrst), so that the terminal C2b
Is (Vdd-Vthrst-Vthamp). As a result, the terminal C2b becomes (Vdd-Vthrst).
−Vthamp) − (Vdd−Vthrst−Vtha)
mp + ΔV) = − ΔV means that the potential has changed.
This is equal to the voltage change on the terminal T1 side of the photodiode PD. Therefore, only the voltage change due to the photoelectric conversion of the photodiode PD can be purely extracted by the above-described series of operations.

As a result, the potential of the terminal C2a (= terminal C1b) changes by a voltage change ΔV by a proportional component in which the capacitors C1 and C2 are connected in series. That is, Vref− {V · C1 / (C1 + C2)} (1) After that, the switch S1 is opened and turned off, and the processing result is held in the capacitor C1 to be on standby. Thereafter, the transistor M3 is turned off, and the output from the pixel 2a disappears. Subsequently, the switch S3 is closed at a certain timing by the horizontal shift register 4 in FIG.
The processing result of equation (1) held at 1 is output as a pixel signal. Thereafter, the switch S3 is opened and turned off, and returns to the initial reset state. The same operation as described above is performed for each pixel.

However, the CMOS image sensor shown in FIG. 8 has a problem with the shutter function. That is, in the CCD, the carriers are simultaneously transferred from the photodiode to the transfer area at a certain moment.
All pixels in the screen are synchronized, and the CCD essentially has a shutter function.

On the other hand, the CMOS image sensor shown in FIG. 8 reads out data sequentially for each row, so that an image created based on this information indicates a different time for each row. Therefore, extracting a still image results in a distorted image. Such shutters of images shifted in time are often called rolling shutters.

On the other hand, a shutter for producing a still image which is temporally aligned is often called a field shutter. A conventional CM having the configuration of FIG. 8 having only a rolling shutter function
One method for providing a field shutter function in an OS image sensor is to provide a mechanical shutter. That is, a mechanical shutter may be provided other than the element, and the shutter may be opened for a specific time. However, this method is costly and makes it difficult to capture moving images.

In order to provide a field shutter function, it is essential to have a switch for simultaneously extracting image information at a certain moment from all pixels and a storage unit for temporarily storing the information. Therefore, this is usually realized by adding the transistor M4 and the capacitor Ce to the pixel portion as shown in FIG. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. 9, the pixel 2b is different from the pixel 2a of FIG. 8 in that a MOS transistor M4 having a drain and a source connected between the N-type layer of the photodiode PD and the terminal T1.
And an adjustment capacitor Ce having one end connected to the terminal T1 and the other end grounded. The transistor M4 has a shutter function, and the capacitor Ce has a storage function. Note that the capacitor Ce may be sufficient with the gate capacitance of the transistor M2 in some cases. In such a case, the capacitor Ce need not be particularly provided. The operation in such a configuration is described below.

It is assumed that the pixel 2b is not a top row and a bottom row of the pixel portion, but is a pixel of a certain column in an intermediate row. In describing the pixel operation cycle, it is assumed that the output of the previous information has just been completed. In this state,
The transistors M1, M3, M4 are off. At this time, the potential of the terminal T1 is (Vdd-Vthrst). Here, Vdd is a power supply voltage, and Vthrst is a threshold voltage of the transistor M1. At this time, since the terminal T1 is not connected anywhere and is electrically floating, the terminal T1 remains at the reset potential. Further, since the transistor M3 is off, there is no output from the pixel 2b on the column signal line. On the other hand, the transistor M4 is also off, and thus the photoelectric conversion is performed in the photodiode PD that is electrically separated from the terminal T1. Pixel 2
b executes the photoelectric conversion in this way, and waits until the information of the pixels in all rows below itself is read.

In this manner, the signals of all the pixels are read out, and when a predetermined time elapses after the start of the photoelectric conversion, the transistors M4 of all the pixels are simultaneously turned on. Then, the charges accumulated on the N-type layer side of the photodiode PD are simultaneously transferred to the terminal T1 in all the pixels. As a result, the charge of the photodiode PD is lost, and the PD is reset. When the transfer is completed, the transistor M4 is turned off, and the photodiode PD starts photoelectric conversion again.

The capacitance Cpxl of the terminal T1 is
e, the gate capacitance Camp of the transistor M2, the diffusion capacitance Crst of the transistor M1, and the floating capacitance Cf of the wiring.
It consists of Therefore, assuming that the transferred total charge amount is Q, a potential change of ΔV = Q / Cpxl results in a terminal T1
Happens. Since the carriers to be transferred are electrons, the charge Q has a negative value, and accordingly, ΔV also has a negative value. Before the electric charge transfer, the potential of the terminal T1 becomes (Vdd-Vthrs).
t), (Vdd−Vthrs) after the charge transfer.
t + △ V).

When charge transfer is completed in all pixels, CDS
The circuit 5 performs signal processing for each row. During the processing of another row, the pixel of interest 2b waits while holding the electric charge in the capacitor Ce connected to the terminal T1. And
The CDS circuit 5 starts processing the pixel 2b of interest. First, it performs its own reset operation. That is, as described above, the switches S1 and S2 are closed and the terminal C2a
And the potential of the terminal C1b to the reference potential Vref. At this time, the switch S3 is open and off.
In this state, when a high-level voltage is applied to the gate of the transistor M3 to turn on M3, a column signal line (ie,
(Vdd-Vthrst-Vthamp) is connected to the terminal C2b).
+ △ V) is output. As a result, (Vdd−Vthrst−Vthamp + △) is stored in the capacitor C2.
(V-Vref).

Subsequently, when the switch S2 is opened and turned off, there is no connection to the terminal C2a (= terminal C1b), so that the terminal C2a is in an electrically floating state. Here, the transistor M1 is turned on once, turned off after a predetermined time, and the terminal T1 is reset. Then, the potential of the terminal T1 becomes (Vdd-Vthrst), so that the terminal C2b
Is (Vdd-Vthrst-Vthamp). Therefore, the potential of the terminal C2b is (Vdd-Vthr
st-Vthamp)-(Vdd-Vthrst-Vt
hamp + ΔV) = − ΔV. This is a component proportional to the amount of charge Q generated in the photodiode PD. Therefore, only the signal component obtained by the photoelectric conversion of the photodiode PD can be purely extracted by the above-described series of operations.

As a result, the potential of the terminal C2a (= terminal C1b) changes by a change of -ΔV by a proportional component in which the capacitors C1 and C2 are connected in series. That is, (1)
It changes by the same value as the expression. After that, the switch S1 is opened and turned off, and the processing result is held in the capacitor C1 to be on standby. Thereafter, the transistor M3 is turned off, and the pixel 2b is turned off.
The output from is lost. Subsequently, the switch S3 is closed at a certain timing by the horizontal shift register 4 in FIG. 7, and the processing result of Expression (1) held in the capacitor C1 is output as a pixel signal. Then switch S
3 is opened and turned off, and returns to the initial state. Thus, one cycle of a series of processing is completed, and the same operation is repeated thereafter.

[0026]

However, FIG.
There is a serious problem in the CMOS image sensor with a field shutter function, which is the conventional solid-state imaging device shown in FIG. That is, in the conventional device of FIG. 9, the charge of the photodiode PD is transferred to the terminal T1 which has been reset in advance, and after generating a certain potential and outputting it to the outside of the pixel, the charge is reset again to cancel the reference for cancellation. Level. That is, a reset operation at a different timing is used between when a signal is output and when a background is output. As described above, there is a problem that the kTC noise is not removed when the voltages obtained by the reset operation at different timings are compared.

This kTC noise is noise caused by thermal motion of electrons. For example, as shown in FIG. 10, setting the potential of a certain capacitor C to a certain potential V means that
Is given (or removed) by a predetermined number n of electrons having a charge q. The number n can be represented by the following equation.

N = V / (C · q) (2) As a specific operation, as shown in FIG. 10, a capacitor C is connected to a power source of a voltage V via a resistor R and a switch S4, and the switch S4 is connected. When the switch S4 is opened after a sufficiently long time after being closed, the above-mentioned number of electrons is stored in the capacitor C, and both ends are at the voltage V.

However, since the electrons are actually performing a thermal motion at random, while the switch S4 is closed, the number of electrons in the capacitor C sometimes becomes larger than n in some cases. In the case of, there is a variation in time, such as smaller than n. For this reason, when the switch S4 is opened and turned off, the number of electrons remaining in the capacitor C at that time may be larger or smaller than n by chance. This variation appears as noise called kTC noise.
kTC is k: Boltzmann's constant, T: absolute temperature, C: capacity, and the noise level Vi is represented by Vi = √ (kT / C) (3) in rms. As can be seen from the equation (3), the characteristic is that the noise level Vi depends only on the temperature and the capacity.

Therefore, comparing the two different reset timings at the terminal T1 of the CMOS image sensor in FIG.
i1 and Vi2 remain and cannot be canceled. There is no correlation between these noise levels Vi1 and Vi2. When comparing such uncorrelated noise levels, kTC noise is multiplied by √2, and Vi ′ = √ (2kT / C) (4)

As can be seen from the above equations (3) and (4), the kTC noise increases as the capacitance decreases. For this reason, in the configurations of FIGS. 8 and 9, as pixels are miniaturized, Cpxl cannot be gradually increased, and the kTC noise increases.

Here, the kTC noise is quantitatively estimated. For example, assume that the capacitance Cpxl of the terminal T1 becomes 8 fF. This numerical value of 8fF indicates that the pixel size is 5
When the diameter is less than μm, it is a realistic value.
At this time, the kTC noise component Vi ′ becomes about 1 mV at room temperature of T = 300 ° K. Assuming that the maximum amplitude of the signal is 2 V and the noise is only kTC noise, the S / N ratio of the CMOS image sensor with the field shutter function is 46d.
B. Since the S / N ratio of the CCD system is said to be 60 dB or more, it can be seen that the performance is considerably inferior to that of the CCD system only with kTC noise.

In the case of the CMOS image sensor having the simplest structure shown in FIG. 8, the capacitance Cpd of the photodiode PD is considerably larger than the capacitance of the terminal T1.
The problem is smaller than in the configuration of FIG. However, it is impossible to remove kTC noise with the configuration of FIG.

On the other hand, in the conventional CMOS image sensor having the configuration shown in FIG. 9, when the size is reduced, the number of transistors may be larger than the configuration shown in FIG. 8, and a large capacity cannot be gradually allocated to the terminal T1. Therefore, the necessity of suppressing the kTC noise is higher in the configuration of FIG. In the configuration of FIG. 9,
If a rolling shutter operation is performed instead of a field shutter, kTC noise can be removed.

The rolling shutter operation in the configuration of FIG. 9 is performed as follows. First, the transistors M4 and M3 are turned off. At this time, there is no output from the pixel 2b on the column signal line C2b. At this time, light is incident on the photodiode PD of the pixel 2b, photoelectric conversion is performed, and charges are accumulated in the photodiode PD. Further, the CDS circuit 5 processes signals of elements in other rows.

Next, the processing of the line of interest starts. The transistor M1 is turned on, and the terminal T1 is connected to (Vdd-Vth
rst). Then, the transistor M1
Is turned off. Subsequently, the transistor M3 is turned on. At this time, the transistor M4 remains off.
As a result, the signal (V) when the terminal T1 is reset
dd−Vthrst−Vthamp) is output to the column signal line. In the CDS circuit 5, the switches S1 and S
2 is closed, and (Vdd-Vthrst-
(Vthamp-Vref) is stored.

Next, the switch S2 is opened and turned off. Subsequently, the transistor M4 is turned on. Thereby, the charge of the photodiode PD flows into the terminal T1 through the drain and the source of the transistor M4. The capacitance Cpxl of the terminal T1 is the capacitance of the capacitor Ce, the gate capacitance Camp of the transistor M2, and the diffusion capacitance Cp of the transistor M1.
rst and the stray capacitance Cf of the wiring. Assuming that the total charge of the photodiode PD is Q, ΔV = Q / Cpxl
Only the potential change occurs at the terminal T1. This terminal T1
Is amplified by the transistor M2 and passed through the transistor M3 which is on (Vdd−Vthrst−V
(Tamp + ΔV) is output to the column signal line.

Thus, the change in the potential of the terminal C2b is (Vdd-Vthrst-Vthamp + ｍｐV)-(V
dd−Vthrst−Vthamp) = + ΔV, so that the potential Vref + ΔV · C1 / (C
1 + C2)} appears at terminal C1b. This potential is output to the horizontal shift register 4. Then, the transistor M
3 is turned off to bring it to the first reset state.

In this case, the reset is performed only once, and the background noise is removed from the signal in the same reset operation, so that the kTC noise can also be removed. Because of these characteristics, the configuration shown in FIG. 9 is more suitable for the field shutter operation than for the field shutter operation.
Often used in rolling shutter operation with low noise.

As described above, in any of the conventional solid-state imaging devices shown in FIGS. 8 and 9, the photocharge conversion function, the charge temporary storage function, and the charge-voltage conversion function of the photodiode PD are not independent. , One photodiode PD and three transistors M1 to M as shown in FIG.
The solid-state imaging device having a pixel configuration of 3 has a feature that the above three functional units are integrated and is very simple in configuration, but as a result, a field shutter function and a kTC noise canceling function can be realized. Therefore, there is a problem that it is not possible to obtain a high-quality still image that is uniform in time.

Further, in the solid-state imaging device having a pixel configuration including one photodiode PD, four transistors M1 to M4, and one capacitor Ce shown in FIG. While still images can be obtained, the field shutter function and k
There is a problem that only one of the TC noise canceling functions can be used.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a solid-state imaging device that can simultaneously realize a field shutter function and a kTC noise cancellation function.

Another object of the present invention is to provide a solid-state imaging device having a structure which is advantageous for miniaturization by reducing the area of a photodiode.

[0044]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a photodiode, a converter for converting a charge obtained by photoelectrically converting the photodiode into a potential change, and resetting the converter. A plurality of pixels each including a transistor for resetting and output means for outputting the potential of the conversion unit to the outside are arranged in a two-dimensional matrix or a one-dimensional line, and a signal voltage and a signal voltage from the pixel are In a solid-state imaging device equipped with a noise canceller that removes noise by sampling two background noises that are not on the ground and taking the difference between the two, charge is transferred between the photodiode and the conversion unit in the pixel. A capacitor for temporary storage is provided, and a first charge transfer transistor is provided between the capacitor and the photodiode. A second charge transfer transistor is provided between the converter and the converter, and after resetting the converter by the reset transistor, the potential of only background noise without a signal is output by the output means and stored in the noise canceller. After that, the charge that has been photoelectrically converted by the photodiode and transferred to the capacitor at the same time for all pixels through the first charge transfer transistor and accumulated is transferred to the second charge transfer transistor.
The new potential generated in the conversion unit is output to the noise canceller by the output means, and the difference from the potential of only the background noise previously stored in the noise canceller is calculated. And a control means for extracting the difference as a true signal.

According to the present invention, after the electric charge obtained by the photoelectric conversion by the photodiodes of all the pixels at the same time is accumulated in the capacitor, when the electric charge is output to the outside through the output means, the reset transistor and the output means are operated to operate the signal. The potential of only the background noise that is not riding is transmitted to the noise canceller and stored, and then the signal corresponding to the electric charge stored in the capacitor is output from the conversion unit to the noise canceller through the output means, so that the noise of the photodiode in the noise canceller is reduced. Only a signal component proportional to the charge generated by the conversion can be extracted.

In order to achieve the above-mentioned object, the present invention provides a first charge transfer transistor connected to a photodiode and a second charge transfer transistor connected to a converter in a pixel. A MOS gate which is provided between the first and second charge transfer transistors and is provided immediately below the charge transfer transistor, and which stores the charge from the photodiode. After outputting the potential of only the background noise that does not ride on the output means and storing it in the noise canceller, photoelectrically converts it with a photodiode and transfers it through the first charge transfer transistor to all pixels simultaneously immediately below the MOS gate for accumulation. The stored charge is transferred to the conversion unit through the second charge transfer transistor, and as a result, a new potential generated in the conversion unit is transferred. Output by the force means to the noise canceller, taking the difference between the background noise only potential previously saved in a noise canceller, in which a structure having a control means for taking the difference as a true signal.

According to the present invention, after the electric charges obtained by photoelectric conversion at the same time by the photodiodes of all the pixels are accumulated immediately below the MOS gate, when the electric charges are outputted to the outside through the output means, the reset transistor and the output means are operated. Outputting the potential of only the background noise without a signal on the output means and storing it in the noise canceller, and then outputting the signal corresponding to the electric charge accumulated immediately below the MOS gate from the conversion unit to the noise canceller through the output means. Accordingly, it is possible to extract only a signal component proportional to the charge generated by the photoelectric conversion of the photodiode in the noise canceller.

Here, by connecting a second reset transistor, which is switched at an arbitrary timing and resets the photodiode when turned on, to a connection point between the photodiode and the first charge transfer transistor, an arbitrary timing is obtained. Resets the photodiode.

Further, in order to achieve the above object, the present invention provides a photodiode, a first reset transistor connected to the photodiode, and an electric charge obtained by photoelectrically converting the photodiode into a potential change. A plurality of pixels each including a conversion unit for conversion, a second reset transistor for resetting the conversion unit, and an output unit for outputting the potential of the conversion unit to the outside are provided in a two-dimensional matrix or a one-dimensional line. A solid-state imaging device having a noise canceller that is arranged and samples two states of a signal voltage from a pixel and a background noise only where no signal voltage is applied, and removes the noise by taking the difference therebetween. A first charge transfer transistor connected to the photodiode and the first reset transistor in the pixel; A second charge transfer transistor having one end connected to the means, a second reset transistor connected to the second charge transfer transistor and the output means, and a first and second charge transfer transistor. A MOS gate for accumulating charges from the photodiode, which is provided close to each other, and a MOS gate for accumulating charges from the photodiode is provided for each pixel, and after the photodiode is reset by the first reset transistor, the first reset transistor Is turned off, and the first charge transfer transistor is turned on while a first voltage for setting the potential immediately below the MOS gate to an intermediate level between the maximum time and the minimum time is applied to the MOS gate. In the first shutter time, the charge photoelectrically converted by the photodiode is transferred to and stored immediately below the MOS gate. After that, the first charge transfer transistor is turned off, and the photodiode is reset again by the first reset transistor. Then, the first reset transistor is turned off, and the potential immediately below the MOS gate is set to the first potential. The first charge transfer transistor is turned on in a state where the second voltage for setting to a level larger than the voltage of the second gate is applied to the MOS gate, and the second charge transfer transistor is turned on.
During the shutter time, the control unit turns off the first charge transfer transistor after transferring and accumulating the charge photoelectrically converted by the photodiode immediately below the MOS gate.

According to the present invention, the electric charge photoelectrically converted by the photodiode during the longer first shutter time is added to the electric charge photoelectrically converted by the photodiode during the shorter second shutter time immediately below the MOS gate. be able to.

[0051]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an equivalent circuit diagram of one pixel circuit of the solid-state imaging device according to the first embodiment of the present invention. 8, the same components as those in FIGS. 8 and 9 are denoted by the same reference numerals. In the first embodiment shown in FIG.
c is different from the pixel 2b of FIG. 9 by adding one MOS field effect transistor (FET) and one capacitor,
This is a photodiode, five transistor, and two capacitor configuration. That is, in the pixel 2c, the N-type layer side of the photodiode PD is connected to the connection point (terminal) T1 to the source of the resetting transistor M1 and the gate of the transistor M2 via the drain and source of the transistor M5 and the drain and source of the transistor M6. Connected by

The common connection point between the transistors M5 and M6 is grounded via a capacitor Cex. Further, the terminal T1 is grounded via the capacitor Ce. Further, the source of the transistor M2 is connected to the CDS circuit 5 and the load 6 via the drain and the source of the output transistor M3, respectively. Note that the capacitor Ce
x is composed of, for example, an N ^- diffusion layer formed on the surface of the p substrate. The capacitor Ce has a capacitance Cpxl of the terminal T1 and a gate capacitance Camp of the transistor M2 and a capacitance of the transistor M1.
When the sum of the diffusion capacitance Crst and the floating capacitance Cf of the wiring is sufficient, there is no particular need to provide them. The capacitance Cp of the terminal T1
xl constitutes a conversion unit for converting the above-mentioned electric charge into a voltage together with the capacitor Ce.

Next, the operation of this embodiment will be described. Here, it is assumed that the pixel 2c is not a top row and a bottom row of the pixel portion, but is a pixel in a certain column in an intermediate row. The switching control of each of the transistors M1, M3, M5 and M6 is performed based on a signal from a control circuit (not shown).

As a starting point of the explanation of the operation cycle, the operation starts from the point that the output of the previous signal from the pixel 2c has just finished. In this state, the transistor M
1, M6 is off, and the terminal T1 is in an electrically floating state. At the terminal T1, the charge that has been photoelectrically converted by the photodiode PD in the previous cycle and transferred through the transistors M5 and M6 remains. The transistor M3 is also off, and there is no output from the pixel 2c to the column signal line.

On the other hand, the transistor M5 is also off, and the photodiode PD performs photoelectric conversion while being electrically separated from the others, and accumulates electric charges. In addition, the charge existing in the capacitor Cex has been transferred to the terminal T1 through the transistor M6, and the capacitor Cex has no charge.

In such a state, the pixel 2c is waiting for the CDS circuit 5 to complete the processing of the pixels in another row. When the reading of signals from all the pixels is completed, the transistor M5 turns on all the pixels including the pixel 2c at the same time.
Then, the charge Q stored in the photodiode PD
Are simultaneously transferred to the respective capacitors Cex through the respective transistors M5 in all the pixels. As a result, the charge of the photodiode PD disappears and is reset. After completion of the charge transfer, the transistor M5 is turned off, and the photodiode PD performs photoelectric conversion again and starts accumulating charges.

Thereafter, the pixel 2c waits while the CDS circuit 5 is processing pixels in another row. When the processing of the pixel 2c of interest starts, the pixel 2c performs a reset operation of the terminal T1. That is, a high-level signal from a control circuit (not shown) is applied to the gate electrode of the transistor M1 to turn on M1. At this time, the transistor M
3, M6 remains off. As a result, the potential of the terminal T1 becomes (Vdd-Vthrst). Where Vdd
Is a power supply voltage, and Vthrst is a threshold voltage of the transistor M1.

Thereafter, the signal to the gate electrode of the transistor M1 becomes low level, and M1 is turned off. As a result, the terminal T1 returns to an electrically floating state, and the reset operation is completed. At this time, since the kTC noise component Vktc is put on the terminal T1, the potential of the terminal T1 becomes (Vdd−
(Vthrst + Vktc). Although Vktc is not explicitly described in the description of the related art, it will be shown to clarify that it can be removed by this embodiment.

On the other hand, the CDS circuit 5 also prepares for signal processing of the pixel 2c. That is, the switch S1,
S2 is closed, and the terminals C2a and C1b are set to the reference potential Vref. In this state, a high-level signal is applied to the gate electrode of the transistor M3 from a control circuit (not shown) to turn on M3. Therefore, (Vdd−Vthrst + Vktc−) is applied to the column signal output line, that is, the terminal C2b.
Vthamp) is output. Where Vtha
mp is a threshold voltage of the amplification transistor M2.
As a result, (Vdd-Vthrst) is stored in the capacitor C2.
+ Vktc−Vthamp−Vref).

Next, the CDS circuit 5 opens the switch S2 and turns it off, so that the terminal C2a (= terminal C1b) floats. Here, the transistor M6 is turned on when a high-level signal is applied to its gate electrode from a control circuit (not shown). Then, the electric charge Q held in the capacitor Cex is transferred to the terminal T through the transistor M6.
Transferred to 1. After the completion of the charge transfer, the transistor M6 is turned off. As a result, the capacitor Cex has no charge, and is in a reset state.

On the other hand, a potential change due to the charge Q occurs at the terminal T1. The capacitance Cpxl of the terminal T1 is
And the gate capacitance Camp of the transistor M2,
It is composed of the diffusion capacitance Crst of the transistor M1 and the floating capacitance Cf of the wiring. When the electric charge Q enters here, a potential change of ΔV = Q / Cpxl occurs. Therefore, the potential of the terminal T1 is (Vdd-Vthrst + Vk
tc + △ V).

When a potential change occurs at the terminal T1, the potential change is amplified by a source follower circuit formed by a transistor M2, and further transmitted to a column signal output line, that is, a terminal C2b through a transistor M3 which is in an ON state. As a result, the potential of the terminal C2b becomes (Vdd-Vthrst + V
ktc−Vthamp + △ V). That is, the terminal C
2b is (Vdd-Vthrst + V
ktc−Vthamp + △ V) − (Vdd−Vthrs
(t + Vktc−Vthamp) = △ V, and is affected only by the component due to the charge amount Q due to the photoelectric conversion of the photodiode PD, and is not affected by kTC noise.

In response to the potential change of the terminal C2b, the terminal C2a (= terminal C1b), which is in an electrically floating state,
The proportional component Vre when the capacitors C1 and C2 are connected in series
A potential change of f + {V · C1 / (C1 + C2)} occurs. After that, the switch S1 is opened and turned off, and the processing result of the above-described potential change is held in the capacitor C1. Then, the transistor M3 is turned off, and the output from the pixel 2c disappears. Thereafter, the switch S3 is turned on by a horizontal shift register (not shown), and the processing result of the pixel 2c held in the capacitor C1 is output as a pixel signal through the switch S3. Then, switch S3
Is re-opened and turned off, and one cycle in the pixel 2c ends. After that, the same is repeated from the beginning again.

The description of the operation of the above embodiment is an example, and the present invention is not limited to this. For example, in the above description, the reset of the terminal T1 by the transistor M1 is performed immediately before the reset potential of the terminal T1 is output. However, the present invention is not limited to this. It may be performed once somewhere before the signal output operation. For example, the transistor M1 may be turned on immediately after the previous signal output ends, and the reset operation of the terminal T1 may be performed first.

In the above description, the reset of the capacitor Cex is performed by completely transferring the stored charge of Cex. However, if the stored charge is too large, the transfer cannot be completed and the charge remains in Cex. An afterimage may occur. Therefore, before the transistor M5 is turned on and the charge is transferred from the photodiode PD to the capacitor Cex, the operation of once turning on the transistors M1 and M6 and forcibly resetting the capacitor Cex may be performed. .

As described above, according to the present embodiment, the CD
In the S circuit 5, the signal is the background noise (Vdd-Vt) from the signal due to the charge transfer of the photodiode PD.
hrst-Vthamp + Vktc) is removed, and the voltage change ΔV proportional to the total charge Q generated by the photoelectric conversion of the photodiode PD becomes purely the column signal output line C2.
b, a kTC noise canceling function can be realized.

The electric charge is stored in the capacitor C for a predetermined time.
ex can also be held. Furthermore, in this embodiment, since the charges obtained by photoelectrically converting the light simultaneously incident on the photodiodes of all the pixels including the photodiode PD are converted into a voltage and output, a field shutter function is provided. And still images at the same time can be obtained. As described above, it is possible to capture a still image with higher image quality as compared with the related art.

By the way, although the area of the pixel is limited, if the number of transistors is increased steadily, the area of the photodiode is reduced accordingly. Then, the charge amount Q generated in the photodiode decreases, and the sensitivity to brightness as an image sensor decreases. However, in the configuration of the present embodiment, the above-described reduction in the area of the photodiode does not become disadvantageous but works rather advantageously.

That is, in this embodiment, the terminal T1
Can be expressed by ΔV = Q / Cpxl, so that decreasing Cpxl can increase the charge-voltage conversion rate. Therefore, if Cpxl is reduced by the rate at which the area of the photodiode is reduced, the sensitivity becomes constant. Further, the smaller the capacitance Cpxl, the higher the sensitivity, which is advantageous.

On the other hand, in the conventional configurations shown in FIGS. 8 and 9, as can be seen from the equations (3) and (4), when the capacitance Cpxl is reduced, the kTC noise increases, and thus the conventional Cpxl Cannot be reduced. However, according to the configuration of the present embodiment, the field shutter operation and the kTC noise removal can be performed at the same time, so that Cpxl can be reduced and the area of the photodiode can be reduced. Therefore, the configuration is advantageous for miniaturization.

Next, a second embodiment of the present invention will be described. A feature of the present invention is that a photodiode for performing photoelectric conversion, a site for temporarily holding a carrier generated by the photodiode, and a site for converting a charge of the carrier into a voltage are independently provided. Here, the structure of the site for temporarily holding the carrier is not limited to the capacitor, and another method is also possible. In the second embodiment, carriers are held by MOS gates.

FIG. 2 is an equivalent circuit diagram of one pixel of a solid-state imaging device according to a second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. This second
In this embodiment, as shown in FIG. 2, a MOS gate Mccd is arranged close to transistors M5 and M6 instead of capacitor Cex of FIG.
It is characterized in that a pixel 2d having a structure capable of holding electric charges under ccd is used. FIG. 3 shows how the potentials and charges move at this time. Note that, similarly to FIG. 1, Ce is an additional capacity for adjustment, so that its function is to omit it.

Next, the operation of this embodiment will be described with reference to FIGS. It is assumed that the pixel 2d is not a top row and a bottom row of the solid-state imaging device, but is a pixel in a column having some intermediate row. As a starting point for explaining the operation cycle,
It starts from the point that the output of the previous signal from the pixel 2d has just finished.

In this state, the transistors M1 and M6 are off, and the terminal T1 is in an electrically floating state. In the terminal T1, the charge that has been photoelectrically converted by the photodiode PD in the previous cycle and transferred through the transistors M5, Mccd, and M6 remains as it is. The transistor M3 is also off, and there is no output from this pixel 2d to the column signal line. On the other hand, the transistor M5 is also off, and the photodiode PD performs photoelectric conversion as shown in FIG.
Electric charges are accumulated as shown in FIG. In addition, Mccd is also off, and no charge is stored, and no charge is present.

In such a state, the pixel 2d is waiting for the CDS circuit 5 to finish processing the pixels on the other rows. When the reading of signals from all the pixels is completed and a predetermined time has elapsed from the start of the photoelectric conversion, the transistor M5 and the MOS gate Mccd are simultaneously turned on in all the pixels including the pixel 2d as shown in FIG. Then, the electric charge Q stored in the photodiode PD is simultaneously transferred to all the pixels in the direction directly below each MOS gate Mccd through each transistor M5. As a result, the charge of the photodiode PD disappears and is reset.

After the completion of the charge transfer, the transistor M5 is turned off as shown in FIG.
The data is transferred directly below the S gate Mccd. Again, the photodiode PD performs photoelectric conversion and starts accumulating charges. On the other hand, Mccd remains on and continues to hold charge under the gate. The pixel 2d is in this state,
While the DS circuit 5 is processing pixels in another row, it keeps waiting.

Thereafter, when the processing of the pixel 2d of interest starts, the pixel 2d performs a reset operation of the terminal T1. That is, a high-level signal from a control circuit (not shown) is applied to the gate electrode of the transistor M1 to turn on M1. At this time, the transistors M3 and M6 remain off. As a result, the potential of the terminal T1 becomes (Vdd-Vt).
hrst). Here, Vdd is the power supply voltage, Vth
rst is the threshold voltage of the transistor M1.

Thereafter, the signal to the gate electrode of the transistor M1 becomes low level, and M1 is turned off. As a result, the terminal T1 returns to an electrically floating state, and the reset operation is completed. At this time, since the kTC noise component Vktc is put on the terminal T1, the potential of the terminal T1 becomes (Vdd−
(Vthrst + Vktc).

On the other hand, the CDS circuit 5 also prepares for signal processing of the pixel 2d. That is, the switch S1,
S2 is closed, and the terminals C2a and C1b are set to the reference potential Vref. In this state, a high-level signal is applied to the gate electrode of the transistor M3 from a control circuit (not shown) to turn on M3. Therefore, (Vdd−Vthrst + Vktc−) is applied to the column signal output line, that is, the terminal C2b.
Vthamp) is output. Where Vtha
mp is a threshold voltage of the amplification transistor M2.
As a result, (Vdd-Vthrst) is stored in the capacitor C2.
+ Vktc−Vthamp−Vref).

Next, the CDS circuit 5 opens the switch S2 to turn it off, so that the terminal C2a (= terminal C1b) floats. Here, when a high-level signal is applied to the gate electrode of the transistor M6 from a control circuit (not shown), the transistor M6 is turned on as shown in FIG. On the other hand, when a low-level signal is applied to the MOS gate Mccd, the charge Q immediately below Mccd is transferred to the terminal T1 through the transistor M6. After the completion of the charge transfer, the transistor M6 is turned off, and all charges are transferred to the terminal T1, as shown in FIG.

As a result, a potential change due to the electric charge Q occurs at the terminal T1. The capacitance Cpxl of the terminal T1 is determined by the capacitance of the capacitor Ce and the gate capacitance Camp of the transistor M2.
And the diffusion capacitance Crst of the transistor M1 and the floating capacitance Cf of the wiring. When the electric charge Q enters here, a potential change of ΔV = Q / Cpxl occurs.
Therefore, the potential of the terminal T1 becomes (Vdd−Vthrst +
Vktc + △ V).

When a potential change occurs at the terminal T1, the potential change is amplified by a source follower circuit constituted by a transistor M2, and further transmitted to a column signal output line, that is, a terminal C2b through a transistor M3 which is in an ON state. As a result, the potential of the terminal C2b becomes (Vdd-Vthrst + V
ktc−Vthamp + △ V). That is, the terminal C
2b is (Vdd-Vthrst + V
ktc−Vthamp + △ V) − (Vdd−Vthrs
(t + Vktc−Vthamp) = △ V, and is affected only by the component due to the charge amount Q due to the photoelectric conversion of the photodiode PD, and is not affected by kTC noise.

According to the potential change of the terminal C2b, the terminal C2a (= terminal C1b), which is in an electrically floating state,
The proportional component Vre when the capacitors C1 and C2 are connected in series
A potential change of f + {V · C1 / (C1 + C2)} occurs. After that, the switch S1 is opened and turned off, and the processing result of the above-described potential change is held in the capacitor C1. Then, the transistor M3 is turned off, and the output from the pixel 2c disappears.

Thereafter, the switch S3 is turned on by a horizontal shift register (not shown), and the processing result of the pixel 2d held in the capacitor C1 is output as a pixel signal through the switch S3. Subsequently, the switch S3 is opened again to be turned off, and one cycle in the pixel 2d ends. After that, the same is repeated from the beginning again.

The operation described in the above embodiment is an example, and the present invention is not limited to this. For example, in the above description, the reset of the terminal T1 by the transistor M1 is performed immediately before the reset potential of the terminal T1 is output. However, the present invention is not limited to this. It may be performed once somewhere before the signal output operation.

By the above operation, the signal to be subtracted and the background noise are taken at the reset potential performed at the same timing, so that the kTC noise is canceled. In addition, since the photoelectrically converted charges of all pixels at the same time are sequentially output from the horizontal shift register, a field shutter function is realized.

Next, the third embodiment and the fourth embodiment of the present invention will be described.
An embodiment will be described. FIG. 4 is an equivalent circuit diagram of one pixel of a third embodiment of the solid-state imaging device according to the present invention,
FIG. 5 shows an equivalent circuit diagram of one pixel of the fourth embodiment of the solid-state imaging device according to the present invention. In both figures, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

In the first and second embodiments, the photodiode PD is reset by transferring carriers (charges). However, in this method, the photodiode PD is reset once per field, and the exposure time is always fixed. In this case, since the shutter speed cannot be freely set, it is convenient to attach an independent photodiode reset transistor to the photodiode PD.

Therefore, in the third embodiment of the present invention shown in FIG. 4, the pixel of the first embodiment is provided with a photodiode reset transistor M7.
In the fourth embodiment of the present invention, the pixel of the second embodiment has a photodiode reset transistor M
7 is provided. That is, in FIGS. 4 and 5, the N-type layer of the photodiode PD is connected to the power supply voltage Vdd via the source and drain of the MOS field-effect transistor M7.

4 and 5, when a high-level reset signal is applied to the gate of the transistor M7, the transistor M7 is turned on, and the transistor M7 is turned on.
The power supply voltage Vdd is applied to the N-type layer of the photodiode PD via the drain and the source of No. 7 to reset it. That is, even if the transfer of the carriers of the photodiode PD is not completed, the photodiode PD can be reset at an arbitrary timing by turning on the transistor M7 at an arbitrary timing. Therefore, in the third and fourth embodiments, the shutter time can be set freely.

In the fourth embodiment shown in FIG. 5, since the carrier holding portion is constituted by the CCD type MOS gate Mccd, the portion where the carrier immediately below the MOS gate Mccd is held by the potential of the MOS gate Mccd. Can be moved freely. Thereby, an advantageous operation mode can be set.

Next, another operation mode of the fourth embodiment of the present invention will be described. As a method of expanding the dynamic range, a method of adding a shutter having a short shutter time and a shutter having a long shutter time has been conventionally known. A shutter having a long shutter time is, for example, 10 msec, and a shutter having a short shutter time is, for example, 0.5 msec.

As is well known, when the shutter time is long, dark places are well photographed, but bright places are solid white. On the other hand, if the shutter time is short,
Images in bright places are better, but dark places are solid black. Therefore, by adding both pieces of information, it is possible to capture both dark and bright places together.

Hereinafter, the operation in another mode of the fourth embodiment will be specifically described based on the configuration shown in FIG. 5A, the same components as those in FIG. 5 are denoted by the same reference numerals. The transistors M7, M
Illustrations of 1 to M3 are omitted. First, after the photodiode PD is reset, photoelectric conversion is performed for the longer shutter time Tl. Subsequently, the MOS gate M
A first potential is applied to the Mccd gate electrode such that the potential of the ccd channel becomes approximately half the potential when the potential of Vdd is applied to the Mccd gate electrode.

When the transistor M5 is turned on in this state, as shown in FIG. 6B, carriers (charges) are transferred under the MOS gate Mccd through the transistor M5. Subsequently, the transistor M5 is turned off. Thereby, as shown in FIG. 6B, the potential of the potential of the transistor M5 increases, and the MOS gate Mccd
The electric charge is held immediately below the.

Next, after resetting the photodiode PD again, photoelectric conversion is performed only for Ts having a short shutter time. As a result of this photoelectric conversion, electric charges are accumulated in the photodiode PD as schematically shown by a black circle in FIG. Subsequently, the first electrode is applied to the gate electrode of the MOS gate Mccd.
Is applied, for example, Vdd. As a result, the potential of the potential immediately below Mccd becomes further deeper than the previous state.

In this state, when the transistor M5 is turned on, as shown in FIG. 6D, the MOS gate Mccd
Then, the electric charge accumulated in the photodiode PD flows through the transistor M5, and the previous shutter time Tl
, The charge of the current shutter time Ts is M
It is added just below the ccd. By outputting the charge thus generated to Tl, a signal having a wide dynamic range can be output.

In the above description, the NMOS FE
Although T is used, if the N-type and P-type are switched and the direction of the voltage is reversed, the same effect can be naturally obtained with the PMOS FET.

[0099]

As described above, according to the present invention,
After accumulating the charge obtained by photoelectric conversion at the same time by the photodiodes of all pixels in a charge storage unit such as a capacitor or a MOS gate, when outputting to the outside through output means,
The reset transistor and the output means are operated to send a predetermined potential to the noise canceller, and then a signal corresponding to the electric charge accumulated in the charge accumulating unit is output to the noise canceller through the output means. To extract only signal components proportional to the charge generated by
The field shutter operation by simultaneous photoelectric conversion of all pixels and the removal of background noise (kTC noise removal) by the noise canceller can be performed at the same time, whereby a high-quality still image can be captured.

According to the present invention, the charge photoelectrically converted by the photodiode in the longer first shutter time and the charge photoelectrically converted by the photodiode in the shorter second shutter time are transferred to the MOS gate. Since the signals are added immediately below, a signal having a wide dynamic range can be output.

Further, according to the present invention, a voltage inversely proportional to the capacitance at the common connection terminal of the reset transistor, the second charge transfer transistor, and the output means is generated at the common connection terminal. Therefore, since the above-described capacitance can be reduced in accordance with the reduction in the area of the photodiode, a configuration advantageous for miniaturization can be obtained.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of one pixel according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one pixel according to the second embodiment of the present invention.

FIG. 3 is a diagram showing a state of potential and charge movement of a main part of FIG. 2;

FIG. 4 is an equivalent circuit diagram of one pixel according to a third embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of one pixel according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation in another mode according to the fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of an example of the entire solid-state imaging device.

FIG. 8 is an equivalent circuit diagram of one pixel of an example of a conventional solid-state imaging device.

FIG. 9 is an equivalent circuit diagram of another pixel of another example of the conventional solid-state imaging device.

FIG. 10 is a diagram showing that a potential of a certain capacitor C is set to a certain potential V;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Vertical shift register 2c, 2d Pixel of 1st, 2nd embodiment 3 Load and noise canceller 4 Horizontal shift register 5 CDS circuit 6 Load PD photodiode M1 Reset field effect transistor M2 Amplification field effect transistor (output means) M3 Output field effect transistor (output means) M5, M6 Charge transfer transistor (first and second charge transfer transistors) M7 Photodiode reset field effect transistor Mccd MOS gate Cex Charge storage capacitor Ce Capacitance of converter Adjustment capacitor S1, S2, S3 Switch T1 terminal

Claims (4)

[Claims] 1. A photodiode, a converter for converting electric charge obtained by photoelectric conversion of the photodiode into a potential change, a reset transistor for resetting the converter, and a potential of the converter. A plurality of pixels each including an output unit for outputting to the outside are arranged in a two-dimensional matrix or a one-dimensional line, and only a signal voltage from the pixel and a background noise without a signal voltage are present. In a solid-state imaging device provided with a noise canceller that removes noise by sampling one and taking a difference between the two, a capacitor for temporarily storing charge between the photodiode and the conversion unit is provided in the pixel. ,
A first charge transfer transistor is provided between the capacitor and the photodiode, and a second charge transfer transistor is provided between the capacitor and the conversion unit. The reset unit resets the conversion unit. Later, after outputting the potential of only background noise on which no signal is carried by the output means and storing the potential in the noise canceller, photoelectric conversion is performed by the photodiode, and all the pixels are simultaneously transferred to the capacitor through the first charge transfer transistor. Transferring the transferred and accumulated charge to the conversion unit through the second charge transfer transistor; and outputting a new potential generated in the conversion unit to the noise canceller by the output unit. Of the background noise only stored in advance in A solid-state imaging device comprising: a control unit that obtains a difference from a position and extracts the difference as a true signal. 2. A photodiode, a converter for converting electric charge obtained by photoelectric conversion of the photodiode into a potential change, a reset transistor for resetting the converter, and a potential of the converter. A plurality of pixels each including an output unit for outputting to the outside are arranged in a two-dimensional matrix or a one-dimensional line, and only a signal voltage from the pixel and a background noise without a signal voltage are present. In a solid-state imaging device including a noise canceller that removes noise by sampling one and taking a difference between them, a first pixel connected to the photodiode in the pixel is provided.
A charge transfer transistor, a second charge transfer transistor connected to the converter, and the first and second charge transfer transistors. MO that accumulates electric charges
An S gate is provided. After resetting the conversion unit by the reset transistor, a potential of only background noise without a signal is output by the output unit and stored in the noise canceller. The charges which have been converted and transferred through the first charge transfer transistor to all the pixels at the same time immediately below the MOS gate and stored are transferred to the conversion unit through the second charge transfer transistor. A new potential generated in the section is output to the noise canceller by the output means, a difference from a potential of only the background noise stored in advance in the noise canceller is obtained, and the difference is extracted as a true signal. A solid-state imaging device comprising means. 3. A second reset transistor, which is switched at an arbitrary timing and resets the photodiode when turned on, is connected to a connection point between the photodiode and the first charge transfer transistor. The solid-state imaging device according to claim 1. 4. A photodiode, a first reset transistor connected to the photodiode, a converter for converting a charge obtained by photoelectric conversion of the photodiode into a potential change, and a converter for: A plurality of pixels each including a second resetting transistor for resetting, and an output unit for outputting the potential of the conversion unit to the outside are arranged in a two-dimensional matrix or a one-dimensional line. A solid-state imaging device including a noise canceller that removes noise by sampling two of a signal voltage and a background noise only where no signal voltage is applied, and taking a difference between the two. A first charge transfer transistor connected to the photodiode and the first reset transistor; A second charge transfer transistor, and a MOS gate that is provided between the first and second charge transfer transistors and that is provided immediately below the second charge transfer transistor and that stores charges from the photodiode. After the photodiode is reset by a first reset transistor, the first reset transistor is turned off, and the potential immediately below the MOS gate is set to an intermediate level between the maximum time and the minimum time. While the first voltage is being applied to the MOS gate, the first charge transfer transistor is turned on, and the charge photoelectrically converted by the photodiode is transferred directly below the MOS gate for a first shutter time. The first charge transfer transistor is turned off, and the first reset transistor is again turned on. After resetting the photodiode by motor, said first reset transistor is turned off, and the MOS
The first charge transfer transistor is turned on in a state where a second voltage for setting the potential immediately below the gate to a level higher than the first voltage is applied to the MOS gate, and the first charge transfer transistor is turned on. Control means for transferring the charge photoelectrically converted by the photodiode to a position immediately below the MOS gate for a second shutter time shorter than the shutter time, and then turning off the first charge transfer transistor. A solid-state imaging device comprising: