JP2002064100A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [PROBLEMS] To improve the reliability of a semiconductor device by improving conduction failure between a base metal film to which a bump is connected and an extraction electrode as an uppermost layer wiring on a substrate. SOLUTION: A through hole 4 reaching a lead electrode 2 is provided.
Is formed on the inorganic insulating film 3a, the exposed surface of the extraction electrode 2 is sputter-etched, and then the pattern of the high melting point metal film 6 is formed continuously in a vacuum so as to cover the exposed extraction electrode 2. Next, the upper layer of the refractory metal film 6 is made of P
After forming a pattern of the IQ film 3b,
The underlying metal film 7 is patterned in contact with the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique and, more particularly, to a controlled collapse bond (CCB).
ing) A technology effective when applied to a semiconductor device having an electrode conductor pattern to which a bump is connected.

[0002]

2. Description of the Related Art For example, as described in Japanese Patent Application Laid-Open No. 5-114655, a CCB bump is bonded to an electrode conductor pattern (hereinafter referred to as a base metal film) formed on a main surface of a semiconductor chip. And the underlying metal film is
It is electrically connected to a lead electrode, which is the uppermost layer wiring of the semiconductor chip, through a through hole formed in the surface protection film. The surface protective film is the final insulating film among the insulating films formed on the semiconductor chip, and is formed by laminating an inorganic insulating film and a polyimide resin film (hereinafter, referred to as a PIQ film) in order from the lower layer. The lead electrode is made of, for example, an aluminum (Al) film, an Al-silicon (Si) alloy film, or an Al-Si-copper (Cu) alloy film.

The following is a method of forming a base metal film studied by the present inventor, the outline of which is as follows.

[0004] First, after depositing an inorganic insulating film on the upper layer of the extraction electrode, the inorganic insulation film is processed by dry etching using a resist pattern as a mask to expose the surface of the extraction electrode. Next, a photosensitive PIQ is formed on the inorganic insulating film.
After applying the film, the PIQ film is exposed and developed by lithography, and then cured and baked. As a result, through holes are formed in the surface protection film made of the PIQ film and the inorganic insulating film on the extraction electrode. next,
After depositing a base metal film on the PIQ film, a pattern of the base metal film is formed using the resist pattern as a mask.

[0005]

However, the present inventor has studied that the resist pattern used for processing the inorganic insulating film is removed by the asher treatment using ozone (O ₃ ), so that the exposed extraction electrode is exposed. It has been clarified that the surface of the Al film or the Al alloy film constituting the oxide film is oxidized, and a problem arises in that an alumina (Al ₂ O ₃ ) layer is formed on the surface of the extraction electrode. For this reason, conduction failure occurs between the underlying metal film and the extraction electrode, and there is a concern that the reliability of the semiconductor device may be reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the reliability of a semiconductor device by improving conduction failure between a base metal film to which a bump is connected and an extraction electrode which is the uppermost wiring on a substrate. Is to provide.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the method of manufacturing a semiconductor device according to the present invention, when forming a base metal film electrically connected to an extraction electrode which is an uppermost layer wiring on a substrate, after forming an inorganic insulating film on an upper layer of the extraction electrode, Forming a through-hole reaching the extraction electrode in the inorganic insulating film; and sputter etching the exposed surface of the extraction electrode, and continuously covering the exposed extraction electrode in a vacuum of 10 ⁻² Torr or more. The method includes a step of forming a pattern of a melting point metal film and a step of forming a pattern of a base metal film in contact with the high melting point metal film.

According to the above-described means, after forming a through hole in the inorganic insulating film, the oxide layer formed on the exposed surface of the extraction electrode is removed by sputter etching, and the extraction electrode is continuously formed in a vacuum. On the other hand, a refractory metal film having an oxidation preventing function is formed. Thus, the extraction electrode, the high-melting-point metal film, and the base metal film are sequentially connected without the interposition of the oxide layer, so that a conduction failure between the base metal film and the extraction electrode can be prevented.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) An example of a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, an inorganic insulating film 3a is deposited on the uppermost layer wiring of the substrate 1, that is, on the upper layer of the lead electrode 2 made of, for example, an Al film. Inorganic insulating film 3a
Is formed of, for example, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film or a laminated film of SiO ₂ and a Si ₃ N ₄ film, and the thickness of the inorganic insulating film 3a is, for example, 0.5.
About 3 μm.

Next, although not shown, the inorganic insulating film 3
A resist film is applied on a, and is patterned by lithography to form a resist pattern.
Next, after processing the inorganic insulating film 3a using this resist pattern as a mask, the resist pattern is removed by asher treatment, and as shown in FIG. 2, a through hole 4 is formed in the inorganic insulating film 3a. The processing of the inorganic insulating film 3a is as follows.
Dry etching, wet etching, or a combination of dry etching and wet etching is performed. Here, when the resist pattern is removed, A of about several tens nm is obtained by asher treatment using O ₃ gas.
The l ₂ O ₃ layer 5 is formed on the surface of the extraction electrode 2 exposed at the bottom of the through hole 4.

Next, after the Al ₂ O ₃ layer 5 is removed by Ar sputter etching, as shown in FIG.
A high melting point metal film 6 having a thickness of about 10 to 100 nm is formed as an upper layer. This refractory metal film 6 has an anti-oxidation function for the extraction electrode 2, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), nitride It is made of tungsten (WN). In order to prevent the surface of the extraction electrode 2 from being oxidized, the steps from the Ar sputter etching to the formation of the refractory metal film 6 are continuously performed in a vacuum of 10 ⁻² Torr or more.

Next, although not shown, a resist film is applied on the high melting point metal film 6 and is patterned by lithography to form a resist pattern. Next, after processing the refractory metal film 6 using the resist pattern as a mask, the resist pattern is removed by asher treatment, and the refractory metal film 6 is patterned as shown in FIG.

Here, since the refractory metal film 6 is for ensuring conduction between the extraction electrode 2 and a base metal film formed in a later step, the refractory metal film 6 is not necessarily required.
It is not necessary to cover all of the exposed portions, and for example, as long as it covers 50% or more of the exposed surface of the extraction electrode 2 as shown in FIG. 5 or FIG. In the patterning of the refractory metal film 6 shown in FIG. 6, the resist mask used in the processing of the through hole 4 can be used, and a new resist mask is not required.

Next, as shown in FIG.
Is coated with a photosensitive PIQ film 3b. Thereafter, as shown in FIG. 8, the PIQ film 3b is exposed and developed by lithography to
After removing the IQ film 3b, a hardening bake at about 320 to 350 ° C. is performed. As a result, the surface protection film 3 composed of the lamination of the inorganic insulating film 3a and the PIQ film 3b is formed with the refractory metal film 6 on the extraction electrode 2 exposed. Note that, in order to improve the adhesiveness of the base metal film formed in a later step, it is preferable that the opening of the PIQ film 3b is processed to be larger than the through hole 4.

Next, as shown in FIG. 9, a base metal film 7 is formed on the PIQ film 3b by, for example, a sputtering method. The base metal film 7 is constituted by, for example, three types of metal layers laminated in order from the lower layer. The lowermost metal layer is made of, for example, chromium (Cr) or Ti, and has a thickness of, for example, about 0.03 to 0.2 μm. The metal film of the intermediate layer is made of, for example, nickel (N
i) or Cu, the thickness of which is, for example, 0.3
About 3 μm. Further, the uppermost metal film is made of, for example, gold (Au) and has a thickness of, for example, 0.0.
It is about 5-0.2 μm. Note that a Ni-Cu alloy or a Ni-W alloy can be used for the metal film of the intermediate layer.

Next, although not shown, a resist film is applied on the underlying metal film 7 and is patterned by lithography to form a resist pattern. Next, using this resist pattern as a mask,
After processing the resist pattern, the resist pattern is removed by asher processing, and as shown in FIG.
For example, a BLM (Ball Limiting Metalization) film is formed.

Thereafter, although not shown, the substrate 1 is separated into semiconductor chips, and the semiconductor chips are mounted on a package substrate provided with, for example, CCB bumps.
Alternatively, after a solder is formed on the base metal film 7 by, for example, a lift-off method or a metal mask vapor deposition, the solder is spheroidized by wet back to form a CCB bump, and then the substrate 1 is separated into a semiconductor chip. The chip is mounted on a package substrate.

As described above, according to the first embodiment, after the through hole 4 is formed in the inorganic insulating film 3a, the exposed Al ₂ O ₃ layer 5 on the surface of the extraction electrode 2 is removed by Ar sputter etching. , Continuously in a vacuum, extraction electrode 2
A high melting point metal film 6 having an oxidation preventing function on the surface of the substrate is formed. As a result, the extraction electrode 2, the refractory metal layer 6, and the underlying metal film 7 are sequentially connected without the intermediary of the Al ₂ O ₃ layer 5, so that conduction between the underlying metal film 7 and the extraction electrode 2 is achieved. Failure can be prevented.

(Embodiment 2) An example of a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described in the order of steps with reference to FIGS.

First, the uppermost layer wiring, for example, A
The refractory metal film 6 is formed continuously on the l film. Next, although not shown, a resist film is applied on the high melting point metal film 6 and is patterned by lithography to form a resist pattern. Next, using the resist pattern as a mask, the refractory metal film 6 and the above A
After sequentially processing the L film, the resist pattern is removed by asher treatment, and as shown in FIG. 11, the extraction electrode 2 composed of an Al film whose surface is covered with a refractory metal film 6.
To form

Next, after depositing an inorganic insulating film 3a on the upper layer of the refractory metal film 6, although not shown,
A resist film is applied on a, and is patterned by lithography to form a resist pattern.
Next, after processing the inorganic insulating film 3a using this resist pattern as a mask, the resist pattern is removed by asher treatment, and a through hole 4 is formed in the inorganic insulating film 3a as shown in FIG. In the processing step of the inorganic insulating film 3a, the refractory metal film 6 is shaved and
The etching of the inorganic insulating film 3a is controlled so that the surface of the metal film 6 is not exposed, and the refractory metal film 6 having a thickness of about 10 to 100 nm is left on the extraction electrode 2.

Next, as shown in FIG.
A photosensitive PIQ film 3b is applied on the upper layer of a. After this,
As shown in FIG. 14, the PIQ film 3b is exposed to light and developed by a lithography technique to remove the PIQ film 3b on the through hole 4, and then subjected to a hardening bake at about 320 to 350 ° C. As a result, the surface protection film 3 composed of the lamination of the inorganic insulating film 3a and the PIQ film 3b is formed with the refractory metal film 6 on the extraction electrode 2 exposed.

Next, as shown in FIG. 15, the PIQ film 3b
The underlying metal film 7 is formed on the upper layer by, for example, a sputtering method. Next, although not shown, a resist film is applied on the underlying metal film 7 and is patterned by lithography to form a resist pattern.
Next, after processing the underlying metal film 7 using this resist pattern as a mask, the resist pattern is removed by asher processing, and a pattern of the underlying metal film 7 is formed as shown in FIG.

As described above, according to the second embodiment, the refractory metal film 6 having an antioxidant function for the extraction electrode 2 is formed on the extraction electrode 2, and the surface of the extraction electrode 2 is By preventing the exposure, the formation of an Al ₂ O ₃ layer on the surface of the extraction electrode 2 can be prevented, and poor conduction between the base metal film 7 and the extraction electrode 2 can be prevented.

Third Embodiment An example of a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 17, a trench insulating film 9 having an etching selectivity with respect to the interlayer insulating film 8 is formed on the interlayer insulating film 8 provided on the substrate 1. Next, a groove pattern 10 is formed by etching the groove insulating film 9 using the resist pattern as a mask, and thereafter, a barrier layer having a function of preventing the diffusion of Cu in the upper layer of the groove insulating film 9. 11 is deposited by a sputtering method or a CVD (Chemical Vapor Deposition) method. The barrier layer 11 is made of TiN, T
a, TaN, W, WN, etc.

Subsequently, a Cu film 12 is formed on the barrier layer 11.
Is deposited by a sputtering method. After that, the substrate 1 is subjected to a heat treatment to flow Cu atoms constituting the Cu film 12 into the groove pattern 10 by a flow phenomenon (reflow processing). This reflow treatment is performed, for example, in a hydrogen atmosphere for 4 hours.
This is performed by heating the substrate 1 to about 50 ° C.

Alternatively, a Cu film 1 is formed on the barrier layer 11.
2 is deposited by continuous film formation of a sputtering method and a subsequent electrolytic plating method. In this case, first, a Cu seed layer is formed by a sputtering method. The seed layer is provided in order to allow Cu to grow in the electroplating in order to reliably conduct electricity to the inner wall and the bottom of the groove pattern 10. Then, CuSO ₄ containing additives
By connecting the electrode to the positive electrode and connecting the substrate 1 to the negative electrode in the liquid and passing a current, Cu ions are generated by electroplating, and the Cu film 12 is grown using the seed layer as a seed. Subsequently, the substrate 1 may be subjected to a reflow process.

Thereafter, as shown in FIG.
The surface and the exposed barrier layer 11 are polished by the CMP method, and the barrier layer 11 and the C
By embedding the u film 12, the uppermost layer wiring C
The extraction electrode 2 composed of the u film 12 is formed.

Thereafter, similarly to the manufacturing method described in the first embodiment, the inorganic insulating film 3a (FIGS. 1 and 2), the refractory metal film 6 (FIGS. 3 and 4), and the PIQ film 3b ( 7 and 8) and the pattern of the underlying metal film 7 (FIGS. 9 and 10) are sequentially formed to form the semiconductor device shown in FIG.

Here, in the case of an Al film left in the air, only its surface is oxidized by about several tens of nm, whereas in the case of a Cu film left in the air, the oxidation is gradually reduced to the inside of the film. Therefore, it is necessary to cover the entire extraction electrode 2 composed of the Cu film 12 exposed at the bottom of the through hole 4 with the refractory metal film 6.

As described above, according to the third embodiment, even when the lead electrode 2 composed of the Cu film 12 is used for the uppermost wiring, the through hole 4 is formed in the inorganic insulating film 3a.
Is formed, the surface of the extraction electrode 2 is covered with the refractory metal film 6, thereby preventing oxidation of the Cu film 12 and preventing conduction failure between the underlying metal film 7 and the extraction electrode 2. .

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the base metal film electrically connected to the uppermost wiring on the substrate is formed of CCB.
Although the electrode conductor pattern to which the bump is connected was used,
An electrode conductor pattern to which bumps other than the bumps are connected may be used, and similar effects can be obtained.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, without passing through an oxide layer,
Since the underlying metal film and the extraction electrode are electrically connected, poor conduction between the underlying metal film and the extraction electrode can be prevented. As a result, poor conduction between the underlying metal film and the extraction electrode is improved, and the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to Embodiment 3 of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Leader electrode 3 Surface protective film 3a Inorganic insulating film 3b PIQ film 4 Through hole 5 Alumina layer 6 Refractory metal film 7 Base metal film 8 Interlayer insulating film 9 Groove insulating film 10 Groove pattern 11 Barrier layer 12 Copper film

Continued on the front page F-term (reference) QQ75 QQ92 QQ94 QQ98 RR04 RR06 RR22 TT02 VV07 XX09

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming an electrode conductor pattern electrically connected to an extraction electrode, which is an uppermost layer wiring on a substrate, wherein (a) an inorganic insulating film is formed on an upper layer of the extraction electrode. After forming, a step of forming a through hole reaching the extraction electrode in the inorganic insulating film;
(B) a step of forming a pattern of a high melting point metal film covering the exposed lead electrode, and (c) a step of forming the electrode conductor pattern in contact with the high melting point metal film. Device manufacturing method. 2. A method for manufacturing a semiconductor device in which an electrode conductor pattern electrically connected to an extraction electrode as an uppermost layer wiring on a substrate is provided. (A) An inorganic insulating film is formed on an upper layer of the extraction electrode. After forming, a step of forming a through hole reaching the extraction electrode in the inorganic insulating film;
(B) forming a pattern of a refractory metal film covering the exposed lead electrode; and (c) forming the electrode conductor pattern in contact with the refractory metal film. A method for manufacturing a semiconductor device, wherein a melting point metal film covers 50% or more of the surface of the exposed extraction electrode. 3. A method of manufacturing a semiconductor device for forming an electrode conductor pattern electrically connected to an extraction electrode as an uppermost layer wiring on a substrate, comprising: (a) forming an inorganic insulating film on an upper layer of the extraction electrode. After forming, a step of forming a through hole reaching the extraction electrode in the inorganic insulating film;
(B) a step of forming a pattern of a refractory metal film covering the exposed lead electrode after sputter etching the surface of the exposed lead electrode; and (c) forming the electrode conductor pattern in contact with the refractory metal film. Forming a semiconductor device. 4. A method for manufacturing a semiconductor device in which an electrode conductor pattern electrically connected to an extraction electrode as an uppermost layer wiring on a substrate is provided. (A) An inorganic insulating film is formed on an upper layer of the extraction electrode. After forming, a step of forming a through hole reaching the extraction electrode in the inorganic insulating film;
(B) forming a pattern of a high-melting-point metal film over the exposed extraction electrode after the exposed surface of the extraction electrode is sputter-etched and continuously covering the exposed extraction electrode in a vacuum of 10 ⁻² Torr or more; A) forming the electrode conductor pattern in contact with the refractory metal film. 5. A method of manufacturing a semiconductor device for forming an electrode conductor pattern electrically connected to an extraction electrode as an uppermost layer wiring on a substrate, wherein: (a) the extraction electrode and the refractory metal film are formed in a lower layer. And (b) forming an inorganic insulating film on the refractory metal film and then forming a through hole reaching the refractory metal film in the inorganic insulating film. (C) forming the electrode conductor pattern in contact with the refractory metal film.