JP2002063794A - Rom data read-out circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable data to be outputted at a high speed without causing needless power consumption. SOLUTION: A reference voltage Vref is obtained at a connection point of a third N channel MOS transistor 3 and a fifth N channel MOS transistor 5, but this connection point is to be in a connection state by a bit line 11 and a fourth N channel MOS transistor which becomes in a conduction state when a pre-charge signal has a logic value High, so that the reference voltage Vref and a potential of a bit line 11 are closed each other, it is prevented that a potential of the bit line and the reference voltage Vref are reversed during pre-charge conventionally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a circuit for reading data from a ROM known as a read-only memory, and more particularly to a circuit for improving operating characteristics.

[0002]

2. Description of the Related Art Conventionally, as a circuit of this kind, for example,
The configuration shown in FIGS. 3 and 4 is publicly known. That is, the conventional circuit will be described with reference to the same drawing. First, as a basic configuration of the conventional circuit, as shown in FIG.
, Precharge circuit 102, reference circuit 10
3 and a comparison circuit 104. Among them, the comparison current circuit 101 and the precharge circuit 102 are provided for each of the ROMs (not shown) from which data is read. The bit line 11 is connected to a memory cell. The bit line 11 is connected to one input stage of a comparison circuit 103 that outputs a so-called sense result. The output stage of the reference circuit 103 is connected to the input stage of the comparison circuit 103.

FIG. 4 shows a more specific example of a circuit configuration of a ROM data reading circuit. That is, first, the comparison current circuit 101 uses the first and second P-channel MOS transistors MP1 and MP2 and the first N-channel MOS transistor MN1 to generate the third P-channel MOS transistor MPN.
The precharge circuit 102 is configured by the channel MOS transistor MP3. Further, the reference circuit 103 is configured by the second and third N-channel MOS transistors MN2 and MN3 and the fourth P-channel MOS transistor MP4. Further, the reference voltage Vref generated by the reference circuit 103 is applied to the non-inverting input terminal of the comparison circuit 104, while the comparison circuit 104
The potential of the bit line 11 is applied to the inverting input terminal.

[0006] A read signal (read signal) is supplied to the gate of the first N-channel MOS transistor MN 1 by a fourth P-channel MOS transistor MP 4.
The signal obtained by inverting the read signal is supplied to the gate of the third P-channel MOS transistor MP3.
A signal obtained by inverting a precharge signal (a signal for charging to an intermediate potential) is applied, while the bit line 11 is connected to a memory cell (not shown).

In such a configuration, first, in the comparison current circuit 101, when the read signal becomes the logical value High, the first N-channel MOS transistor MN1 and the second P-channel MOS transistor MP2 are activated. A comparison current that is の of the maximum current is supplied to the memory cell via the bit line 11 and the bit line 11 is charged at the same time. In addition, the reference circuit 103 outputs a read signal whose logical value is High.
, The fourth P-channel MOS transistor MP4 operates to generate a reference voltage Vref set approximately at the middle between the state where the potential of the bit line 11 is the lowest and the state where the potential is the highest. I have. In addition, the third P
The channel MOS transistor MP3 is activated when the precharge signal becomes a logical value High, and charges the bit line 11. The precharge causes the voltage of the bit line 11 to become equal to the reference value V.
ref is approaching.

When data is read from the memory cell, first, the read signal and the precharge signal are set to the logical value High, whereby the comparison current circuit 1
01, the precharge circuit 102, and the reference circuit 103 are activated, and the voltage of the bit line 11 rises, and at the same time, the reference voltage Vref is generated. Next, when the precharge is completed (the precharge signal changes from the logic value High to the logic Low), the potential of the bit line 11 rises and falls according to the state of the selected memory cell (comprising an N-channel MOS transistor). It will be. For example, in the case of a so-called mask ROM, the state of a memory cell is the presence or absence of a contact,
If there is a contact, a path to ground (earth) is made and the bit line 11 is discharged, while if there is no contact, the bit line 11
It is charged by conduction of the channel MOS transistor MP2.

As described above, the potential of the bit line 11 rises and falls according to the state of the memory cell.
At 04, the reference voltage Vref is compared with the reference voltage Vref.
Data presence (1 or 0) depending on whether it is higher or lower
Is determined, and the result of the determination is output from the comparison circuit 104.

[0008]

However, in the conventional circuit described above, the reference voltage Vref is set separately from the bit line to be precharged before the start of sensing. When precharging the bit line, the potential of the bit line temporarily reaches the target potential finally when precharging the bit line due to factors such as the fact that it is in a state equivalent to the connection of a capacitive load. , The potential above or below the target potential. When the temporary potential becomes higher or lower than the final target potential with respect to the reference voltage Vref, a phenomenon occurs in which the output of the comparison circuit 104 is temporarily inverted. As a result, a circuit to which a sense output is input not only causes a disadvantage that erroneous read data is input, but also causes a disadvantage.
In particular, in a circuit configured using such a CMOS transistor, despite the demand for low power consumption, careless inversion of the output signal of the comparison circuit 104 causes an increase in power consumption. was there. Further, since there is a change in the potential of the bit line as described above, in order to obtain a correct sense output, the comparison circuit 104
Can be resolved by setting the access timing to the sense output from after the output inversion occurs.
The speed at which data is read from the ROM is reduced, and a problem arises in that it is not possible to meet the demand for higher speed.

The present invention has been made in view of the above situation, and provides a ROM data reading circuit capable of reading data at high speed without wasteful power consumption. Another object of the present invention is to provide a reliable R
An OM data read circuit is provided.

[0010]

In order to achieve the object of the present invention, a ROM data reading circuit according to the present invention comprises:
A comparison current circuit for setting a bit line connected to a memory cell to a state in which a predetermined charging voltage is applied while the read signal is in an active state; a reference circuit for generating a reference voltage; A comparison circuit that compares the reference voltage output by the circuit and outputs a result of the comparison.
A switch for connecting the output stage of the reference circuit to the bit line while the precharge signal is in an active state, comprising a precharge transistor for setting the bit line to a state in which the predetermined charging voltage is applied. It is provided.

According to another aspect of the present invention, there is provided a ROM data read circuit according to the present invention, wherein a bit line connected to a memory cell is supplied with a predetermined charge voltage while a read signal is active. A comparison current circuit, a precharge circuit for setting the bit line to a state in which the predetermined charging voltage is applied while a precharge signal is in an active state, a reference circuit for generating a reference voltage, And a comparison circuit that compares the reference voltage output by the reference circuit and outputs a result of the comparison.While the precharge signal is in an active state, the output stage of the reference circuit and the It is also preferable to provide a switch means for connecting the bit line to the bit line.

In this configuration, the output stage of the reference circuit that outputs the reference voltage is connected to the bit line and the switch means, so that the reference voltage and the voltage of the bit line are close to each other. In addition, high-speed access becomes possible, and unnecessary logical inversion of the output signal in the comparison circuit during precharge as in the conventional circuit does not occur, so that a reliable read operation can be ensured. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. The same components as those of the conventional circuit shown in FIGS. 3 and 4 are denoted by the same reference numerals. First, a basic configuration of a ROM data read circuit according to an embodiment of the present invention will be described with reference to FIG. The ROM data reading circuit S is configured by using a comparison current circuit 101, a reference circuit 103A, and a comparison circuit 104 as main components. In particular, the reference circuit 103A is a precharge circuit (not shown). ), The output stage of the reference circuit 103A and the bit line 11
2 is different from the conventional configuration. FIG. 2 shows a more specific circuit configuration. Hereinafter, the specific circuit configuration will be described with reference to FIG.

First, the comparison current circuit 101 includes a first N-channel MOS transistor ("MN" in FIG. 2).
1 ").
That is, the first N-channel MOS transistor (hereinafter referred to as “first NMOS”) 1 is configured such that the power supply voltage is applied to its drain, while the source is
One input terminal of the comparison circuit 104, that is, in the embodiment of the present invention, is connected to the non-inverting input terminal and to the bit line 11. The bit line 11 is connected to a memory cell in a ROM (not shown). And
The gate of the first NMOS 1 receives a read signal from an external circuit (not shown).

The reference circuit 103A includes second to sixth N-channel MOS transistors (in FIG. 2, "MN2", "MN3", "MN4",
"MN5" and "MN6") 2 to 6. First, a second N-channel MOS transistor (hereinafter, referred to as a “second NMOS”) 2 as a precharge transistor constitutes a precharge circuit 102, and a power supply voltage is applied to a drain thereof. , While the source is connected to the bit line 11. A precharge signal is applied to the gate of the second NMOS 2 from an external circuit (not shown).

A third N-channel MOS transistor (hereinafter referred to as "third NMOS") 3, a fifth and sixth N-channel MOS transistors (hereinafter referred to as "fifth NMOS" and "sixth NMOS", respectively) 5) 6
Are connected in series between the power supply and the ground to constitute the reference circuit 103A. That is,
While the power supply voltage is applied to the drain of the third NMOS 3, the fifth NMOS 3 is connected to the source of the third NMOS 3.
5 is connected, and the other input terminal of the comparison circuit 104, that is, in the embodiment of the present invention, an inverting input terminal and a fourth N-channel MO described later.
The source of S (hereinafter referred to as “fourth NMOS”) 4 is connected. Further, the fifth and sixth NMOSs 5, 6 are:
The drain and the gate are connected to each other to form a so-called diode connection state, and the fifth NMO
The source of S5 is connected to the drain of the sixth NMOS 6, and the source of the sixth NMOS 6 is connected to the ground.

The fourth NMOS 4 realizes the switch 12 described above. In this case, the drain is connected to the bit line so as to function as a transfer switch, while the source is as described above. As the third
Of the NMOS3, the drain of the fifth NMOS5, and the other input terminal of the comparison circuit 104 (in other words, the output terminal of the reference circuit 103A). A precharge signal is applied to the gate of the fourth NMOS 4 from an external circuit (not shown).

Next, the operation of the ROM data read circuit having the above configuration will be described. ROM not shown
When reading data from the memory, first, the read signal and the precharge signal supplied from the outside are both in the active state, that is, the logical value is changed from the logical value Low to the logical value High.
Becomes When the read signal has a logical value of High, the first NMOS 1 is in a conductive state. When the precharge signal has a logical value of High, the second NMOS 2 is in a conductive state, and the bit line 11 is in the first state. Then, the battery is charged by a power supply (not shown) via the second NMOSs 1 and 2. That is, the bit line 11 is in a state where a predetermined charging voltage (power supply voltage not shown) is applied.

At the same time, the read signal has the logical value High.
When the precharge signal has the logical value High, the third NMOS 3
S4 is in a conductive state. by this,
A reference voltage Vref is generated on the source side of the third NMOS 3, but the source of the third NMOS 3 is connected to the bit line 1.
Since 1 is connected via the fourth NMOS 4, the reference voltage Vref and the voltage of the bit line 11 are close enough that the output state of the comparison circuit 104 does not cause inversion as in the related art. . That is, when the state of the potential of the bit line 11 when the precharge signal becomes the logical value High and the bit line 11 is charged is higher than the reference voltage Vref, the potential of the bit line 11 becomes higher than the reference voltage Vref. The reference voltage Vref until the voltage does not fall below Vref
When the bit line 11 is charged, the potential of the bit line 11 becomes higher than the reference voltage Vref.
If the voltage is lower than the reference voltage Vref, the potential of the bit line 11 approaches the vicinity of not exceeding the reference voltage Vref due to charging.

When a predetermined time elapses after the precharge signal becomes the logical value High, the precharge signal becomes the logical value Low again, and the precharge ends, and at the same time, the memory cell is selected. Then, the potential of the bit line 11 in the state where the power supply voltage is applied through the first NMOS 1 which is in the conductive state by the read signal still having the logical value High is the state of the selected memory cell, that is, the mask ROM. In such a case, it will move up and down according to the presence or absence of a contact. Then, the potential of the bit line 11 and the reference voltage Vref are compared with the comparison circuit 104.
Are output, the presence or absence (1 or 0) of the data in the memory cell is output. That is, when the data of the memory cell is “1”, the potential of the bit line 11> the reference voltage Vref, and the comparison circuit 104 outputs a level signal corresponding to the logical value High, while When the data of the memory cell is “0”, the potential of the bit line 11 <the reference voltage Vref, and the comparison circuit 104 outputs a level signal corresponding to the logical value Low.

[0021]

As described above, according to the present invention,
By configuring so that the potential of the bit line can be set to a level close to the reference voltage, the access speed after the end of precharge is increased. Further, since the inversion of the potential relationship between the bit line and the reference voltage during the precharge is reliably prevented, wasteful power consumption in the comparison circuit as in the related art does not occur, thereby saving power. This has the effect of contributing to power consumption and providing a highly reliable ROM data reading circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a basic configuration example of a ROM data read circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration example of a ROM data read circuit having the configuration shown in FIG.

FIG. 3 is a configuration diagram showing a basic configuration example of a conventional ROM data reading circuit.

FIG. 4 is a circuit diagram showing a specific circuit configuration example of a ROM data read circuit having the configuration shown in FIG. 4;

[Explanation of symbols]

 101: comparison current circuit 103A: reference circuit 104: comparison circuit

Claims (3)

[Claims] 1. A comparison current circuit for setting a bit line connected to a memory cell to a state in which a predetermined charging voltage is applied while a read signal is active, a reference circuit for generating a reference voltage, and the bit line. And a comparison circuit that compares the reference voltage output from the reference circuit with a reference voltage output by the reference circuit, and outputs a comparison result.The reference circuit sets the bit line while the precharge signal is in an active state. A precharge transistor for setting a predetermined charging voltage to be applied; and a switch for connecting an output stage of the reference circuit to the bit line while the precharge signal is in an active state. Characteristic ROM data reading circuit. 2. A comparison current circuit for setting a bit line connected to a memory cell to a state where a predetermined charging voltage is applied while a read signal is in an active state, and said bit line is connected to a bit line while a precharge signal is in an active state. A precharging circuit for applying the predetermined charging voltage, a reference circuit for generating a reference voltage, a voltage of the bit line and a reference voltage output by the reference circuit, A comparison circuit that outputs a result, and a switch that connects the output stage of the reference circuit and the bit line while the precharge signal is in an active state. ROM data read circuit. 3. The ROM data read circuit according to claim 1, wherein the switch means uses a MOS transistor.