JP2002062858A - Power supply circuit, liquid crystal display device and electronic equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] VH, V3, V2, V which are drive potentials of liquid crystal
This is a power supply circuit for supplying C, -V2, -V3, VL, and the like, and aims to reduce the power consumption of the liquid crystal display device. A charge pump circuit performs a charge pump operation based on a clock generated by a latch pulse LP (a pulse-like clock including a periodically generated pulse), thereby supplying a driving potential of a liquid crystal.
The charging of the pumping capacitor and the backup capacitor is stopped during the LP pulse generation period.
A charge pump operation for alternately charging the backup capacitor with a plurality of pumping capacitors is performed based on a given clock. The pumping capacitor and the backup capacitor are charged every horizontal scanning period in driving the liquid crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply circuit, a liquid crystal display device including the power supply circuit, and an electronic apparatus including the liquid crystal display device.

[0002]

2. Description of the Related Art As a first background art, a power supply circuit used in a liquid crystal display device driven one line at a time will be described with reference to FIG. This figure is basically the same as FIG. 3 of JP-A-2-150819. Here, V0 to V5 are VD = V0−V1
= V1-V2 = V3-V4 = V4-V5. For example, when the duty is 1/240, VD is 1.6.
About V.

A voltage externally input to the liquid crystal display device has a reference potential of GND for VCC for a logic portion of a driver IC and V for generating a liquid crystal panel drive voltage.
EE. VEE is considerably higher than VCC, and is, for example, about 20 V to 25 V at a duty of 1/240. Of V0 to V5, VEE is VEE and V5 is G
ND is used as it is. The remaining V1 to V4 are VEE-
The voltage obtained by dividing the voltage between GNDs by the resistors R1 to R5 is subjected to low impedance conversion by the operational amplifiers OP1 to OP4. OP1 to OP4 operate with VEE system voltage, and
Are not directly involved in forming the panel drive voltage itself.

Hereinafter, power consumption will be described with the scanning line side represented by Y and the data line side represented by X. For example, a scanning line electrode of the panel is represented by a Y electrode, a driver IC for driving the Y electrode is represented by a Y driver, a data line electrode of the panel is represented by an X electrode, and a driver IC for driving the X electrode is represented by an X driver. The voltage applied to the unselected Y electrodes is V1 or V4. When the unselected Y electrode is at V1, the voltage applied to the X electrode is V0 or V2.
When the non-selected Y electrode is at V4, the voltage applied to the X electrode is V3 or V5.

In the case of a duty of 1/240, only one line of the Y electrode is in a selected state, while all the remaining 239 lines are in a non-selected state. Therefore, the charge / discharge current flowing between the X electrode and the selected Y electrode is considerably smaller than the charge / discharge current flowing between the X electrode and the non-selected Y electrode. That is, most of the current consumed by the liquid crystal panel itself is a charge / discharge current flowing between the X electrode and the Y electrode in a non-selected state. Therefore, here, attention is paid only to the charge / discharge current flowing between the X electrode and the unselected Y electrode.

For example, consider the case where the voltage of the X electrode changes from V0 to V2 when the voltage of the unselected Y electrode is V1. At this time, assuming that the capacitance of the liquid crystal layer between the X and Y electrodes is Cpn, when the voltage of the X electrode changes from V0 to V1, Cp
The charge of n × (V0−V1) flows out of V0 and flows into V1 (see D in FIG. 48). Next, when the voltage of the X electrode changes from V1 to V2, the charge of Cpn × (V1−V2) becomes V
It flows out of 1 and flows into V2 (see E). Where V0
Since −V1 = V1−V2, the charge flowing into V1 is equal to the charge flowing out of V1. Therefore, the flow of charge into and out of V1 is reduced to zero, resulting in Cpn
The charge of × (V0−V2) flows out of V0 and flows into V2 (see F). This charge is the operational amplifier OP
2 finally flows to GND (see G). However, this charge does not work effectively on the path that travels through OP2 to GND, and merely generates heat loss and heats OP2. If the charge / discharge current of the panel in this case is Ipn and GND = 0V, this Ipn
Is Ipn × VEE. And FIG.
As is clear from G of FIG. 5, the effective utilization rate of this Ipn is (V0−V2) / VEE. In the case of 1/240 duty, since V0-V2 is about 2 × 1.6 V and VEE is 20 V to 25 V, the effective utilization rate is 1
That is less than 6%.

As a second background art, a power supply circuit used in a liquid crystal display device driven by four lines simultaneously selected will be described. The basic concept of a driving method (MLS driving) for simultaneously selecting a plurality of Y electrodes (row electrodes) is described in Reference 1 (A GENE).
RALIZED ADDRESSING TECHNI
QUE FOR FOR RMS RESPONDINGMA
TRIX LCDS. 1988 INTERRNATI
NAL DISPLAY RESEARCH CON
F. 80-85), USP 5,262,8
81. If the response of the liquid crystal is made faster by simple one-line sequential driving, the reduction of contrast becomes a problem. However, the MLS driving can solve this problem.

When simultaneously selecting L lines (L is a positive integer of 2 or more) by MLS driving, VM and V
A total of three levels of potentials, VH and VL, with M as the midpoint potential, are required. Here, VM is used as a non-selection potential, and VH and VL are used as selection potentials. The X electrode requires a potential of (L + 1) level around VM. As L increases, the voltage width VH-HL for driving the Y electrode decreases, and conversely, a large voltage width is required for driving the X electrode.

FIG. 49 shows an example of a power supply circuit that can be considered when the four-line simultaneous selection method is used. The voltages required for driving the panel include VH and VL, which are the selection voltages for the Y electrodes,
VM is a non-selection voltage of the Y electrode, and Vx0 to Vx4 are a drive voltage of the X electrode. VM is the central potential of the voltage applied to the panel, and VH−VM = VM−V
L, Vx0-Vx1 = Vx1-Vx2 = Vx2-Vx3
= Vx3-Vx4 holds. The central potential Vx2 on the X electrode side is the same as VM. For example, 1/240
For a panel equivalent to duty, VH-VL is about 25V,
Vx0−Vx1 is about 1.6V.

The voltage externally input to the liquid crystal display device is, with GND as a reference potential (0 V), VCC for the logic section of the driver IC, and VEE (= VH-VL) for generating the liquid crystal panel drive voltage. As described above, VEE has a considerably higher voltage than VCC. In FIG. 49, VDDy and VSSy are voltages of the logic portion of the Y driver, and VCC and GND are directly connected. VDDx and VSSx are voltages of the logic section of the X driver, and assuming GND = 0 V, VDDx−VSSx
= VCC. The withstand voltage required for the X driver is Vx0-V
x4, for example, about 7 V for a panel corresponding to 1/240 duty. VH and VL have VEE and GN respectively
Use D as is. Vx0 to Vx4 and VSSX are V
A voltage obtained by dividing the voltage between EE and GND by the resistors R1 to R6 into low impedance by the operational amplifiers OP1 to OP6 is used. Further, in order to satisfy the relationship of VDDx-VSSx = VCC, the resistance values of R7 to R10 are set so that R7 = R8 and R9 = R10. OP1
OP6 operates with a VEE-based voltage, and VCC is not directly involved in forming the panel drive voltage itself.

The power consumption when the power supply circuit shown in FIG. 49 is used will be described below. The voltage applied to the Y electrode when not selected is VM, and the voltage applied to the X electrode is Vx
0 to Vx4. As in the case of the one-line sequential driving described above, most of the current consumption of the liquid crystal panel itself is a charge / discharge current flowing between the X electrode and the Y electrode in a non-selected state. The power consumption by the charge / discharge current Ipn of the panel is GN
Assuming that D = 0 V, Ipn × VEE is obtained. However,
As described above, the voltage difference between Vx0 to Vx4 and VM is V
It is considerably smaller than the voltage difference between EE and GND. Therefore, the effective utilization rate of Ipn is extremely low, and most of the path travels through the operational amplifier and goes to GND, causing only heat loss and causing the operational amplifier to generate heat.

Further, assuming that the current consumption in the logic section of the X driver is IXD, the power consumption due to this is IXD ×
IXD × VEE instead of VCC. IXD × (VE
The portion of (E-VCC) also travels in the operational amplifier and reaches the GND to simply cause a heat loss and heat the operational amplifier. Although the operating voltage width of the X driver can be reduced according to the multiple line simultaneous selection method, this advantage cannot be utilized at all in reducing power consumption in this background art.

As a third background art, a power supply circuit of a liquid crystal display device using a two-terminal type nonlinear switching element will be described. A driving method of such a liquid crystal display device is described in Japanese Patent Publication No. 5-34655, and a power supply circuit used in this case is disclosed in Japanese Patent Publication No. 5-46954.
And US Pat. No. 5,101,116.
FIG. 50 (FIG. 1 of US Pat. No. 5,101,116)
A drive voltage waveform described in A is transcribed) and FIG.
ig. The operation and configuration of this power supply circuit will be described with reference to FIG. In FIG. 50, TPy
(Y = 1, 2,..., N) is a voltage waveform for driving the Y electrode, VD2 is a positive-side selection voltage, VS2 is a negative-side selection voltage, and VM ⁺ is a non-selection voltage after selecting VD2. , VM ^- is a non-selection voltage after selecting the VS2. VD2-VS
2 is about 40 V, and VD2−VM ⁺ = VM ⁻
-VS2 holds. That is, VD2 and VS2
If the center voltage VC, VD2 and VS2 are substantially symmetrical with respect to VC, VM ⁺ and VM ^- also substantially symmetric with respect to VC.

VM ⁺ -VM ^- is considerably smaller than VD2-VS2. In the MLS drive described above, both the positive and negative selection voltages are always required. In contrast, 2
In a liquid crystal display device using a terminal type nonlinear switching element, a selection voltage required at a certain point in time is VD2 or VS2.
, And both selection voltages are not required at the same timing. FIG. 51 is an example of a circuit that focuses on this point and is devised so that the withstand voltage of the Y driver is about half of VD2−VS2. At the timing when VD2 is required, the transistor 250 is turned on and the transistor 25 is turned on.
Turn 2 off. As a result, VD (t) becomes VD2 which is higher than VM ⁺ , and VS (t) becomes VS1 which is higher than VS2 due to capacitive coupling. At the timing when VS2 is required, the transistor 252 is turned on and the transistor 250 is turned off. Thereby, VS (t)
The VM ^- than VS2 next to a low voltage, VD (t)
Becomes VD1 which is lower than VD2 due to capacitive coupling. When it is sufficient to apply either the positive voltage or the negative voltage at the same timing,
By shaking the power supply voltage applied to the driver, the withstand voltage of the Y driver can be reduced to about half of VD2−VS2. Hereinafter, the driving method in which the power supply voltage is fluctuated in this way is referred to as a fluctuating power supply method. At present, this swing power supply method is predominant in liquid crystal panels using a two-terminal type nonlinear switching element.

As described above, the swing power supply method has an advantage that the withstand voltage of the Y driver is only about half of VD2-VS2, but nevertheless, there is a disadvantage that the power consumption of the liquid crystal display device is extremely increased. . One of the causes of the increase in power consumption is that all the parasitic capacitances of the Y driver are charged / discharged with the swaying voltage width and that a short-circuit current flows in the Y driver at the swaying timing. Another cause is that the power consumption of the power supply circuit itself is large, and there is no good way to reduce the power consumption of the power supply circuit itself.

In summary, the power supply circuit having the configuration shown in FIGS. 48 and 49 has the following problems.

(1) The reactive power consumption when supplying the charge / discharge current of the panel is large.

(2) Since the current consumption in the logic section of the X driver is also supplied from the high voltage VEE, the power consumption further increases.

(3) A high voltage V as a power supply for the operational amplifier
Since EE is used, the power consumption due to the idling current of the operational amplifier that constantly flows from VEE to GND is large.

(4) As the operational amplifier used in the power supply circuit, a high-priced, low-power, high-voltage operational amplifier must be used.

Further, even in the power supply circuit / drive system having the structure shown in FIG. 51, the power consumption cannot be reduced.

An object of the present invention is to solve the above-described problems, and an object of the present invention is to provide an inexpensive power supply circuit with low power consumption, a liquid crystal display device, and electronic equipment.

[0023]

According to the present invention, there is provided a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element. Performing a charge pump operation based on a clock generated by a pulsed clock including a periodically generated pulse, and supplying any of the first to Nth potentials directly or via an adjustment unit. A charge pump circuit; and means for stopping charging of a pumping capacitor included in the charge pump circuit and charging of a backup capacitor by the pumping capacitor during a period during which the pulse of the pulsed clock is generated. I do.

According to the present invention, the charging of the pumping capacitor and the backup capacitor is stopped during the pulse generation period of the pulse-like clock, thereby preventing the charge from escaping at the transition timing. As the pulsed clock, a latch pulse or the like used for the driver IC is optimal.

The present invention also provides an input power supply voltage,
A power supply circuit for supplying first to Nth (N ≧ 4) potentials for driving a display element, performs a charge pump operation based on a given clock, and connects the first potential on the high potential side to the low potential. A charge pump circuit for supplying any of the N-th potentials on the potential side, directly or via adjustment means, and a charge pump operation for alternately charging a backup capacitor with a plurality of pumping capacitors are provided. And a charge pump circuit for supplying an I-th potential (1 <I <N) among the first to N-th potentials directly or via an adjustment unit based on a clock.

According to the present invention, since the backup capacitor is charged alternately by the plurality of pumping capacitors, the output capability of the charge pump circuit can be increased. In particular, display characteristics and the like can be effectively improved by generating the intermediate potential I, which generally requires a large amount of current to be supplied, by the charge pump circuit having a high output capability.

According to the present invention, there is provided an input power supply voltage,
A power supply circuit for supplying first to Nth (N ≧ 4) potentials for driving a display element, performing a charge pump operation based on a given clock, and performing any one of the first to Nth potentials Supply directly or via the adjusting means.
A pump circuit; and means for charging a pumping capacitor included in the charge pump circuit and charging a backup capacitor by the pumping capacitor every horizontal scanning period in driving the display element. .

According to the present invention, the charge pump operation can be completed every one horizontal period, thereby effectively preventing display unevenness and the like.

Further, the present invention is characterized in that the charge pump circuit performs a charge pump operation of alternately charging a backup capacitor by a plurality of pumping capacitors every horizontal period.

As described above, by alternately charging the backup capacitor with each of the plurality of pumping capacitors every horizontal period, it is possible to complete the charge pump operation every horizontal period.

Further, the present invention is characterized in that it includes means for stopping a given clock of the charge pump circuit.

According to the present invention, the display-off control can be performed with only a slight increase in the number of elements, and the current consumption when the display is off can be reduced to almost zero.

Further, according to the present invention, there is provided a liquid crystal display device including any one of the above power supply circuits, a liquid crystal panel including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes,
A data line driver that drives the data line electrode based on a potential supplied by the power supply circuit; and a scan line driver that drives the scan line electrode based on a potential supplied by the power supply circuit. And

According to the present invention, not only the power consumption of the power supply circuit itself but also the power consumption of the liquid crystal display device can be reduced, and a liquid crystal display device most suitable for portable electronic equipment can be provided.

Further, in the liquid crystal display device according to the present invention, the power supply circuit may be configured such that the power supply circuit includes a first high-potential-side voltage included in the input power supply voltage.
The input potential and the second input potential on the low potential side
A charge pump operation based on a means for supplying the potential as one of the potentials and a given clock, and
A charge pump circuit for supplying any one of the potentials directly or via an adjusting means, and supplying the first and second input potentials to a power supply voltage of at least one logic unit of the data line driver and the scanning line driver. It is characterized by being used as

According to the present invention, the first and second input potentials are
It is used as any one of the first to N-th potentials, and is also used as a power supply voltage of a logic portion of a data line driver or a scanning line driver. As a result, it is not necessary to separately supply a power supply voltage for a logic unit such as a data line driver, and the convenience of the user of the device can be improved.
Further, the power consumption of the device can be further reduced.

Further, according to the present invention, in the power supply circuit, the first and second power supply circuits are operated by a charge pump operation based on a given clock.
A charge pump circuit that generates a potential different from the second input potential and supplies the generated potential as any of the first to N-th potentials is provided.

According to the present invention, for example, the power supply voltage of the logic section and the Gth and Jth potentials (1 <G,
When the potential difference of J <N) is different, the charge pump circuit can adjust the potential difference to be the same. This makes it easier to use the first and second input potentials as the power supply voltage of the logic section of the driver.

Further, in the liquid crystal display device according to the present invention, the power supply circuit performs a charge pump operation based on a clock generated by a latch pulse for the data line driver or a shift clock for the scanning line driver. A charge pump circuit for supplying any one of the first to N-th potentials directly or via an adjusting unit is provided.

The latch pulse and the shift clock are pulse-like clocks including periodically generated pulses, and are most suitable for generating a clock for the charge pump circuit. Therefore, by using these, it is possible to maintain both the display quality of the liquid crystal display device and low power consumption.

According to the present invention, an input power supply voltage is given.
A power supply circuit for supplying first to N-th (N ≧ 4) potentials for driving a display element, wherein the first input potential on the high potential side included in the input power supply voltage is supplied to the first to N-th potentials. Means for supplying a G-th potential (1 <G <N) of the potentials; and a second input potential on the low potential side included in the input power supply voltage, the J-th potential of the first to N-th potentials. 1 <J <N) means for supplying as a potential; a charge pump circuit which performs a charge pump operation based on a given clock, and supplies the first potential on the high potential side directly or via an adjusting means; And a charge pump circuit that performs a charge pump operation based on a given clock and supplies the N-th potential on the low potential side directly or via an adjustment unit.

When a display element such as a liquid crystal is driven, generally, the consumption current that must be supplied by the first potential on the high potential side and the N-th potential on the low potential side is small, and the G-th potential is an intermediate potential. And the J-th potential, the amount of current that must be supplied is large. According to the present invention, the first and Nth potentials are supplied by a charge pump circuit having a low output capability but high efficiency, and the G and Jth potentials are supplied by an input power supply voltage having a high output capability. . As a result, according to the present invention, it is possible to maintain both display quality and lower power consumption, and it is possible to provide a power supply circuit optimal for a liquid crystal display device aiming for lower power consumption.

Further, according to the present invention, there is provided a charge pump that performs a charge pump operation based on a given clock by using a potential other than the first, G, J, and N-th potentials among the first to N-th potentials.
It is characterized by being supplied by a pump circuit or a given operational amplifier.

If all the potentials other than the first, Gth, Jth, and Nth potentials are supplied by the charge pump circuit, further lower power consumption can be achieved. On the other hand, even if an operational amplifier having a high output capability is used to supply these potentials, the present invention has the advantage that the operating voltage of the operational amplifier can be reduced, so that the power consumption is not significantly reduced.

Further, according to the present invention, the first to Nth potentials may be the first input potential, the second input potential, a midpoint potential of the first and second input potentials, and the first and second input potentials. It is characterized in that it is formed symmetrically with respect to either the generated potential when a potential different from the potential is generated and the midpoint potential of the first or second input potential.

That is, according to the present invention, the first to N-th potentials are
Symmetrically with respect to the first input potential, symmetrically with respect to the second input potential, symmetrically with respect to the midpoint potential of the first and second input potentials, or the generated potential and the first or second input potential Can be formed symmetrically with respect to the midpoint potential.

Further, according to the present invention, a potential different from the first and second input potentials is generated based on one of the first and second input potentials, and the generated potential is changed to one of the G-th and J-th potentials. It is characterized by doing.

For example, consider the case where the required potential difference between the Gth and Jth potentials is larger than the potential difference between the first and second input potentials. In this case, according to the present invention, for example, by generating a higher potential from the first input potential, it is possible to obtain the Gth and Jth potentials having a desired potential difference. This makes it possible to lower the logic voltage.

According to the present invention, when an input power supply voltage is applied,
A power supply circuit for supplying first to N-th (N ≧ 4) potentials for driving a display element, wherein K is set based on a given clock;
A charge pump circuit that performs a charge pump operation of double (K ≧ 2) boosting and supplies any of the first to N-th potentials directly or through an adjusting unit; M times (where L / M is not an integer) step-down or M
/ L times boosting charge pump operation,
And a charge pump circuit for supplying any of the N-th potential directly or via an adjusting means.

According to the present invention, for example, a six-fold booster circuit and one
A power supply circuit in which a / 3-fold step-down circuit is mixed can be realized. This makes it possible to supply various voltage groups required for driving the display element with low power consumption.

According to the present invention, an input power supply voltage is given,
A power supply circuit for supplying first to N-th (N ≧ 4) potentials for driving a display element, wherein K is set based on a given clock;
Double (K ≧ 2) step-up or L / M times (L / M is not an integer) step-down or M / L times step-up charge pump operation to directly or one of the first to Nth potentials It is characterized by including a charge pump circuit supplied through an adjusting means, and means for changing a boosting rate or a step-down rate of the charge pump circuit.

According to the present invention, the step-up or step-down ratio of the charge pump circuit can be changed. For example, it is possible to change a six-fold booster circuit to a five-fold booster circuit. For example, by changing the step-up ratio or the like in accordance with the characteristics of the display element and the value of the input power supply voltage, it becomes possible to form various necessary drive voltage groups. It is desirable that the step-up / step-down ratio can be changed by using an external terminal or the like.

Further, according to the present invention, when an input power supply voltage is given,
A power supply circuit for supplying a first to Nth (N ≧ 4) potentials for driving a display element, wherein the power supply circuit performs a charge pump operation based on a given clock, and the first potential or the low potential on the high potential side. A charge pump circuit for supplying the N-th potential on the potential side directly or via an adjusting unit; and a first period or the first potential by the charge pump circuit for a given period after the input power supply voltage is turned on. Means for stopping the supply of the N potential.

According to the present invention, after the input power supply voltage is turned on,
After a given period has elapsed and the control circuit or the like operates normally, supply of the first or Nth potential can be started. This allows the system to start up normally.

According to the present invention, an input power supply voltage is given,
A power supply circuit for supplying first to N-th (N ≧ 4) potentials for driving a display element, wherein the first input potential on the high potential side included in the input power supply voltage is supplied to the first to N-th potentials. Means for supplying a G-th potential (1 <G <N) of the potentials; and a second input potential on the low potential side included in the input power supply voltage, the J-th potential of the first to N-th potentials. 1 <J <N) means for supplying the potential as the potential;
Means for supplying a third input potential higher or lower than the second input potential as one of the first potential on the high potential side and the N-th potential on the low potential side, and a given clock Performs a charge pump operation based on a charge pump circuit that supplies any one of the first and Nth potentials directly or through an adjusting unit, and performs a charge pump operation based on a given clock; A charge pump circuit for supplying an F-th potential (1 <F <N) higher or lower than the G-th and J-th potentials, directly or via an adjusting unit; A potential other than the first, F, G, J, and N-th potentials in the N-th potential is supplied by a charge pump circuit that performs a charge pump operation based on a given clock. .

According to the present invention, it is possible to supply the first to Nth potentials by a circuit and means having an output capability commensurate with the required current consumption, and to maintain both display quality and low power consumption. it can.

According to the present invention, an input power supply voltage is given,
A power supply circuit for supplying first to Nth (N ≧ 4) potentials for driving a display element, performing a charge pump operation based on a given clock, and performing any one of the first to Nth potentials Supply directly or via the adjusting means.
When at least one of a pump circuit and supply of the input power supply voltage, supply of the given clock, or input of a display-off control signal is performed, a voltage is supplied by at least one of the first and Nth potentials. Means for discharging the residual charge of the circuit portion to be performed.

According to the present invention, a situation in which a high voltage is continuously applied to the display element can be prevented, and the reliability can be improved.

Further, an electronic apparatus according to the present invention includes the above-mentioned liquid crystal display device.

According to the present invention, it is possible to reduce the power consumption of not only a liquid crystal display device but also an electronic device including the same. This makes it possible to extend the battery life of an electronic device such as a portable information device.

[0061]

Embodiments of the present invention will be described below with reference to the drawings. GN for convenience unless otherwise noted
The description will proceed with the potential of D set to 0V.

[Embodiment 1] FIG. 1 is a block diagram of a power supply circuit according to Embodiment 1. This power supply circuit has a function of generating the same output voltage as the power supply circuit of FIG.

The input power supply voltage of this power supply circuit is Vcc
(First input potential) and only GND (second input potential), and are single power supply inputs. A latch pulse LP composed of a pulse generated every horizontal scanning period is input. The clock forming circuit 1 forms several clock signals having different timings necessary for the charge pump circuit based on LP, and uses Vcc and GND as power supplies. The negative-direction six-fold booster circuit 2 generates G based on Vcc.
A voltage VEE obtained by boosting ND six times in the negative direction is generated by a charge pump operation. When Vcc is 3.3V, VE
E becomes -16.5V. The contrast adjustment circuit 3
A selection voltage VL that provides an optimum contrast is generated based on VEE. This VL becomes the negative side selection voltage of the Y electrode. 2
The double boosting circuit 4 generates a positive-side selection voltage VH, which is twice the GND with reference to VL, by a charge pump operation. The negative-direction double boosting circuit 5 generates -V3, which is a voltage obtained by double-raising GND in the negative direction with reference to Vcc, by a charge pump operation. The 1/2 step-down circuits 6 and 7
V2, which is a voltage obtained by equally dividing between cc and GND, and GND-
-V2, which is a voltage obtained by dividing (-V3) into two equal parts, is generated by the charge pump operation. GND is applied to the central potential VC.
Is used as it is. Further, Vcc is used as it is for V3 which is a potential symmetrical to −V3 with respect to GND. Thus, a voltage for driving the liquid crystal panel was formed. In this power supply circuit, the output voltages VH, V3, V2, VC, -V
2, -V3 and VL are symmetric with respect to GND (second input potential). The circuit 8 forms a voltage higher than VL by Vcc, and generates this voltage by the logic voltage VDDy of the Y driver.
It is supplied as. Since VDDy itself is not directly applied to the panel, it is not subject to voltage symmetry.

The present embodiment described above has the following structural features.

(1) In this embodiment, the first input potential Vcc on the high potential side and the second input potential GND on the low potential side included in the input power supply voltage are set to the first to Nth potentials (N ≧ 4). G in
The potential V3 and the J-th potential VC are used as they are. Further, a charge pump operation is performed based on a given clock, and the first potential VH on the high potential side and the N-th potential VL on the low potential side are performed.
Booster circuit 4, which supplies the voltage directly or via an adjusting means (contrast adjusting circuit 3), a negative direction 6-fold booster circuit 2
Contains.

As described in the background art, the current consumption of the liquid crystal panel itself is determined by the non-selection voltage VC of the Y electrode and the X
Most of the current flows between the electrode drive voltages V3, V2, -V2, and -V3. For example, when the duty is 1/240, only four lines of the Y electrode are in the selected state, while all the remaining 236 lines are in the non-selected state. This embodiment pays attention to this point, and supplies the first potential VH and the N-th potential VL by a charge pump circuit having low output capability (current supply capability) but high efficiency, and the G-th potential which is an intermediate potential. V3 and the J-th potential VC are connected to input power supply voltages Vcc and GND having high output capability. By doing so, it is possible to maintain both display quality and reduce power consumption. On the other hand, the power supply circuit in FIG. 49 has a configuration in which all the current flows between the first potential VEE and the N-th potential GND. Therefore, the circuit forming VEE must have high output capability. Therefore, it is almost impossible to supply VEE with a charge pump circuit, and it is impossible to maintain display quality and reduce power consumption at the same time.

(2) In this embodiment, the potentials V2,-other than the first, Gth, Jth, and Nth potentials among the first to Nth potentials are used.
V2 and -V3 are supplied by 降 step-down circuits 6 and 7 and a negative-direction double step-up circuit 5 that perform a charge pump operation based on a given clock. Thus, V2, -V2,-
By further supplying V3 by the charge pump circuit, further lower power consumption can be achieved. Moreover, according to the present embodiment, the clock necessary for the charge pump operation can be shared between the charge pump circuits, so that the control is easy and the increase in the circuit scale can be minimized.

FIG. 2 shows that V2 and -V2 are
The block diagram in the case of supplying by P1 and OP2 is shown.
R1 and R3 are bleeder resistors for dividing the voltage between V3 and VC (GND), and R2 and R4 are bleeder resistors for dividing the voltage between VC and -V3. OP1,
OP2 is an operational amplifier for outputting the voltage divided by the bleeder resistance at low impedance. Also R
Reference numerals 11 and R12 denote resistors for limiting the output currents of the OP1 and OP2 to stabilize the operation and reduce the power consumption, and C1 to C4 are smoothing capacitors for suppressing fluctuations of V2 and -V2. is there. OP1 operates using V3 and VC as power supplies, and OP2 operates using VC and -V3 as power supplies. C1 may be arranged between V3 and VC, and C4 may be arranged between VC and -V3. As described above, V2 and -V2 are connected to the operational amplifier O.
Even when supplied by P1 and OP2, OP1 and OP2 operate with a small power supply voltage unlike the power supply circuit of FIG. 49, so that the power consumption of this part can be suppressed within an allowable range.

(3) In the present embodiment, a charge pump operation of K-fold (K.gtoreq.2) is performed based on a given clock, and any one of the first to N-th potentials is adjusted directly or by adjusting means ( Negative direction 6 supplied via contrast adjustment circuit 3)
Double booster circuit 2, Double booster circuit 4, Negative double booster circuit 5
Performs a L / M-fold (where L / M is not an integer) step-down or M / L-times charge pump operation based on a given clock, and adjusts any of the first to Nth potentials directly or by adjusting means降 step-down circuits 6 and 7 supplied through As described above, in the present embodiment, the charge pump circuit that performs the K-fold boost and the charge pump circuit that performs the L / M-fold step-down are mixed. Thereby, a single input power supply (Vc
c, GND) can be supplied with low power consumption.

Next, FIG.
This will be described with reference to FIG. The contrast adjustment circuit 3 is connected to GND
-Fixed resistor Rfix and variable resistor Rvol inserted in series between VEE and bipolar transistor Tr
And a capacitor CVL. In the liquid crystal display device driven by the power supply circuit of the present embodiment, since the current flowing through the output voltage VL is small, the base current of the Tr can be small. As a result, Rfix and Rvol are 500KΩ ~ 1M
Ω and high resistance, the power consumption by this resistance is 0.2m
W to about 0.4 mW.

In FIG. 1, the contrast adjustment circuit 3 is connected to V
Although provided only on the L side, it may be provided only on the VH side, or provided on both the VH side and the VL side. In FIG. 1, the contrast adjusting circuit 3 is provided only on one side, and VH is generated by the double boosting circuit 4 based on the voltage VL obtained by the contrast adjusting circuit 3. This configuration has an advantage that VH can be automatically adjusted by adjusting VL by the contrast adjustment circuit 3. On the other hand, according to the configuration in which the contrast adjustment circuit 3 is provided on both sides of VH and VL,
There is an advantage that H and VL can be adjusted independently. MIM
The non-linear switching element has a characteristic that the easiness of current flow differs depending on the direction in which the voltage is applied. Therefore, in a liquid crystal display device using MIM or the like, | V
It may be preferable to lower H | by approximately 0.5 V with respect to | VL |. Therefore, in such a case, it is desirable to provide the contrast adjustment circuit on both the VH side and the VL side. Specifically, a diode or the like may be included in the contrast adjustment circuit on the VH side, and VH may be reduced using the forward voltage of the diode.

In FIG. 1, the 1/2 step-down circuits 6 and 7 are provided in order to obtain a voltage of 7 levels. However, when the desired voltage is 5 levels, the 1/2 step-down circuits 6 and 7 are omitted. do it.

According to the present embodiment having the above configuration, it is possible to reduce the power consumption of the liquid crystal display device driven by the four-line simultaneous selection method for the following reasons.

The first reason is that the power consumption due to the charge / discharge current of the panel is ultimately reduced. Consider a charge / discharge current that accounts for most of the panel current, that is, a charge / discharge current flowing between the X electrode and the unselected Y electrode.
The charge / discharge current flowing between the voltage V3, -V3, V2, -V2 of the X electrode and the voltage VC of the Y electrode are represented by IP3 and IM, respectively.
3, IP2 and IM2. Then, the power consumption by IP3 is Vcc × IP3. Further, since the charge pump circuit has extremely high efficiency, the power consumption by IM3 is also approximately Vcc × IM3, and the power consumption by IP2 and IM2 is also approximately (１ ／) × Vcc × IP2, (1/2), respectively.
× Vcc × IM2. On the other hand, in the background example of FIG.
Assuming that the high voltage is VEE, the power consumption by each of these currents is VEE × IP3, VEE × IM3, VEE × IP2,
VEE × IM2. VEE is about 25V,
Since cc is about 3.3 V, the power consumption by IP3 and IM3 is 1/7 or less of the background example, and IP2 and IM2
, The power consumption is 1/14 or less.

Next, the charge / discharge current flowing between the X electrode and the selected Y electrode will be considered. Y electrode voltage VH,
The charge / discharge current flowing between the VL and the X electrode is IVH,
IVL. Then, again, due to the high efficiency of the charge pump circuit, the power consumption by IVH and IVL is approximately 5 × Vcc × IVH and 5 × Vcc × IVL, respectively.
It becomes smaller than the power consumption of the background example.

The second reason is that the power consumption in the logic section of the X driver which operates at a high speed and consumes a large amount of current is reduced. As described above, in the power supply circuit of the background example, since the current consumption in the logic section of the X driver is supplied from the high voltage VEE, the power consumption is VEE × current consumption. On the other hand, in this embodiment, the power consumption is Vcc × current consumption, which is 1/7 or less of the background example.

The third reason is that the power consumption of the booster circuit for forming the high voltage VEE is small. Generally, a charge pump type booster circuit has a small boosting capability, and when a large current is taken out, an output voltage is reduced. In the liquid crystal display device driven by the power supply circuit of the background example, the current of the high-voltage system is large, so that the charge pump type booster circuit has insufficient capacity to form VEE. Therefore, in the background example, a switching regulator type DC-DC converter that rectifies a high voltage generated when the current flowing through the coil is intermittent and forms a high voltage VEE is used. Switching regulator type DC-DC converter has an efficiency of 5
It is about 80% for V input and about 60% for 3.3V input. Therefore, the power consumption of the liquid crystal display device driven by the power supply circuit of the background example is very large, including the step-up circuit for forming the VEE. On the other hand, the liquid crystal display device driven by the power supply circuit of this embodiment has a small high-voltage current. Therefore, the high voltage VEE can be supplied by a charge pump type booster circuit having a small output capability but high efficiency,
Power consumption including the booster circuit forming VEE can be greatly reduced.

The above is the reason why the power supply circuit of this embodiment can reduce the power consumption of the liquid crystal display device. When a liquid crystal display device driven by two screens having 640 × 480 dots and a dot pitch of 0.2 mm was actually driven by the power supply circuit of the system shown in FIG. 1, the typical power consumption was about 12 mW as expected. Value.

In the case where the power supply circuit of this embodiment is integrated into an IC, the VL can be formed by incorporating an operational amplifier type regulator in the IC instead of using the above-mentioned externally mounted circuit using bipolar transistors. . Further, in order to lower the withstand voltage of the IC, a second voltage for forming the VH is required.
It is also a practical means to externally connect a transistor for switching VH-GND among the elements constituting the double booster circuit 4, and to integrate the other elements into one chip.

In the power supply circuit of this embodiment, most of the structure is formed by the charge pump circuit, so that an impression that many capacitors are required is given. However, in practice, it is possible to omit a part of the backup capacitor included in the charge pump circuit or to use only a small capacitance value of about 0.1 μF. This is probably because the capacity of the liquid crystal panel itself acts as a backup capacitor.

[Embodiment 2] Embodiment 2 is an embodiment relating to the clock forming circuit 1 of FIG. 1. FIG. 4 shows an example of its configuration, and FIG. 5 shows a timing chart for explaining its operation. This entire circuit operates on the Vcc-GND system. In addition, as a basic clock signal, a horizontal scanning period (1
H) A latch pulse LP including a pulse generated every time is used. The D-type flip-flop DF has a / Q output connected to the write data input D, thereby providing an L-type flip-flop.
A toggle operation is performed at the rising edge of P. NOR circuit N
or1 and Nor2 are for forming two-phase clock signals A and B, and have inverter circuits Inv1 and Inv.
v2 and Inv3 are for forming signals / A, / B and Doff having phases opposite to those of A, B and / Doff, respectively.

(1) Pulse-like clock In this embodiment, a periodically generated pulse (P1 in FIG. 5,
A charge pump circuit (such as the negative-direction six-fold booster circuit 2 in FIG. 1) performs a charge pump operation based on a clock generated by the pulse-like clock LP including P2. The charging of the pumping capacitor included in the charge pump circuit and the charging of the backup capacitor by the pumping capacitor are stopped during the pulse generation period of the pulse clock LP. That is, as shown by Tp in FIG. 5, during the period during which the pulse of LP is generated (the period when LP is at the high level), both the signal A and the signal B are set to the low level. When the signals A and B become low level, all the switches (transistors) forming the charge pump circuit are turned off, thereby preventing the charge from escaping at the transition timing.

However, if the off time of the switch group at this transition timing is too long (the period of Tp is too long),
Conversely, the time required to charge the pumping capacitor and the backup capacitor is reduced, so that the required voltage cannot be obtained. LP has a pulse width of usually 100 ns to 300 ns.
Since this is a pulsed clock having a period of about ns and a period of about several tens μs to 100 μs, it is convenient as a basic clock of this circuit. In addition, the charge / discharge of the panel is performed by one horizontal scan (1
H) Since it occurs in a cycle, it is reasonable to charge the panel drive voltage in a 1H cycle using LP. Although it is possible to generate a basic clock internally with a CR oscillation circuit or the like without inputting LP, it is simpler to use the latch pulse input to the driver IC as the basic clock for this power supply circuit. preferable.

The pulse clock used in this embodiment is not limited to LP which is a latch pulse for an X driver,
For example, a shift clock YSCL for the Y driver may be used. If a pulsed clock is not used,
The period Tp for turning off the switch group may be created using a delay circuit or the like.

(2) Clock Stop Function In this embodiment, while the display-off control signal / Doff is at the low level, both the signal A and the signal B are set to the low level so that the operation of the charge pump circuit is stopped. I have.
That is, the power supply circuit has a function of stopping the clock supplied to the charge pump circuit. By adding this function, the power consumption of the power supply circuit during the display-off control can be reduced to almost zero. In addition, since the output of the selection voltage is stopped at the same time, even if the Y driver does not have the display off control function, the entire liquid crystal display device can have the display off control function. In the example shown in FIG.
In consideration of testability at the time of C conversion, the generation of the clock is stopped by resetting the DF, and the operation of the charge pump circuit is stopped. However, L
It is also possible to stop the operation of the charge pump circuit by using a method of inputting P and / Doff to a given AND circuit and using the obtained signal as a new basic clock.

[Embodiment 3] In Embodiment 3, the negative direction 6 shown in FIG.
This is an embodiment relating to a charge pump circuit such as a double booster circuit 2, a double booster circuit 4, and the like.

(1) Basic Concept FIG. 6 is the most basic conceptual diagram of the charge pump circuit. In FIG. 6, SWa and SWb are interlocking switches, and one of them is also falling to the A side while the other is falling to the A side. In FIG. 6, SWa and SWb are represented by mechanical switches. However, actually, the switches SWa and SWb control a MOS transistor for controlling conduction and interruption to the A side and a conduction and interruption to the B side. Usually, it can be constituted by two MOS transistors.

While SWa and SWb are switched to the A side, the pumping capacitor Cp is charged with the voltage of Vb-Va. Next, when SWa and SWb are switched to the B side, the charge charged in Cp is transferred to the backup capacitor Cb. By repeating this switching operation, the voltage applied to Cb, that is, Ve
The voltage between -Vd approaches a value substantially equal to the voltage between Vb-Va. At this time, if Vd is a fixed voltage, a voltage higher than Vd by Vb-Va is generated in Ve. Conversely, if Ve is a fixed voltage, Ve
A voltage lower than e by Vb-Va is generated at Vd. The above is the basic operation of the charge pump circuit. As described below, depending on where Va, Vb, Vd, and Ve are connected, this circuit functions as a booster circuit or a step-down circuit.

(2) Double boosting FIG. 7 is a diagram in which Vd is connected to Vb in FIG.
It is a conceptual diagram of a double boosting charge pump circuit. That is, for the above-mentioned reason, Ve−Vd = Ve−Vb =
Ve−Va = (Ve−Vb) +
(Vb−Va) = 2 × (Vb−Va) holds. That is, when Va is set to the reference level (0 V) of the potential, Ve =
2 × Vb, and Ve is a voltage obtained by boosting Vb twice.

(3) Negative Double Boost FIG. 8 is a conceptual diagram of a negative double boost charge pump circuit in which Ve is connected to Va in FIG.
Since SWa and SWb repeat the interlocking switching operation, Ve−Vd = Va−Vd = Vb−Va.
b−Vd = (Vb−Va) + (Va−Vd) = 2 × (V
b-Va) holds. That is, when Vb is set to the reference level (0 V) of the potential, Vd = 2 × Va, and Vd is Va
Is doubled in the negative direction.

(4) 1/2 step-down FIG. 9 shows that the input voltage is changed from Vb-Va to Vb-
Vd, which is a conceptual diagram of a 降 step-down charge pump circuit. Ve is the output voltage, and Ve
Is supplied from the backup capacitor Cb. First, when SWa and SWb are conducting with the B side, Cp and Cb are connected in parallel, and the voltages applied to Cp and Cb are equal. Next, when SWa and SWb are switched to the A side, the series-connected Cp and Cb fall between the input voltages Vb and Vd, and the voltage applied to Cp and Cb becomes half of the input voltage.
Next, when SWa and SWb switch to the B side again, Cp
And Cb are connected in parallel, the charge stored in Cp is supplied to Cb, and the voltage applied to Cp and the voltage applied to Cb become equal. Therefore, if the electric charge that can be stored in Cp and Cb is sufficiently larger than the electric charge carried away by the load current of Ve, SWa and SWb repeat the interlocking switching operation, so that Ve becomes 1 / the input voltage. An output voltage close to 2 will be generated.

(5) Negative Direction Sixfold Boost FIG. 10 is a conceptual diagram showing an example of a negative direction sixfold boosting charge pump circuit, and FIGS. 11 (A) and 11 (B).
Are SWa1 to SWa3 and SWb1 to SWb3, respectively.
FIG. 7 is a connection relation diagram when the switch is switched to the A side and the B side. SWa1 to SWa3 and SWb1 to SWb3 are interlock switches, Cp1 to Cp3 are pumping capacitors, and Cb1 and Cb23 are backup capacitors.

By the same operation as the above-described double boosting circuit in the negative direction, -V3B is a voltage obtained by boosting GND twice in the negative direction with respect to Vcc, -2 × (Vcc-GND).
Occurs. When all the switches are switched to the A side, as shown in FIG. 11A, Cp2 and Cp3 are connected in parallel, so that Cp2 and Cp3 are approximately 2 ×
It will be charged with the voltage of (Vcc-GND).

Next, when all the switches are switched to the B side, as shown in FIG. 11B, Cp2 and Cp2 connected in series are connected.
3 is connected in parallel to Cb23. Cp2 and Cp3 are
As described above, the battery is charged at 2 × (Vcc−GND). Therefore, 4 × (Vcc−G) is applied between −V3B and VEE.
ND), and Cb23 is charged with this voltage. For the above reasons, all switches repeat the interlocking switching operation, so that VEE has GN based on Vcc.
A voltage obtained by boosting D six times in the negative direction, that is, Vcc−6 × (V
cc-GND). For example, when Vcc = 3V, a voltage of -3V is generated at -V3B and a voltage of -15V is generated at VEE.

FIG. 12 is a conceptual diagram showing another example of the charge pump circuit for boosting the negative direction six times.
FIG. 13B shows SWa1 to SWa3 and SWb, respectively.
1 is a connection relation diagram when SWb23 is switched to A side and B side. Cp1 to Cp3 are pumping capacitors, and Cb1 to Cb3 are backup capacitors.

As in the circuit of FIG. 10, -V3B includes V
A voltage of −2 × (Vcc−GND), which is a voltage that is twice as high as GND with respect to cc, is generated. All switches are A
When switching to the side, as shown in FIG. 13A, Cp2 is charged with a voltage of approximately 2 × (Vcc-GND). Further, as shown in FIG. 12, Cp2, Cb2, S
The circuit composed of Wb23 and SWa2 is Cp1, Cb1,
Like the circuit composed of SWb1 and SWa1, it is a negative direction double boosting circuit. Therefore, Cb2 is also 2 × (Vcc
−GND), and VEM has −4 × (V
(cc-GND). This allows Cp3
Is charged at a voltage of 4 × (Vcc−GND).

Next, when all the switches are switched to the B side, as shown in FIG. 13 (B), C is set between -V3B and VEE.
The connection relationship is such that P3 is inserted. The voltage of -V3B is-
2 × (Vcc−GND), and Cp3 is 4 × (Vcc−GND).
−GND). Therefore, VEE eventually generates a voltage obtained by boosting GND six times in the negative direction based on Vcc, that is, a voltage of Vcc−6 × (Vcc−GND).

The circuit of FIG. 10 differs from the circuit of FIG.
Since VEM which is a stable voltage between V3B and VEE is not required, there is an advantage that the number of capacitors required is one less than that of the circuit of FIG. On the other hand, FIG.
Since the circuit of No. 2 shares a switch connected to the + electrodes of Cp2 and Cp3, there is an advantage that the number of switches required is one less (two as the number of transistors) than the circuit of FIG. Further, by forming the intermediate voltage VEM, there is an advantage that the drain withstand voltage of the transistor may be lower than that of the circuit of FIG. 10 and the size of the transistor can be reduced.

(6) 3/2 boosting FIGS. 14A and 14B are conceptual diagrams of a 3/2 boosting charge pump circuit. CpH and CpL are pumping capacitors, and Cb is a backup capacitor. As shown in FIGS. 14A and 14B, in this circuit, a state where CpH, CpL and Cb are connected in series and a state where Cb, CpH and CpL are connected in parallel are alternated. Is repeated. CpH, Cp
When the voltages applied to L are expressed as VcpH and VcpL, respectively, since CpH and CpL are connected in parallel in FIG. 14B, VcpH = VcpL. FIG.
When CpH and CpL are connected in series between Vcc and GND as shown in (A), CpH and CpL have 1 / Vcc of Vcc.
2 is charged. Thereafter, when the connection state shown in FIG. 14B is reached, the charges stored in CpH and CpL are supplied to Cb. By repeating this operation many times, the voltages applied to Cb, CpH, and CpL each approach 1/2 of Vcc, and as a result, the output voltage becomes Vc.
A voltage is generated by boosting c by 3/2 times.

(7) Negative 3 / 2-times Boosting FIGS. 15A and 15B are conceptual diagrams of a negative-direction 3 / 2-fold boosting charge pump circuit. The principle of operation is the same as that of the above-mentioned 3/2 boosting, so that detailed description is omitted. As in the case of 3/2 boosting, the pumping capacitors CpH and CpL are connected to the backup capacitor Cb.
15A in which Cb, CpH and CpL are connected in parallel alternately with the state shown in FIG. And a boosted voltage −3 × Vcc in the opposite direction. A driver IC of a liquid crystal display device often requires a logic voltage and a voltage on the negative side of the logic voltage. By applying this circuit to such a liquid crystal display device, the low voltage of the liquid crystal display device can be reduced. Power consumption can be reduced.

(8) 2/3 Step-Down FIG. 16A and FIG. 16B are conceptual diagrams of a 2/3 step-down charge pump circuit. Also in this circuit,
FIG. 16 with pumping capacitors CpH and CpL connected in series with backup capacitor Cb
The state of FIG. 16A and the state of FIG. 16B in which Cb, CpH, and CpL are connected in parallel are alternately repeated. C
b, CpH, and the voltage applied to CpL are shown in FIG.
16 are all the same because they are connected in parallel.
When connected in series as shown in (A), Cb, CpH and C
Each of pL is charged with a voltage substantially equal to 1/3 of Vcc. By repeating this operation many times, Cb, Cp
Each of the voltages applied to H and CpL is about 1 / Vcc.
3 and as a result, the output is (（) less than Vcc.
A voltage lower by × Vcc, that is, a voltage obtained by stepping down Vcc by 2/3 times, is generated.

(9) Negative 2/3 Step Down FIG. 17A and FIG. 17B are conceptual diagrams of a negative 2/3 step down charge pump circuit. The operation principle is the same as that of the above-mentioned 2/3 step-down, so that the detailed description is omitted. As in the case of 2/3 step-down, the state of FIG. 17A in which CpH and CpL are connected in series with the backup capacitor Cb, and the state of FIG. 17A in which Cb, CpH, and CpL are connected in parallel By alternately repeating the state of B), it is possible to obtain a step-down voltage − ／ × Vcc in a direction opposite to the case of the step-down by 2/3.

(10) Specific Example of Charge Pump Circuit FIG. 18 shows a case where the basic part of the negative-direction double boosting charge pump circuit shown in FIG. 8 is made up of individual components (when it is made up of discrete components). Here is an example. It is assumed that Vx is an input voltage, Vy is an output voltage, and Vx> 0. At timing T1 (see FIG. 19), Trp1 of the PMOS transistor
And Trp2 are turned on, and the pumping capacitor Cp is
It is charged with the voltage of x-GND. At this time, Trn1 and Trn2 of the N-MOS transistor are off. At the next timing T2, Trp1 and Trp2 are turned off and Trn1 and Trn2 are turned on to transfer the charge charged in the pumping capacitor Cp to the backup capacitor Cb. If the source electrode of Trn1 is connected to GND as shown in FIG.
2 is alternately repeated, so that the output Vy has G
A voltage symmetric with Vx is generated with respect to ND.

In FIG. 18, the signals / A1, / A2, B and B2 entering the gates of the transistors are, for example, phase and voltage signals as shown in FIG. If the levels of these signals are not between VC and GND, a means for level shifting the signals is required. A simple level shift method using individual components is a method using a coupling capacitor Cs and a diode D as shown in FIGS. 20 (A) and 20 (B). The capacitance of the coupling capacitor Cs may be about 470 pF. By the connection of FIG. 20A, the signal / A has the same phase and the same amplitude
A gate signal that can turn on / off the S transistor Trp /
Ax can be obtained. 20B, a gate signal Bx which has the same phase and the same amplitude as the signal B and can turn on / off the NMOS transistor Trn can be obtained. Rp is a resistance of several MΩ, and functions to compensate for the leakage current of the diode and stabilize the voltage of the gate signal.

The case where the charge pump circuit is formed by using the individual components has been described above. On the other hand, when the charge pump circuit is formed into a monolithic IC, a well-known structure and means more suitable for forming a monolithic IC may be adopted as the transistor configuration and the level shift means of the charge pump circuit.

(11) Charge Pump Circuit Using Diode FIG. 21 shows a configuration example of a charge pump circuit in the case where diodes D1 and D2 are used instead of transistors as switching elements. V1 is a stable input voltage, and Vx is a clock having an amplitude voltage of Vp and a high driving capability. According to this circuit, if the forward voltage of the diode is about 0.6 V, the output voltage V2 = V1− (clock amplitude voltage Vp−about 0.6V) can be efficiently generated.

Next, the operation will be described with reference to the timing chart of FIG. For the sake of simplicity, the forward voltages of the diodes D1 and D2 are set to 0V. Period T
In c, Vx = Va, and Vd = V1 because D1 is a forward bias. Therefore, the capacitor Cp is charged with the voltage of V1-Va. In the period Td, the level of Vd is pulled by Cp and decreases by Vp which is a voltage drop of Vx. As a result, current flows through the route of V1, Cb, D2, Cp, and Vx, and Cb is charged. By repeating the above operations in the periods Tc and Td, the output voltage V2 = V1−Vp can be obtained.

As shown in FIG. 23, when the circuit of FIG. 21 is stacked in two stages, V1-2 × (Vp−about 0.
6V). Similarly, if three stages are stacked, a voltage of V1-3 × (Vp-about 0.6 V) can be obtained.

As described above, as the charge pump circuit of the present invention, not only a circuit using a transistor or the like but also various circuits such as a circuit using a diode can be adopted.

[Fourth Embodiment] The fourth embodiment relates to a technique for increasing the output capability (current supply capability) of the charge pump circuit. Basically, the output capability can be increased by lowering the on-resistance of the transistor forming the charge pump circuit and increasing the capacitance value of the capacitor. However, there are cases where other methods are more efficient. As one of the methods, a method of preparing a plurality of pumping capacitors and alternately charging the backup capacitor with the plurality of pumping capacitors is considered.
As another method, it is also possible to add a circuit for doubling the frequency of the LP and perform a charging operation and a pumping operation every half cycle of the LP. For example, in FIG.
V3 is a current consumed by a circuit portion connected to -V3,
The voltage consumed by the circuit portion connected to -V2 causes a double voltage drop. Therefore, it is desirable to increase the output capability of the charge pump circuit that supplies -V3 by the above-described various methods.

FIG. 24 shows a circuit example in which a plurality of pumping capacitors Cp1 and Cp2 are provided to increase the output capability. Here, similarly to FIG. 18, an example in which a circuit is configured by individual components is shown.

Signals A, / A, B, and / B are signals formed by the clock forming circuit described with reference to FIG. 4, and Vx is an input voltage. The period in which A is at a high level is defined as T1, B
Is a high level period T2. The period of T1 is T
rn1, Trn2, Trp3, and Trp4 are off, and Trp1 and Trp2 are on. This gives C
p1 is charged with the voltage Vx. Also, Trn3 and Trn4
Is also turned on, the charge previously charged in Cp2 moves to Cb. Next, in the period of T2, Trp1, Trp
p2, Trn3, and Trn4 are off, and Trp3 and Trp4 are on. As a result, Cp2 becomes the voltage Vx
Will be charged. Since Trn1 and Trn2 are also turned on, the charge previously charged in Cp1 moves to Cb. Thus, the two charge pump capacitors Cp
By supplying charges to Cb alternately at 1, Cp2,
A charge pump circuit with better output voltage smoothness and higher output capability can be realized.

Note that the portion indicated by H in FIG.
Level shift means for forming a signal having a voltage and a phase necessary for driving the gates of the transistors Trp4, Trn2 and Trn4 from the signals A and / B.
Cs1 and Cs2 are coupling capacitors having a capacitance of about 470 pF, D1 and D2 are diodes, and Inv3 to 6
Is an inverter, and Rf1 and Rf2 are resistors of about 1 KΩ. Inv3, Inv4 and Rf1 form one hold circuit, and Inv5, Inv6 and Rf2 form another hold circuit. If the connection as shown in FIG. 24 is made and the positive power supply terminals of Inv3 to Inv6 are connected to GND, the negative power supply terminals of Inv3 to Inv6 are Vx rather than GND
As a result, a signal having the same amplitude as that of the signal A or the signal / B and having the same or opposite phase is obtained from the outputs of Inv3 to Inv6. It is preferable to insert a smoothing capacitor Cx of about 0.1 μF between the power terminals of Inv3 to Inv6. This level shift means has an advantage that the decrease in the amplitude of the signal is smaller than that of the level shift means described with reference to FIGS. 20A and 20B.

In this embodiment, a plurality of pumping capacitors are prepared in order to improve the output capability. However, this method is also effective for improving the display quality. For example, according to the method using the latch pulse LP, FIG.
As shown in (A), charging of the pump capacitor Cp (charging operation) and charging of the back-up capacitor Cb by the Cp (pump operation) take two horizontal scanning periods (2).
H). When the charge pump circuit having such a configuration is used, for example, in the negative-direction double booster circuit 5 in FIG. 1, there is a possibility that display irregularities (4 dark lines + 4 light lines) of horizontal stripes having a cycle of 8 lines may occur. The negative direction double boosting circuit 5 supplies a current consumed by both -V2 and -V3, and -V2 and -V3 supply VH,
This is because the consumed current is larger than VL. Therefore, if the negative direction double boosting circuit 5 is configured to have a plurality of pumping capacitors as shown in FIG. 24, the above-described display unevenness can be effectively prevented. The reason for this is that, as shown in FIG.
This is because the charging of Cp1 or Cp2 and the charging of Cb by Cp2 or the charging of Cb by Cp1 are performed every horizontal period.

In order to prevent the occurrence of display unevenness as described above, at least charging of the pumping capacitor and charging of the backup capacitor by the pumping capacitor may be performed every horizontal period. Therefore,
For example, if a charge pump operation is performed as shown in FIG. 25C using a signal having a frequency twice the frequency of the latch pulse LP, the display unevenness can be prevented.

[Embodiment 5] Embodiment 5 is an embodiment relating to the change of the step-up ratio and the step-down ratio of the charge pump circuit. In the negative direction six-fold booster circuit described with reference to FIGS. 10 and 12, the boost ratio is fixed to six times. The reason for increasing the boosting factor to six is that, in a liquid crystal display device with a duty of 1/240, when Vcc drops to 3 V, VEE is insufficient at a negative boosting voltage of 5 times (that is, VEE = -12 V), and- This is because about 13.5 V is required. The VEE required for the same liquid crystal display device is about -12 V when Vcc is 3.3 V and about -10.5 V when Vcc is 3.6 V. The reason why the required VEE differs depending on the voltage of Vcc is as follows. That is, in this embodiment, the voltage for driving the X electrode is Vcc or a half thereof.
The step-down voltage is used as it is. Therefore, as Vcc increases, the effective voltage applied to the liquid crystal during the non-selection period increases,
It is necessary to reduce the selection voltage accordingly. Conversely, Vcc
Is lower, the effective voltage applied to the liquid crystal during the non-selection period is also lower, and accordingly, the selection voltage needs to be increased. For the above reasons, the negative direction six-fold booster circuit 2 shown in FIG.
When Vcc is higher than 3.3 V, the boosting factor is sufficient to be 5 times instead of 6 times. Rather, when Vcc is high, power consumption is reduced by automatically switching to 5 times. preferable. In a liquid crystal display device with a duty ratio of 1/200, a five-fold boost in the negative direction is sufficient even when Vcc drops to 3V. For this reason, 5
It is preferable to be able to switch from double to six times and from six to five times.

The change of the step-up ratio and the step-down ratio can be realized as follows. For example, in the circuit shown in FIG. 10 described above, a configuration as shown in FIG. That is, the magnification changing circuit 20 is provided, and the contact A of SWa2 may be connected to -V3B in the case of boosting by six times, and the contact A of SWa2 may be connected to GND in the case of boosting by five times.
Alternatively, a magnification changing circuit 22 may be provided, and the contact B of SWb2 may be connected to -V3B in the case of a 6-fold boost, and the contact B of SWb2 may be connected to GND in the case of a 5-fold boost. On the other hand, in the circuit shown in FIG. 12 described above, a configuration as shown in FIG. That is, a magnification changing circuit 24 is provided, and in the case of a 6-fold boost in the negative direction,
The contact A of SWa2 may be connected to -V3B, and the contact A of SWa2 may be connected to GND in the case of a five-fold boost in the negative direction.

In order to change the 3/2 boosting to the 2/3 boosting, the following may be performed. That is, FIG. 14 (A), FIG.
In the 3 / 2-fold booster circuit shown in FIG. 4 (B), the output terminal is connected to the + terminal of Cb, and Vcc is connected to the − terminal, as shown in FIGS. 16 (A) and 16 (B). And Cb +
Switching means for connecting the terminal to Vcc and the-terminal to the output terminal may be provided.

As described above, according to this embodiment, K times (K ≧ K)
2) A charge pump circuit which performs a charge pump operation of step-up or L / M times (L / M is not an integer) step-down or M / L times step-up, and changes a step-up ratio or step-down ratio of this charge pump circuit Means are provided. Thus, for example, the current wastefully consumed by the contrast adjustment circuit 3 of FIG. 1 and the like can be reduced, and the power consumption can be further reduced.

In the negative-direction six-fold booster circuit shown in FIGS. 10 and 12, -V3B is formed.
This corresponds to a voltage that is twice as high as GND with respect to Vcc. On the other hand, the output voltage -V3 of the negative-direction double booster circuit 5 in FIG. 1 also corresponds to a voltage obtained by double-raising GND in the negative direction based on Vcc. Therefore, for example, FIGS.
, The circuit including SWb1, SWa1, Cp1, and Cp2 is not provided, and the output voltage −V
3 can be shared as -V3B in FIGS. Alternatively, on the contrary, it is possible to share -V3B of the negative direction six-fold booster circuit 2 as -V3 without providing the negative-direction double booster circuit 5. However, since the output voltage is greatly reduced by the load current in the case of sharing, it is preferable to selectively use whether or not to share depending on the panel size.

[Embodiment 6] Embodiment 6 is an embodiment in which means for stopping the supply of high voltage by the charge pump circuit for a given period after the input power supply voltage is applied is provided.

When a high voltage (the first potential VH and the Nth potential VL in FIG. 1) is generated using the charge pump circuit, the generation of the high voltage is stopped for a given period after the input power supply voltage is turned on. Otherwise, the system may not start up properly. One of the reasons is that if the logic portion of the driver IC (data line driver, scanning line driver) does not operate normally before the high voltage is generated, the output circuit and the like inside the driver IC will be in a short circuit state. This is because there are cases. In order to prevent such a situation, for example, a supply stop circuit 26 is provided in the negative direction six-fold booster circuit 2 in FIG. 1 as shown in FIG. Then, the connection between -V3Bin and -V3Bout may be cut off for a given period after the input power supply voltage is turned on. FIG. 28B shows the supply stop circuit 26.
An example of a specific configuration of the above will be described. After Vcc is input, C
For a given period determined by the time constant of × R, Tr is turned off, and −V
3Bin and -V3Bout are cut off. Further, a path that uses the input power supply voltage as it is as the output voltage of the power supply circuit, that is, a path between Vcc and V3 in FIG.
It is desirable to insert a resistance of about 10Ω in the path between VCs for overcurrent prevention.

In the configuration of FIG. 1, VL (Nth potential) is supplied by the supply stop circuit 26 provided in the negative direction six-fold booster circuit 2.
Is stopped, the supply of VH (first potential) is also stopped. Therefore, it is not necessary to provide a supply stop circuit in the double boosting circuit 4. On the other hand, for example, Vcc based on GND
When supplying VH using a circuit that boosts the voltage by 6 times,
A supply stop circuit may be provided in the six-fold booster circuit.

[Embodiment 7] FIG. 29 is a block diagram of a power supply circuit according to Embodiment 7. This power supply circuit has a function of generating a voltage in which the output voltage of the power supply circuit of the first embodiment shown in FIG. 1 is entirely shifted to the higher potential side by Vcc-GND. FIG.
In the first embodiment, the first to Nth potentials are formed symmetrically with respect to the second input potential GND on the low potential side.
Are formed symmetrically with respect to the first input potential Vcc on the high potential side.

For the sake of simplicity, only the parts different from the first embodiment will be mainly described. The negative-direction quintuple booster circuit 32 outputs V
Voltage VEE obtained by boosting GND five times in the negative direction based on cc
Is generated by the charge pump operation. Vcc is 3.
At 3V, VEE goes to -13.2V. The double boosting circuit 34 generates a voltage VH obtained by boosting Vcc twice with reference to VL. The double boosting circuit 35 generates Vcc based on GND.
Is generated twice as much as the voltage V3. The 1/2 voltage step-down circuits 36 and 37 are V2, which is a voltage obtained by equally dividing V3-Vcc, and -V2, which is a voltage obtained by equally dividing Vcc-GND.
Occurs. Thus, a voltage for driving the liquid crystal panel was formed. Note that Vcc is used as it is for the central potential VC,
GND is used as it is for -V3. This power supply circuit
The level of the output voltage is the input power supply voltage Vc on the high potential side.
It has the feature of being symmetric with respect to c. According to the power supply circuit having such a configuration, the power consumption of the liquid crystal display device driven by the four-line simultaneous selection method can be reduced for the same reason as described in the first embodiment.

As described above, when the output voltage necessary for driving the liquid crystal has the center potential and most of the current consumption flows between the center potential and another voltage, the center potential is changed to the first and second input voltages. By using a configuration in which the output voltage is formed by a circuit mainly including a charge pump circuit,
The power consumption of the liquid crystal display device can be reduced. According to such a configuration, current consumption at the high voltages VH and VL is reduced, so that these high voltages VH and VL can be easily formed by a charge pump circuit having a low output capability. By forming these high voltages with a charge pump circuit having small power loss, the power consumption of the liquid crystal display device can be further reduced.

In the seventh embodiment, the negative-direction quintuple boosting circuit is changed to a positive-direction boosting circuit, and VH is boosted twice in the negative direction after VH is formed by the contrast adjusting circuit.
It is also possible to form L.

[Eighth Embodiment] FIG. 30 is a block diagram of a power supply circuit according to an eighth embodiment. This power supply circuit has a function of generating a voltage in which the output voltage of the power supply circuit according to the first embodiment is entirely shifted to a high potential side by ×× (Vcc-GND). In the eighth embodiment, the first to N-th potentials are formed symmetrically with respect to the midpoint potential of the first input potential Vcc and the second input potential GND.

The 降 step-down circuit 46 is a circuit for generating a voltage VC obtained by equally dividing the voltage between Vcc and GND into two by a charge pump operation, and this VC becomes the central potential of the first to Nth potentials. The negative direction quintuple boosting circuit 42 generates a voltage VEE obtained by boosting GND five times in the negative direction with reference to Vcc. The double boosting circuit 44 generates a voltage VH obtained by boosting VC twice based on VL. The negative direction double boosting circuit 45 includes:
−V of a voltage obtained by double-raising GND in the negative direction with reference to VC
Generates 3. The double boosting circuit 49 generates Vc based on VC.
A voltage V3 is generated by boosting c twice in the positive direction. Thus, a voltage for driving the liquid crystal panel was formed. Vcc is used as it is for V2, and GND is used as it is for -V2. This power supply circuit is characterized in that the output voltage is symmetric with respect to the midpoint potential VC between the first input potential and the second input potential. According to the eighth embodiment, it is possible to reduce the power consumption of the liquid crystal display device driven by the four-line simultaneous selection method for the same reason as described in the first embodiment.

When the desired voltage has five levels,
In FIG. 30, the double boosting circuit 49 and the negative double boosting circuit 45 may be omitted.

Ninth Embodiment FIG. 31 is a block diagram of a power supply circuit according to a ninth embodiment. In the ninth embodiment, the output voltage of the power supply circuit is formed symmetrically with respect to the first and second input potentials Vcc and the midpoint potential of GND. The power supply circuit according to the ninth embodiment includes:
This is a circuit for driving a liquid crystal panel using a two-terminal nonlinear switching element. The power supply circuit described with reference to FIG.
While the power supply voltage applied to the driver is fluctuated, the power supply circuit of the ninth embodiment outputs a steady voltage that does not fluctuate. FIG. 32 shows an example of a panel drive waveform when this power supply circuit is used.

First, FIG. 32 will be described. VSH
Is a positive-side selection voltage, and VSL is a negative-side selection voltage. VNH is a non-selection voltage after selecting VSH,
VNL is a non-selection voltage after VSL is selected. Each voltage has a relation of VSH-VNH = VNL-VSL, in other words, the midpoint potential between VNH and VNL is VSH and VSL.
Is equal to the midpoint potential. The horizontal axis t is a time axis, and one scale corresponds to the length t1H of one selection period. The column electrode drive waveform is an example in the case where the gray scale means is a pulse width gray scale. By making the voltage for driving the column electrodes coincide with the non-selection voltage for the row electrodes as shown in FIG. 32, the configuration of the power supply circuit is significantly simplified.

Next, the circuit of FIG. 31 will be described. VNH and V, which are non-selection voltages and are also column electrode drive voltages
The logic drive voltage Vcc and GND are used as they are for NL. The negative direction quintuple booster circuit 52 generates a voltage VEE obtained by boosting GND five times in the negative direction with reference to Vcc. When Vcc is 5V, VEE becomes -20V. The boosting circuit 60 boosts the same voltage difference as VNL-VSL based on VNH to generate VSH. Thus, a voltage for driving the liquid crystal panel was formed. The power supply circuit having this configuration is characterized in that the output voltage is symmetric with respect to the midpoint potential of the first and second input potentials.

When the liquid crystal panel using the two-terminal type non-linear switching element is driven by the power supply circuit having the above configuration, the operating voltage of the power supply circuit and the Y driver becomes almost twice as high as that of the swing power supply system. Regardless, the power consumption of the liquid crystal display device can be reduced. One of the reasons is that the voltage applied to the Y driver is static,
This is because the problem that occurred in the swing power supply system does not occur. That is, in the present embodiment, the problem that the entire parasitic capacitance of the Y driver is charged / discharged at the voltage width that fluctuates and the problem that the current flows in the Y driver in a short-circuit manner at the timing of fluctuating do not occur. High voltage is 2
Even if the voltage becomes nearly double, the charge / discharge current or short-circuit current of the high voltage system of the Y driver during one selection period occurs in only one of hundreds of outputs, so the current increase due to the increase in voltage is increased. Is negligible. Another reason is that the power consumption of the power supply circuit itself is extremely small. this is,
This is because the output voltage is generated by a highly efficient charge pump type booster circuit. According to this embodiment, it is possible to drive a liquid crystal panel using a two-terminal non-linear switching element with about half the power consumption of the swing power supply system.

In this embodiment, the negative-direction quintuple booster circuit 5 is used.
2 has been described. However, when a low-voltage liquid crystal is used, the negative-direction quintuple boosting circuit 52 may be replaced by a negative-direction quadruple boosting circuit. In addition, Vcc may be reduced to 3.3 V, and if necessary, the negative-direction quintuple boosting circuit 52 may be replaced with a negative-direction quintuple boosting circuit. In this embodiment,
Although the gradation display means has been described as being based on the pulse width modulation method, a frame thinning method may be used.

When the desired voltage has five levels,
In FIG. 31, a 1/2 voltage step-down circuit may be added between VCC and GND to generate the central potential.

[Embodiment 10] FIG. 33 is a block diagram of a power supply circuit according to Embodiment 10. In the tenth embodiment, unlike the ninth embodiment, the first and second input potentials Vcc and VNL which are different from GND are generated. Then, the output voltage of the power supply circuit is formed symmetrically with respect to the midpoint potential between VNL and Vcc or GND.

In the tenth embodiment, VNH, which is a non-selection voltage and a column electrode driving voltage, is added to the logic driving voltage V.
Use cc as it is. Negative 3/2 times booster circuit 61
Generates a voltage VNL obtained by boosting GND in a negative direction by 3/2 times based on Vcc. A configuration example of the negative direction 3/2 booster circuit 61 is as described with reference to FIGS. 15A and 15B. The negative direction quintuple booster circuit 62 generates a voltage VEE obtained by boosting VNL five times in the negative direction with reference to Vcc. When Vcc is 3.3 V, Vcc-VNL is 4.
95V, VNL-VEE became 19.8 V, and Example 9
, An output voltage substantially equal to that when Vcc is 5 V can be obtained. The booster circuit 70 outputs VNL- based on VNH.
The same voltage difference as VSL is boosted in the positive direction to generate VSH. Thus, a voltage for driving the liquid crystal panel was formed.
This power supply circuit has a potential VN different from the first and second input potentials.
L is generated by the charge pump circuit, and the output voltage is Vc
It is characterized by being symmetric with respect to the midpoint potential of c and VNL. According to the tenth embodiment having the above configuration, the logic voltage can be reduced to a low voltage, so that the liquid crystal panel using the two-terminal type nonlinear switching element can be driven with lower power consumption than the ninth embodiment.

[Eleventh Embodiment] FIG. 34 is a block diagram of a power supply circuit according to an eleventh embodiment. The difference from the first embodiment shown in FIG. 1 is that in the eleventh embodiment, the input power supply voltage is the third input potential V
ee. That is, while the first embodiment has a single power supply configuration (Vcc, GND), the eleventh embodiment has a two power supply configuration (Vee, Vcc, GND).

The negative direction double boosting circuit 72 is a voltage VL that doubles GND in the negative direction based on the third input potential Vee.
Is generated by the charge pump operation. The negative-direction double boosting circuit 73 generates a voltage -V3 which is twice the GND in the negative direction with reference to the first input potential Vcc. The 圧 step-down circuits 74 and 75 generate a voltage V2 obtained by equally dividing Vcc and GND, and a voltage -V2 obtained by equally dividing GND and (−V3). Vcc is used as it is for V3, and GND is used as it is for VC. With the power supply circuit having the above configuration, a necessary voltage can be formed by, for example, a four-line simultaneous selection method. The configuration of the charge pump type 降 step-down circuit is as described above with reference to FIG.

FIG. 35 is a block diagram in the case where １ ／ step-down circuits 76 and 77 are provided instead of １ ／ step-down circuits 74 and 75. The 1/3 step-down circuits 76 and 77 respectively
Voltages V1 and V2 obtained by dividing cc-GND by 1/3
A voltage -V obtained by dividing between GND and (-V3) by 1/3
1. Generates -V2. With this power supply circuit, for example,
The required voltage can be formed by the simultaneous line selection method.

In this embodiment, G is used for easy understanding.
Although the case where both Vee and Vcc have a positive potential with respect to ND has been described, it is not necessary that both Vee and Vcc have a positive potential, and as shown in FIG. 36, one or both of Vee and Vcc are with respect to GND. May be a negative potential.

The present embodiment described above has the following structural features.

That is, in this embodiment, the first input potential Vcc on the high potential side and the second input potential GND on the low potential side included in the input power supply voltage are changed from the first to Nth potentials (N ≧ 4). The G potential V3 and the J potential VC are used as they are. In addition, a third potential on the higher potential side or lower potential side than the first and second input potentials
The input potential Vee is used as one of the first potential VH on the high potential side and the N-th potential VL on the low potential side. A charge pump circuit (a negative double booster circuit 72) that performs a charge pump operation based on a given clock and supplies one of the first and Nth potentials VH and VL directly or via an adjusting unit. And a charge pump circuit (negative double booster circuit) that supplies the F-th potential (1 <F <N) higher or lower than the G-th and J-th potentials directly or via an adjusting means. 73). Further, a charge pump circuit (1) that performs a charge pump operation based on a given clock with a potential other than the first, F-th, G-th, J-th, and N-th potentials among the first to N-th potentials. / 2 step-down circuit 74,
75, 1/3 step-down circuits 76, 77). According to the above configuration, the first potential VH or the N-th potential VL that does not require much output capability is supplied by the charge pump circuit having low output capability but high efficiency,
The G-th potential V3 and the J-th potential VC are connected to input power supply voltages Vcc and GND having high output capabilities. Further, voltages such as V2 and -V2 are supplied by a charge pump circuit. This makes it possible to maintain both display quality and lower power consumption. The configuration of the present embodiment also has a structural feature described in (3) of the first embodiment, that is, a structural feature in which charge pump circuits such as K-fold boost and L / M-fold buck are mixed. are doing.

Next, the power consumption of this embodiment will be described. Assuming that the current consumption of the V3-VC system of the load circuit downstream of the power supply circuit is Ic and the current consumption of the -V3-VC system is Id, according to the present embodiment, the power consumption by Ic is Ic ×
Vcc. Further, by making the negative direction double boosting circuit 73 an efficient boosting circuit, the power consumption due to Id becomes approximately Id × Vcc. On the other hand, in the power supply circuit of FIG. 49, the power consumption by Ic is Ic × VEE, and the power consumption by Id is Id × VEE. Suppose Vcc = 5
Assuming that V and VEE = 20 V, the power consumption of the power supply circuit of FIG. 49 is (Ic + Id) × 20 V, and the power consumption of this embodiment is (Ic + Id) × 5 V. Therefore, power consumption can be reduced to about 1/4.

Although the above description focuses on the intermediate voltage only, the same can be said for the power consumption at VH and VL. That is, assuming that the current consumption of the VH-VC system of the load circuit downstream of the power supply circuit is Ia and that of the VL-VC system is Ib, the power consumption by Ia and Ib is as shown in FIG.
In the power supply circuit of (1), the voltage is (Ia + Ib) × 20 V. On the other hand, in this embodiment, the power consumption is substantially (I
a + Ib) × 10 V, which can be reduced by about half. As can be seen from the above description, in the present embodiment, when the load circuit requires the center voltage and most of the current consumption flows between the center voltage and another voltage, the power consumption is significantly reduced. It becomes possible.

In the eleventh embodiment, similar to the first embodiment,
A charge pump operation can be performed by generating a clock using LP which is a pulse-like clock. Also in the eleventh embodiment, charge pump circuits having various configurations as described in the second embodiment can be adopted. Further, it is also possible to reduce the power consumption by employing various methods as described in the third to sixth embodiments. 34 and 35, the output voltage is symmetric with respect to GND, but symmetric with respect to Vcc, symmetric with respect to the midpoint voltage between Vcc and GND.
It is also possible to form an output voltage symmetrically with respect to a given generated voltage and a midpoint voltage between Vcc and GND. Further, in FIG. 34, 1/2 step-down circuits 74 and 75 are provided to obtain a voltage of 7 levels. However, when the desired voltage is 5 levels, 1/2 step-down circuits 74 and 75 may be omitted. . Further, when performing 降 step-down, 、 step-down or the like using an operational amplifier, the configuration shown in FIG. 2 may be used.

[Embodiment 12] In Embodiment 12, when at least one of the stop of the supply of the input power supply voltage, the stop of the supply of the given clock, or the input of the display-off control signal is performed, the first and Nth potentials are changed. This is an embodiment in which a residual charge in a circuit portion to which a voltage is supplied by at least one is discharged.

FIG. 37 shows an example of a circuit for discharging the VH and VL residual charges when the supply of the input power supply voltage or the supply of the clock is stopped. In FIG. 37, signals / A and A are clock signals having phases opposite to each other. Trp8 and Trp9 are PMOS transistors, and while the clock is being supplied, the operation of turning on one of the transistors and turning off the other is repeated. Tr
When p8 turns on, the capacitor Cc1 is charged with the voltage Vcc, and when TrP9 turns on, the electric charge of Cc1 moves to Cc2. If the time constant of Cc2 and the resistance Rc is set to be sufficiently larger than the cycle of the clock signal, the input of the buffer Buf will be at a level almost close to the voltage Vcc. When the clock stops, one of the transistors is always turned off, so that the input of Buf becomes the GND level by Rc, and the output of Buf also becomes the GND level. Voltage Vcc
The input and output of Buf are GN even when the supply of
It becomes D level.

Trn5 and Trn6 are NMOS transistors, and Trp5, Trp6 and Trp7 are PMOS transistors. Ra1, Ra2, and Rb1 are resistances of about several MΩ, and are each set to a resistance value larger than the resistance when Trn5 and TrP5 are turned on. Therefore, the consumption current flowing through these resistors is small even when these transistors are on. When the voltage Vcc is supplied and the clock is supplied, Trn5 turns on because the output of Buf is at the Vcc level. When Trn5 turns on, the gate of Trp7 goes low, turning on Trp7, and the voltage Vee is supplied to VH. Also, the gate of Trn6 goes to the GND level and Trn6 turns off. The voltage -V3 is an inverted output of the voltage Vcc (see FIGS. 1 and 3).
4), the voltage is substantially at the level of -Vcc when the clock is operating with the supply of the voltage Vcc. As a result, Trp5 turns on and Trp6 turns off.

When the supply of the voltage Vcc or the supply of the clock is stopped, the output of Buf and the voltage −V3 become GN.
It becomes D level, and both Trn5 and Trp5 are turned off. Tr
When n5 turns off, the gate of Trp7 goes to the Vee level, Trp7 turns off, and the supply from Vee to VH is cut off. Also, the gate of Trn6 is turned on at the Vee level, and the charge remaining in the VH system is discharged to GND through a resistor Ra3 of about 10 KΩ. Also Trp5
Is turned off, the gate of Trp6 goes low and Tr
p6 is turned on, and the charge remaining in the VL system is discharged to GND through a resistor Rb2 of about 10 KΩ.

As described above, according to the present embodiment, the voltage V
When the supply of cc or clock stops, the voltage Ve
It is possible to cut off the supply of e and discharge the residual charge in the circuit portion to which the voltage is supplied by the voltages VH and VL, without substantially increasing the power consumption. This can prevent an abnormal situation in which a high DC voltage is continuously applied to the circuit portion.

FIG. 38 shows that the display ON / OFF signal
An example of a circuit for discharging H and VL-based charges will be described. The main difference from FIG. 37 is that the signal Don is input to the gate of Trn5. The signal Don is a signal for controlling the display on / off of the liquid crystal display device.
cc), which is a signal which becomes low level (GND) when the display is off. When Don is at a high level, Trn5 turns on,
As a result, the gate of Trp7 becomes the low side, and Trp7 is turned on. As a result, the voltage Vee is supplied to VH.

On the other hand, when Don is at low level, Trn5
Is turned off, so that the gate of Trp7 becomes the same level as Vee, and Trp7 is turned off. Thus, the supply of the voltage Vee to VH is cut off. At the same time, the gate of Trn6 becomes the same level as Vee, and Trn6 turns on. As a result, electric charges remaining in the VH system are discharged.

As described above, by inputting the display on / off control signal to the power supply circuit of this embodiment, the display on / off of the liquid crystal display device can be easily controlled without increasing current consumption. Instead of directly inputting the signal Don to the gate of Trn5 as described above, a circuit for stopping the clock when Don is low is discharged to discharge the VH-system residual charges and display the liquid crystal display device. It may be turned off. Further, as shown in FIG. 4, the liquid crystal display device may be turned off by controlling the reset terminal of the DF to stop the clock and stop the operation of the charge pump circuit.

FIGS. 39A and 39B show circuit examples for discharging the VH and VL-system charges when the input power supply is turned off. For example, in FIG. 39A, when the input power is turned off and Vcc = GND, Trn10 is turned off and Trn10 is turned off.
The gate of n11 goes high. Thereby, Trn11
Is turned on, and VH-based charges are discharged to GND. In FIG. 39B, when Vcc = GND, Trp10
Is turned off, and the gate of Trp11 is on the low side. This turns on Trp11 and discharges the VL-based charge to Vcc.

FIGS. 40A and 40B show the case where the input power is turned off and the case where the display off signal is input.
5 shows an example of a circuit for discharging VH and VL-system charges. Dof
f is a signal that goes high (= Vcc) when the display is off. When Doff goes high, the inverted signal / Doff goes low (= GND), which turns off Trn10 and turns the gate of Trn11 high. As a result, Trn11 is turned on, and VH-based charges are discharged to GND. In FIG. 40B, Dof
When f becomes high level, Trp10 turns off and Trp1
One gate is on the low side. This turns on Trp11 and discharges the VL-based charge to Vcc.

[Thirteenth Embodiment] FIG. 41 shows a configuration example of a liquid crystal display device including the power supply circuit described in the first to twelfth embodiments. This liquid crystal display device includes a liquid crystal panel 88 including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes, a power supply circuit 91, and a data line electrode based on a voltage supplied by the power supply circuit 91. It includes an X driver IC (data line driver) 90 for driving, and a Y driver IC (scanning line driver) 89 for driving a scanning line electrode based on a voltage supplied from a power supply circuit.

VCC-GND is a power supply input for driving the logic section of the driver IC, and VEE-GND is a high voltage power supply input for forming a selection voltage. Power supply circuit
In the case of such a configuration, VEE is not required. LP is a latch pulse for the X driver IC.
It is also used as a shift clock for a Y driver IC including a register. Other timing signals and data signals are omitted for easy understanding of the drawing.

FIG. 42 shows an example of a drive voltage waveform when the liquid crystal panel is driven by the circuit of FIG. This driving waveform corresponds to the driving waveform when V111 = V122 is set in the driving method described in claim 1 of Japanese Patent Publication No. 57-57718. Here, VH and VL are voltages applied to the selected scanning line electrode, and VC (VM) is a voltage applied to the non-selected scanning line electrode. Vx0 and Vx1 are voltages applied to the X electrodes in accordance with ON / OFF of display data. M is a control signal for AC driving the liquid crystal.
, The polarity of the voltage applied to the liquid crystal panel is inverted. t1H indicates the length of time during which one scanning line electrode is selected.

The voltages required for this driving method are the same as those of the first to third embodiments.
It can be formed by the power supply circuit described in the twelfth embodiment. For example, the outputs VC, VH, and VL of the power supply circuit 91 are used for the non-selection level VC and the selection levels VH and VL. Also, V2 is used as Vx0 of the voltage for driving the X electrode, and Vx
1 may be -V2. For example, if the duty is 1 /
In the case of 240, VH is usually about 20 V, and V2 is about 1.6 V, which is about half the logic voltage of 3.3 V. Therefore, a voltage obtained by stepping down the logic voltage by half can be used as V2.

The logic voltage of the X driver IC 90 is VC
C-GND may be used as it is. Y driver IC8
In the case where the intermediate voltage of the driver output voltage is sufficient as in the case of the gate line driver IC for a TFT panel, VCC-GND may be used as it is as the logic voltage 9. However, when the low level of the logic voltage is equal to VL as in a normal driver IC for an STN panel, for example, the logic voltage VDD for the Y driver IC 89 is used.
Must be formed separately. FIG. 43 shows an example of a Y driver logic voltage generation circuit used in this case.
The operation is basically the same as that shown in FIG. That is, B is the signal shown in FIG. 5 and is a signal driven using VCC-GND as a power supply. Cs1 and Cs2 are coupling capacitors having a capacitance of about 470 pF,
1 and D2 are diodes, Buf1 and Buf2 are buffers, and Rf1 and Rf2 are resistors of about 1 KΩ. Buf
1 and Rf1 form one hold circuit.
Another hold circuit is formed by f2 and Rf2. FIG.
7 and connect the negative power supply terminal of the buffer to VL
, A voltage VDDy higher than VL by VCC is generated at the positive power supply terminal of the buffer. Therefore, VDDy may be used as a logic power supply for the Y driver IC 89. The operating frequency of the Y driver IC 89 is about 1/80 of that of the X driver IC 90,
The current consumption of the logic section is extremely small. Therefore, it is possible to drive sufficiently with the power supply voltage formed by the above simple method. The circuit of FIG. 43 also has a function of forming a Y driver shift clock YSCL by level shifting the signal LP. Preferably, a smoothing capacitor Cx of about 0.1 μF is provided between the power supply terminals of the buffer.

The above description has been made on the assumption that VCC is 3.3 V.
However, when VCC is 5 V, it is better to convert the VCC to a lower voltage using an operational amplifier or the like and drive the power supply circuit 91, the Y driver IC 89, and the X driver IC 90 in order to reduce power consumption. preferable. Also, VC
When C is about 1.5 V, this VCC is directly used as Vx
0 and the inverted boosted voltage of VCC (doubled boosted voltage in the negative direction) may be used as Vx1.

In the liquid crystal display device having the above structure, the power supply circuit itself consumes low power. Furthermore, the charging / discharging current that occupies most of the panel current, that is, the charging / discharging current flowing between the X electrode and the non-selected Y electrode is not supplied from the high voltage system but a lower logic unit driving voltage. Supplied from the system. Therefore, the power consumption due to the panel current is greatly reduced, and the power consumption can be significantly reduced as a whole.

[Embodiment 14] FIG. 44A shows another configuration example of the liquid crystal display device. Since the configuration is basically the same as that of the thirteenth embodiment, only the parts different from the thirteenth embodiment will be described. This embodiment is an example in which the Y electrode is driven by the two-line simultaneous selection method.

FIG. 44B shows the voltage required to be applied to the liquid crystal panel in the case of this driving method. As in the thirteenth embodiment, the non-selection level VC
(VM) and selection levels VH and VL are required. Here, VH and VL have a symmetrical relationship with each other about VC. To drive the X electrode, three of Vx0 to Vx2 are used.
Level voltage is required. Vx1 has the same potential as VC, and Vx0 and Vx2 have a symmetrical relationship with each other about Vx1. For example, when the number of Y electrodes to be scanned in one frame period is about 240 and a normal liquid crystal having an effective value of about 2 V in Vth (threshold voltage) is used, VH is about 0 V when VC is 0 V. 16V and Vx0 are about 2V. That is, the only difference from the thirteenth embodiment is that the center potential is added as the drive voltage of the X electrode, and that VH slightly decreases and Vx0 slightly increases. The power supply circuit of this embodiment is suitable for generating such symmetrical voltages with low power consumption.

When VCC is 3.3 V, a low-voltage liquid crystal having an effective value Vth of about 1.6 V may be used. When VCC is about 1.5 V, low-voltage liquid crystal is used, and this VCC may be used as it is as Vx0.

In the liquid crystal display device of this embodiment, the power supply circuit itself has low power consumption, and the power consumption due to the panel current is greatly reduced for the same reason as described in the thirteenth embodiment. In addition, the maximum voltage required for driving is lower than that of the thirteenth embodiment, and further lower power consumption can be achieved. FIG. 49
In the comparative example, if the current consumption in the logic section and the like of the X driver is IXD, the power consumption due to this is IXD × VE
E. On the other hand, in this embodiment, the power consumption is I
XD × VCC is sufficient, and power consumption can be significantly reduced as compared with the comparative example.

[Embodiment 15] FIG. 45A shows another configuration example of the liquid crystal display device. This embodiment is an example in the case where the Y electrodes are driven by the four-line simultaneous selection method.

FIG. 45B shows the voltages required to be applied to the liquid crystal panel in the case of this driving method. The non-selection level VC and the selection levels VH and VL are required to drive the Y electrode, and VH and VL have a symmetrical relationship with each other about VC. For driving the X electrode, Vx0 to Vx
A voltage of five levels of x4 is required, and Vx2 has the same potential as VC. Vx0 and Vx4 and Vx1 and Vx3 are Vx2
Vx0-Vx1
= Vx1-Vx2 = Vx2-Vx3 = Vx3-Vx4. For example, when the number of Y electrodes to be scanned in one frame period is about 240 and a normal liquid crystal whose Vth is an effective value of about 2 V is used, if the voltage of VC is 0 V, VH is about 11.3 V, Vx0 becomes approximately 2.9V. That is, the only difference from the fourteenth embodiment is that two levels of voltages symmetric with respect to the central potential are added as the drive voltage of the X electrode, and that VH slightly decreases and Vx0 slightly increases.

In particular, when VCC is 3.3 V, since VCC and Vx0 are relatively close to each other, VCC can be used as it is as Vx0 as shown in FIG. In this case, the contrast can be easily adjusted by using a liquid crystal having a slightly higher Vth or setting a slightly lower VEE.

Embodiment 16 FIG. 46A shows another configuration example of the liquid crystal display device. This embodiment is an example in the case where the Y electrodes are driven by the 6-line simultaneous selection method.

FIG. 46B shows the voltages required to be applied to the liquid crystal panel in this driving method. To drive the Y electrode, a non-selection level VC and a selection level VH
And VL are required, and VH and VL have a symmetrical relationship with each other about VC. For driving the X electrode, Vx0
A voltage of 7 levels of Vx6 is required, Vx3 is the same potential as VC, and Vx0 to Vx6 are Vx0-Vx1 = V
x1-Vx2 = Vx2-Vx3 = Vx3-Vx4 = Vx
4-Vx5 = Vx5-Vx6 is satisfied. For example, when the number of Y electrodes to be scanned in one frame period is about 240 and a normal liquid crystal whose Vth is an effective value of about 2 V is used, when the voltage of VC is 0 V, VH is about 9.2 V, V
x0 is about 3.6V. That is, the only difference from the fifteenth embodiment is that two levels of voltages symmetric with respect to the central potential are added as the drive voltage of the X electrode, and that VH slightly decreases and Vx0 slightly increases.

In particular, when VCC is 3.3 V, since VCC and Vx0 are at relatively close levels, VCC can be used as it is as Vx0 as shown in FIG. In this case, the contrast can be easily adjusted by using a liquid crystal with a slightly lower Vth or setting a slightly higher VEE.

The practicality of the number of simultaneously selected Y electrodes will be described below. For example, when the number of Y electrodes to be scanned within one frame period is about 240, when the number of lines to be selected simultaneously is 15 to 16, the maximum voltage width required for driving the Y electrodes and the driving for the X electrodes The required maximum voltage width becomes equal. When a normal liquid crystal having an effective value of about 2 V is used, this voltage is slightly less than 6 V. That is,
In the range where the number of simultaneously selected lines is 16 or less, the driving method in which the number of simultaneously selected Y electrodes is large requires a lower maximum voltage, which is advantageous in reducing power consumption. However, conversely, the number of voltage levels required for driving increases, the power supply circuit becomes complicated, and the X driver I
Since the cost of C also increases, it can be said that it is practical to select eight or less lines at the same time.

In the thirteenth to sixteenth embodiments described above,
For example, as shown in FIG. 46A, the first and second input potentials VCC and GND are changed to V3, V2, V1, VC, -V1,
It is used as any one of -V2 and -V3 (first to N-th potentials), and is also used as a power supply voltage for the logic section of the driver IC. It is better to prepare another power supply voltage for driving the logic part of the driver IC in addition to the input power supply voltage (VEE, VCC, GND or VCC, GND) used in the power supply circuit 91, so that the liquid crystal panel can be set to the optimum voltage. It is preferable in terms of driving. However, an increase in the number of input power supply voltages is not preferable for a user of the liquid crystal display device. As described in Examples 13 to 16, V
When CC and GND are used as any of V3, V2 to -V2, and -V3 and used as the power supply voltage of the logic section of the driver IC, the drive is performed with a voltage slightly deviated from the optimum voltage. Can display an image having no problem. Therefore, it is more practical to suppress an increase in the number of input power supply voltages as in the thirteenth to sixteenth embodiments.

In the case where none of V3, V2 to -V2, and -V3 matches VCC and GND, FIG.
As explained in the above, VC
C, a voltage different from GND is generated, and this generated voltage is
3, V2 to -V2, or -V3.

Also, as shown in FIG.
In the sixteenth embodiment, the X-driver latch pulse signal LP or the Y driver latch pulse signal LP or Y
The driver shift clock YSCL is used. The reason why the signal forming the clock of the power supply circuit 91 is preferably a periodic pulsed clock is as already described in the second embodiment. Normally, the latch pulse signal for the X driver is a periodic pulsed clock signal having a cycle of about 30 μs to 100 μs and a pulse width of about 100 ns to 300 ns, and thus can be used as a pulsed clock of the power supply circuit 91 without any problem. In some liquid crystal display devices, the Y-driver shift clock is inputted separately from the X-driver latch pulse. In this case, the Y-driver shift clock is also a periodic pulse-like clock signal similar to the X-driver latch pulse. Therefore, there is no problem using this clock. Among the timing signals input to the liquid crystal display device, these signals are most appropriate. Since most of the current consumption of the liquid crystal display device is a current flowing every time one horizontal scanning period is switched, a charge pump circuit for supplying the current is used for an X driver which is a pulsed clock for each horizontal scanning period. It makes sense to operate in synchronization with a latch pulse or a Y driver shift clock. With a clock signal having a longer cycle than this, the boosting capability becomes insufficient. On the other hand, a pulse-like clock signal having a shorter cycle is preferable for securing the boosting capability.
Since these signals are not input to the liquid crystal display device, they need to be separately generated, which leads to an increase in the size of the circuit.

[Embodiment 17] FIG. 47 shows an example in which the liquid crystal display device of the present invention is mounted on an electronic apparatus. A μPU (micro-microprocessor unit) 112 controls the entire electronic device.
Reference numeral 3 denotes a device for transmitting a timing signal and display data necessary for the liquid crystal display device 115. The memory (VRA
M) 114 stores display data, and the battery 116 is a power supply of the electronic device. The DC / DC converter 117 converts the voltage of the battery 116
To generate the high voltage required for The DC / DC converter 117 may be built in the liquid crystal display device. In the case where the DC / DC converter 117 is built in, a charge pump type D
It is desirable to use a C-DC converter. By using the liquid crystal display device of the present invention for such an electronic device, the power consumption of the electronic device can be significantly reduced.

It should be noted that the present invention is not limited to the above embodiments 1 to 17.
The present invention is not limited to this, and various modifications can be made within the scope of the present invention.

For example, a method using a pulsed clock,
The method of changing the step-up ratio, the method of performing the charge pump every one horizontal period, and the like are not limited to the power supply circuit having the configuration shown in FIGS. Any power supply circuit including a circuit can be applied.

Also, the configuration of the charge pump circuit is shown in FIGS.
The invention is not limited to the one shown in FIG.

In the above embodiment, the charge pump circuit using the latch pulse LP has been described as an example.
When the LP is not used, a non-overlapping clock may be generated using a delay circuit or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power supply circuit according to a first embodiment.

FIG. 2 is a block diagram when an operational amplifier is used to generate V2 and -V2.

FIG. 3 is a circuit diagram illustrating an example of a contrast adjustment circuit.

FIG. 4 is a circuit diagram illustrating an example of a clock forming circuit.

FIG. 5 is a timing chart for explaining the operation of the clock forming circuit.

FIG. 6 is a basic conceptual diagram of a charge pump circuit.

FIG. 7 is a conceptual diagram of a double boosting charge pump circuit.

FIG. 8 is a conceptual diagram of a negative-direction double boosting charge pump circuit.

FIG. 9 is a conceptual diagram of a 降 step-down charge pump circuit.

FIG. 10 is a conceptual diagram of a charge pump circuit for boosting the negative direction six times.

FIGS. 11A and 11B are diagrams for explaining the operation of the circuit in FIG. 10;

FIG. 12 is a conceptual diagram of another example of a charge pump circuit for boosting the negative direction six times;

13A and 13B are diagrams for explaining the operation of the circuit in FIG. 12;

FIGS. 14A and 14B are conceptual diagrams of a charge pump circuit for 3/2 boosting.

15 (A) and 15 (B) show the negative direction 3 /
FIG. 2 is a conceptual diagram of a double boosting charge pump circuit.

16A and 16B are conceptual diagrams of a 2/3 step-down charge pump circuit.

17 (A) and 17 (B) show negative direction 2 /
It is a conceptual diagram of the charge pump circuit for 3 times step-down.

FIG. 18 is a circuit diagram showing a specific example of a negative direction double boosting circuit.

FIG. 19 is a diagram for explaining the operation of the circuit in FIG. 18;

FIGS. 20A and 20B are circuit diagrams illustrating an example of a level shift unit. FIGS.

FIG. 21 is a circuit diagram illustrating an example of a charge pump circuit using a diode.

FIG. 22 is a diagram for explaining the operation of the circuit in FIG. 21;

FIG. 23 is a circuit diagram showing an application example of the circuit of FIG. 21;

FIG. 24 is a circuit diagram showing an example of a charge pump circuit provided with two pumping capacitors.

FIG. 25 (A), FIG. 25 (B), FIG. 25 (C)
FIG. 5 is a diagram for explaining a method of performing a charge pump operation every horizontal scanning period.

FIG. 26 shows a charge / discharge unit provided with a step-up / step-down magnification change unit.
It is a circuit diagram showing an example of a pump circuit.

FIG. 27 shows a charge / discharge unit provided with a step-up / step-down magnification change unit.
It is a circuit diagram showing another example of a pump circuit.

FIGS. 28A and 28B are circuit diagrams illustrating an example in which supply of high voltage is stopped for a given period after power-on.

FIG. 29 is a block diagram of a power supply circuit according to a seventh embodiment.

FIG. 30 is a block diagram of a power supply circuit according to an eighth embodiment.

FIG. 31 is a block diagram of a power supply circuit according to a ninth embodiment.

FIG. 32 is a diagram illustrating an example of a panel drive waveform.

FIG. 33 is a block diagram of a power supply circuit according to a tenth embodiment.

FIG. 34 is a block diagram of a power supply circuit according to an eleventh embodiment.

FIG. 35 is a block diagram showing another example of the power supply circuit according to the eleventh embodiment.

FIG. 36 is a diagram for describing a potential relationship between input power supply voltages.

FIG. 37 is a circuit diagram showing an example of discharging residual charges of VH and VL systems.

FIG. 38 is a circuit diagram showing another example of discharging VH and VL-based residual charges.

39 (A) and 39 (B) show VH and VL.
FIG. 9 is a circuit diagram showing another example of discharging a residual charge of the system.

FIGS. 40A and 40B show VH and VL
FIG. 9 is a circuit diagram showing another example of discharging a residual charge of the system.

FIG. 41 is a block diagram illustrating an example of a liquid crystal display device according to Example 13.

FIG. 42 is a diagram illustrating a drive waveform of the liquid crystal display device of FIG. 41.

FIG. 43 is a circuit diagram showing an example of a level shift means.

FIG. 44A is a block diagram illustrating an example of a liquid crystal display device according to Example 14, and FIG.
FIG. 4 is a diagram for explaining a potential relationship of a driving voltage.

FIG. 45A is a block diagram illustrating an example of a liquid crystal display device according to Example 15, and FIG.
FIG. 4 is a diagram for explaining a potential relationship of a driving voltage.

FIG. 46A is a block diagram illustrating an example of a liquid crystal display device according to Example 16, and FIG.
FIG. 4 is a diagram for explaining a potential relationship of a driving voltage.

FIG. 47 is a block diagram illustrating an example of an electronic apparatus according to a seventeenth embodiment.

FIG. 48 is a circuit diagram illustrating an example of a power supply circuit according to a first background example.

FIG. 49 is a circuit diagram illustrating an example of a power supply circuit according to a second background example.

FIG. 50 is a diagram showing an example of a panel drive waveform for describing the power supply circuit of the third background example.

FIG. 51 is a circuit diagram illustrating an example of a power supply circuit according to a third background example;

[Explanation of symbols]

 LP latch pulse Vcc 1st input potential GND 2nd input potential VH 1st potential V3 Gth potential VC Jth potential VL Nth potential 1 Clock formation circuit 2 Negative 6 times booster circuit 3 Contrast adjustment circuit 4 2 times booster circuit 5 Negative double booster circuit 6 1/2 step-down circuit 7 1/2 step-down circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H02M 3/07 H02M 3/07 F term (Reference) 2H093 NA46 NC34 ND07 ND39 5C006 AF42 AF52 AF72 AF84 BB12 BF14 BF25 BF32 BF36 BF37 BF43 BF46 FA47 5C080 AA10 BB05 DD26 FF03 FF12 JJ02 JJ03 JJ04 5H730 AA14 AS00 BB02 DD04 FF06 FG01

Claims (10)

[Claims] 1. A power supply circuit to which an input power supply voltage is applied and supplies first to Nth (N ≧ 4) potentials for driving a display element, wherein a pulse-like clock including a periodically generated pulse A charge pump circuit that performs a charge pump operation based on the clock generated by the above and supplies one of the first to Nth potentials directly or via an adjustment unit; and a pumping circuit included in the charge pump circuit. Means for stopping charging of the capacitor and charging of the backup capacitor by the pumping capacitor during the generation period of the pulse of the pulsed clock. 2. A power supply circuit to which an input power supply voltage is applied and supplies first to Nth (N ≧ 4) potentials for driving a display element, wherein a charge pump operation is performed based on a given clock. Do
A charge pump circuit for supplying one of the first potential on the high potential side and the N-th potential on the low potential side, directly or via an adjusting means; and a backup capacitor alternately provided by a plurality of pumping capacitors. A charge pump circuit that performs a charge pump operation for charging based on a given clock and supplies an I-th potential (1 <I <N) among the first to N-th potentials directly or via an adjustment unit. And a power supply circuit. 3. A power supply circuit to which an input power supply voltage is applied and supplies first to Nth (N ≧ 4) potentials for driving a display element, wherein a charge pump operation is performed based on a given clock. Do
A charge pump circuit that supplies any one of the first to Nth potentials directly or via an adjustment unit; and charging a pumping capacitor included in the charge pump circuit and charging a backup capacitor using the pumping capacitor. 1 in driving the display element
A power supply circuit for performing the operation every horizontal scanning period. 4. The power supply circuit according to claim 3, wherein the charge pump circuit performs a charge pump operation of alternately charging a backup capacitor every one horizontal period by a plurality of pumping capacitors. 5. The power supply circuit according to claim 1, further comprising means for stopping a given clock of said charge pump circuit. 6. A power supply circuit according to claim 1, a liquid crystal panel including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes, and a potential supplied by said power supply circuit. A liquid crystal display device comprising: a data line driver that drives the data line electrode based on the potential; and a scanning line driver that drives the scanning line electrode based on a potential supplied by the power supply circuit. 7. The first to Nth (N)
≧ 4) a power supply circuit for supplying a potential, a liquid crystal panel including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes, and the data line electrode based on the potential supplied by the power supply circuit. A liquid crystal display device comprising: a data line driver to drive; and a scanning line driver to drive the scanning line electrode based on a potential supplied by the power supply circuit, wherein the power supply circuit is included in the input power supply voltage A first input potential on the high potential side,
Means for supplying a second input potential on the low potential side as one of the first to N-th potentials; performing a charge pump operation based on a given clock;
A charge pump circuit that supplies any one of the first to Nth potentials directly or via an adjustment unit, and supplies the first and second input potentials to at least one of the data line driver and the scanning line driver A liquid crystal display device used as a power supply voltage of a logic unit of the above. 8. The power supply circuit according to claim 7, wherein the power supply circuit generates a potential different from the first and second input potentials by a charge pump operation based on a given clock, and generates the potentials from the first to second input potentials. A liquid crystal display device including a charge pump circuit for supplying any one of N potentials. 9. An input power supply voltage is applied and the first to Nth (N
≧ 4) a power supply circuit for supplying a potential, a liquid crystal panel including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes, and the data line electrode based on the potential supplied by the power supply circuit. A liquid crystal display device comprising: a data line driver to be driven; and a scanning line driver to drive the scanning line electrode based on a voltage supplied by the power supply circuit, wherein the power supply circuit comprises a latch for the data line driver. A charge pump operation is performed based on a pulse or a clock generated by the shift clock for the scanning line driver, and the first to Nth
A liquid crystal display device comprising a charge pump circuit for supplying one of the potentials directly or via an adjusting means. 10. An electronic apparatus comprising the liquid crystal display device according to claim 6. Description: