JP2002049360A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a liquid crystal display device to cope with both of the display signals of a sequential scanning and an interlaced scanning and also to dissolve the generation of the connection defect of up-and-down scanning in the sequential scanning in a liquid crystal display device in which two blocks of row scanning electrode driving circuits are arranged. SOLUTION: In this device, ON periods of row selection pulses to be supplied to adjacent row scanning electrodes G are made so as not to be overlapped by connecting gate circuits AND 1, 2,... among outputs B11, B21, B12, B22,... of respective stages of row scanning electrode driving circuits 13, 14 and row scanning electrodes G1, G2, G3,... corresponding to these outputs and by controlling ON periods of row selection pulses with these gate circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device suitable for, for example, a projection display, and more particularly to an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a circuit configuration of a conventional active matrix type liquid crystal display device, particularly showing a circuit configuration when two blocks of row scan electrode driving circuits are arranged.

The liquid crystal display device 10 has a plurality of column signal electrodes D1, D2,... On a single crystal silicon substrate (not shown).
(Hereinafter, collectively referred to as D as appropriate) are arranged in parallel, and a plurality of row scanning electrodes G are arranged in a direction orthogonal to this.
1, G2,... (Hereinafter collectively referred to as G as appropriate) are arranged.

A display pixel PIX is arranged at the intersection of each column signal electrode D and row scanning electrode G. A counter substrate (not shown) on which a common electrode is formed is disposed at a position facing the silicon substrate, and a liquid crystal layer is held between the pixel electrode and the common electrode via an alignment layer. .

The column signal electrode drive circuit 11 includes a horizontal shift register 12 and sampling switches SW1, SW2, S
W3,... SWi (hereinafter, abbreviated to SW as appropriate). The input side of each sampling switch SW is commonly connected to a display signal supply line SIG to which a display signal (Video) is supplied, and the output side is connected to the corresponding column signal electrodes D1, D2, D3,. ing. The horizontal start signal HS supplied from a drive timing generation circuit (not shown)
T, the horizontal shift register 12 is driven by the horizontal clock signals HCK1 and HCK2, and on-pulse signals are sequentially output at a predetermined timing. The sampling switches SW1, SW2, SW3,
Are sequentially turned on so that the display signal to be output in one line period (one horizontal period) is
, D2, D3,... Are sequentially sampled.

The row scanning electrode driving circuits include row scanning electrode driving circuits 13 corresponding to odd-numbered row scanning electrodes G1, G3,... And even-numbered row scanning electrodes G2, G4,. ..Row scanning electrode drive circuit 14 corresponding to
Are arranged.

Each of the row scan electrode drive circuits 13 and 14 is constituted by a circuit including a shift register (not shown), and a vertical start signal VS is supplied from a drive timing generation circuit (not shown).
Todd, vertical clock signal VCK1odd, VCK2od
d is supplied to the row scan electrode drive circuit 13 and the vertical start signal VSTeven, the vertical clock signal VCK1even, and the vertical clock signal VCK1even.
2even is supplied to the row scan electrode drive circuit 14, respectively. A shift register (not shown) of each row scan electrode drive circuit is driven by the VST, VCK1, and VCK2, and is provided with row scan electrodes G1, G3,.
.., G4,...
A row selection pulse (scan signal) is output.

As shown in the circuit diagram of FIG. 6, the display pixel PIX includes a switching transistor Tr and an auxiliary capacitor C.
s, a pixel electrode 15, a common electrode 16, and a liquid crystal layer LC held between these electrodes. Row scan line G
Is supplied with a row selection pulse, the corresponding display pixel PI
The X switching transistor Tr is turned on,
The display signal sampled by the column signal electrode D is applied to the liquid crystal layer LC via the switching transistor Tr. The storage capacitor Cs is connected to hold the drive voltage of the liquid crystal layer LC during the off period of the switching transistor Tr and obtain a high duty ratio. As a result, a display signal is applied to the liquid crystal layer LC corresponding to the display pixel PIX via the pixel electrode 15, and the degree of light modulation of the liquid crystal layer LC changes according to the voltage value of the display signal. Thus, an image corresponding to the information amount of the display signal is displayed.

FIG. 7 shows the row scan electrode drive circuits 13 and 14.
FIG. 2 is a circuit configuration diagram of a shift register included in FIG. The shift register 20 includes a plurality of inverter circuits 21 and a CMO
It is composed of an S transfer gate 22 (the code is assigned to only one). The first-stage inverter circuit 21 receives a VST (odd or eve) signal from a drive timing generation circuit (not shown).
n, VCK) as well as the CM of each stage
To the OS transfer gate 22, two-phase clock signals of VCK1 (# 1 and its inverted clock / # 1) and VCK2 (# 2 and its inverted clock / # 2) are alternately supplied. VST is shifted by one stage by one clock cycle of VCK1 and VCK2, and is output to the row scan electrode G as a row selection pulse.

As shown in FIG. 5, a liquid crystal display device 10 having two blocks of row scanning electrode driving circuits can cope with both sequential scanning (non-interlace) and interlaced scanning (interlace). Next,
The driving method in each of the interlaced scans will be briefly described.

FIG. 8 is a timing chart showing the operation timing in the case of driving by sequential scanning.

Each shift register of the row scan electrode drive circuit 13 and the row scan electrode drive circuit 14 has a transfer clock VCK having a period twice as long as one line period indicated by "t" in the figure.
1 and VCK2 are supplied. This VCK1 and VCK
The phase of CK2 is shifted by one horizontal cycle between odd and even, and the row scan electrode drive circuit 13 and the row scan electrode drive circuit 14
Performs a shift operation with a clock whose phase is shifted by a half cycle (one horizontal cycle). VSTeven is VSTodd
Are input at a timing delayed by one horizontal cycle. As a result, the row scan electrodes G1, G2, G3, G4,.
.., Row selection pulses for two line periods are sequentially sent out with a phase delay of one line period as shown in FIG. According to this, the switching transistors Tr of the display pixels PIX connected to the respective row scanning electrodes G are turned on for two line periods, respectively, but the row selection pulses for the two line periods overlap by one line period. Therefore, the display signal sampled in the first half of the one-line period is rewritten by the display signal sampled in the second half of the continuous one-line period. Therefore, the display signal of the latter half line period is substantially held in the display pixel PIX, and the liquid crystal layer LC is driven by this signal.

FIG. 9 is a timing chart showing the operation timing when driving by interlaced scanning. VCK1 and VCK2 having a cycle equal to one line period (one horizontal period) are supplied to each shift register of the row scan electrode drive circuits 13 and 14 as a transfer clock. This V
The phases of CK1 and VCK2 are the same in both odd and even, and the row scan electrode drive circuit 13 and the row scan electrode drive circuit 14 perform the shift operation with the clock of the same phase. In the odd field period of the display signal, VST for each shift register of the row scan electrode driving circuits 13 and 14 is
odd and VSTeven are input in the same phase, and during the even field period of the display signal, VSTod for the shift register of the row scan electrode drive circuit 13 is equal to the row scan electrode drive circuit 14.
Is input at a timing one line period ahead of VSTeven for the shift register. As a result, in the odd field period of the display signal, the row scan electrodes (G1, G
2), (G3, G4), (G5, G6),..., Row selection pulses are sequentially transmitted, and during even field periods of the display signal, the row scanning electrodes (G2, G3),
A row selection pulse is sequentially transmitted to each set of (G4, G5), (G6, G7),. As described above, by selecting the combination of the row scanning electrodes by shifting one row in the odd field period and the even field period, it is possible to improve the vertical resolution when driven by the display signal of the interlaced scanning.

As described above, the liquid crystal display device 1 in which two blocks of row scanning electrode driving circuits as shown in FIG.
In the case of 0, an optimum driving method can be selected for both the display signal of the progressive scan and the display signal of the interlaced scan.

[0015]

However, in the liquid crystal display device having the conventional configuration in which the row scanning electrode drive circuits are arranged in two blocks, the following problems occur particularly when driven by display signals of sequential scanning. .

FIGS. 10A and 10B are explanatory diagrams of connection defects occurring in display pixels arranged continuously in the vertical direction. FIG. 10A is a circuit diagram of three display pixels PIX continuous in the vertical direction.
(B) schematically shows the display state.
Now, it is assumed that the center display pixel PIX2 marked with x has a defect.

As described above, the row scan electrodes G1, G2, G3, G4,...
, Row selection pulses for two line periods are sequentially sent out with a phase delay of one line period. In this case, the row scan electrode G
During the on-period of the two line periods of n, the next row Gn + 1 is simultaneously turned on during the latter one line period. Therefore, if a short-mode defect (for example, a short-circuit between the source of the switching transistor Tr and the common line of the storage capacitor Cs or a short-circuit with a well (not shown) of the Tr) exists in the display pixel PIX2 of the row scan electrode Gn + 1, the row scan is performed. A display signal sampled by the column signal electrode Dm as a display signal to the display pixel PIX1 of the electrode Gn is applied to the row scan electrode Gn.
As a result, as shown in FIG. 10B, the defect which originally exists solely in the display pixel PIX2 extends to PIX1, and PIX1 and PI
It will be recognized as a connection defect above and below X2.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. In a liquid crystal display device having two blocks of row scan electrode driving circuits, the present invention is applicable to display signals of both sequential scanning and interlaced scanning. It is an object of the present invention to provide a liquid crystal display device which can perform a vertical scanning and eliminate the occurrence of upper and lower connection defects in the sequential scanning.

[0019]

According to a first aspect of the present invention, there is provided a liquid crystal display device comprising: a switching element provided for each of a plurality of display pixels arranged in a matrix; and a plurality of switching elements connected to one main terminal of the switching element. Column signal electrodes, a plurality of row scanning electrodes connected to the control terminal of the switching element, an auxiliary capacitor and a pixel electrode connected to the other main terminal of the switching element, and a display on the plurality of column signal electrodes. A column signal electrode drive circuit for sequentially sampling signals, a first row scan electrode drive circuit for supplying a row selection pulse to a control terminal of the switching element connected to the odd-numbered row scan electrodes, and an even-numbered A second row scan electrode drive circuit for supplying a row selection pulse to a control terminal of the switching element connected to the row scan electrode; and a second row scan electrode driving circuit arranged to face the plurality of pixel electrodes. In a liquid crystal display device including a common electrode, and a liquid crystal member held between the plurality of pixel electrodes and the common electrode, each output of the first and second row scan electrode driving circuits corresponds to each output. A gate circuit for controlling an ON period of a row selection pulse supplied to a control terminal of the switching element is connected between each row scanning electrode.

According to a second aspect of the present invention, in the liquid crystal display device of the first aspect, the first row scan electrode driving circuit includes two switching elements connected to odd-numbered row scan electrodes. A row selection pulse for turning on the line period is supplied, and the second row scan electrode driving circuit generates a row selection pulse for turning on the switching elements connected to the even-numbered row scan electrodes for two line periods. The row selection pulse supplied from the first row scanning electrode driving circuit is supplied with a phase delay of one line period, and is supplied to the gate circuits connected to the odd-numbered row scanning electrodes and the even-numbered row scanning electrodes. By alternately turning on / off the connected gate circuits every one line period, the ON period of the row selection pulse supplied to the adjacent row scan electrode is only the latter one line cycle. Characterized in that way the.

According to the above configuration, the on-period of the row selection pulse is controlled by the gate circuit, so that the on-period of the row selection pulse supplied to each row selection electrode is changed to the row supplied to the adjacent row scanning electrode. It is possible not to overlap with the ON period of the selection pulse. According to this, the ON periods of the row selection pulses supplied to the adjacent row scanning electrodes are completely separated on the time axis, so that a short-mode defect exists in the display pixels belonging to an arbitrary row. However, the influence does not affect the display signals supplied to the other display pixels located above and below.

[0022]

Next, an embodiment in which the liquid crystal display device according to the present invention is applied to an active matrix type liquid crystal display device will be described.

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device according to this embodiment.

In FIG. 1, the column signal electrode drive circuit 11, the row scan electrode drive circuits 13 and 14, the column signal electrodes D1, D2,.
Since the configuration of 1, G2,..., The display pixel PIX is the same as that in FIG. 5, the description of these components will be omitted.

In the liquid crystal display device 100 of this embodiment, the outputs B11, B1 of the respective stages of the row scan electrode drive circuit 13
2,... Are odd-numbered row scan electrodes G1, G
, And the outputs B21, B22,... Of each stage of the row scan electrode drive circuit 14 correspond to the row scan electrodes G2, G4,. .

A row selection is made between the output B11, B21, B12, B22,... Of each stage of the row scan electrode drive circuits 13 and 14 and each row scan electrode G1, G2, G3, G4,. Gate circuit AN for controlling ON period of pulse
D1, AND2, AND3, AND4,... Are connected.

Gate circuits AND1, AND2, AND
3, AND4,... Among the odd-numbered row scan electrodes G
, G3,... Corresponding to gate circuits AND1, AN
One of the gate signal input terminals of D3,... Is commonly wired to the gate signal input line 101, and the other gate signal input terminal is the output B11, B of each row of the row scan electrode drive circuit 13.
,... Further, the gate circuits AND corresponding to the even-numbered row scan electrodes G2, G4,.
, And one of the gate signal input terminals is connected to the gate signal input line 102 in common, and the other gate signal input terminal is connected to the output B of each stage of the row scan electrode drive circuit 14.
, B22,...

The gate signal input lines 101 and 102 have
A gate signal GA from a drive timing generation circuit (not shown)
TE1 and GATE2 are supplied respectively.

Gate circuits AND1, AND2, AND
, AND4, ..., outputs B11, B21, B1
, B22,... Are at the high level and the gate signals GATE1, GATE2 are at the high level,
The high-level pulse signals are output as row selection pulses to the row scan electrodes G1, G2, G3, G4,.

Next, the operation of the liquid crystal display device 100 configured as described above will be described. FIG. 2 is a timing chart showing operation timing when the liquid crystal display device 100 of FIG. 1 is driven by sequential scanning.

Here, HST, HCK1 and HCK2 supplied to the column signal electrode drive circuit 11 and VSTodd, VCK1odd and VCK2 supplied to the row scan electrode drive circuit 13 are provided.
odd, the row V also supplied to the row scan electrode drive circuit 14
STeven, VCK1even, and VCK2even are the same as those in FIG.

From the row scanning electrode driving circuits 13 and 14,
As the outputs B11, B21, B12, B22,... Of each stage, signal pulses for two line periods are sequentially sent out with a phase delay of one line period as shown in the figure. And
From a drive timing generation circuit (not shown), a gate signal GATE that switches between High / Low in one line cycle is provided.
1 and GATE2 are supplied. The levels of the gate signals GATE1 and GATE2 are set such that High / Low are reversed in the same cycle.

The outputs B11, B21, B12, B22 of the respective stages sent from the row scan electrode drive circuits 13 and 14
.. Correspond to the row scanning electrodes G1, G2,
.., The signal pulses for two line periods overlap by one line period. Here, looking at the output B11 sent from the row scan electrode drive circuit 13, the gate signal GATE1 is High during the latter half line period of the output B11.
Therefore, a row selection pulse (High level) for one line period is output to the row scanning electrode G1. Since the gate signal GATE2 is at the low level during the same period, the row selection pulse is not output from the gate circuit AND2 (low level) due to the output B21 sent from the row scan electrode drive circuit 14. Similarly, in the latter half line period of the output B21, the gate signal GA
Since TE2 is at the high level, a row selection pulse (high level) for one line period is output to the row scanning electrode G2. In the same period, the gate signal GATE
1 is at the low level, the row scan electrode drive circuit 13
Output from the gate circuit AND
3 does not output a row selection pulse (Low level).

Here, the gate circuits AND1, AND2,
, The signal pulses of the outputs B11, B21,..., The gate signals GATE1, GATE2, and the row selection pulses respectively output to the row selection electrodes G1, G2,.

Now, the High / Low level of the signal pulse of the output B11, B21,... Of each stage sent from the row scan electrode drive circuits 13 and 14 is set to 5 / 0V, and the High / Low level of the gate signals GATE1 and GATE2 is set. Low
Assuming that the level is 5/0 V, each signal pulse is H
During the high level period, the gate circuits AND1, AND2,
.. Output a 5V row selection pulse as a high-level signal pulse. This row selection pulse is level-converted by a level shift circuit (not shown) to a voltage required to turn on the switching transistor Tr of the display pixel PIX, for example, 15 V, and the row selection electrode G
1, G2,...

As a result of such an operation being repeated in one line cycle, the ON periods (High level) of the row selection pulses output from the gate circuits AND1, AND2,... To the row selection electrodes G1, G2,. ) Is only the latter one line cycle of the two line cycles of the original outputs B11, B21,..., And therefore exceeds the on-period of the row selection pulse supplied to the adjacent row scan electrode. There will be no wrapping and complete separation on the time axis. Therefore, even if a short-mode defect exists in a display pixel belonging to an arbitrary row, the influence does not affect the display signals supplied to the other display pixels located above and below. It is possible to eliminate the occurrence of the connection defect in the display pixel.

When the liquid crystal display device 100 of FIG. 1 is driven by interlaced scanning, the gate signals GATE1 and G
By fixing both of the ATEs 2 at a High level, driving can be performed at the same operation timing as in FIG.

The liquid crystal display device 100 shown in FIG. 1 can not only eliminate the occurrence of the upper and lower connection defects in the sequential scanning, but also can cope with the display signals of both the sequential scanning and the interlaced scanning. When the correspondence is not taken into consideration, for example, a circuit configuration as shown in FIG. 3 can be adopted.

In the liquid crystal display device 200 shown in FIG.
One of the gate circuits AND1, AND3,... Corresponding to the odd-numbered row scan electrodes G1, G3,... Is commonly wired to the gate signal input line 103, and is supplied with the gate signal GATE. You. Further, one gate signal input terminal of the gate circuits AND2, AND4,... Corresponding to the even-numbered row scanning electrodes G2, G4,. An inverted gate signal GATE is supplied. Other configurations are the same as those in FIG. 1, and the same parts are represented by the same reference numerals. FIG. 4 shows a timing chart of the operation timing at this time.

As described above, when the circuit configuration is specialized for sequential scanning, only one gate signal GATE can be supplied from a drive timing generation circuit (not shown), so that the number of external wirings can be reduced. Can be.

In the above-described embodiment, the gate circuit is connected to AN
Although the example in which the circuit is constituted by the D circuit is described, the function of the gate circuit may be constituted by an OR circuit.

[0042]

As described above, in the liquid crystal display device according to the present invention, the on-period of the row selection pulse supplied to the adjacent row scanning electrode does not overlap in the sequential scanning, so that the influence of the defective pixel is reduced. It is possible to eliminate the occurrence of a connection defect in the display pixels located above and below without affecting the display signals supplied to the other display pixels located above and below.

Accordingly, it is possible to provide a liquid crystal display device which can not only respond to the display signals of both the sequential scanning and the interlaced scanning but also eliminate the occurrence of upper and lower connection defects in the sequential scanning.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device according to an embodiment.

FIG. 2 is a timing chart showing operation timing when the liquid crystal display device of FIG. 1 is driven by sequential scanning.

FIG. 3 is a block diagram showing a circuit configuration of a liquid crystal display device according to another embodiment.

FIG. 4 is a timing chart showing operation timing when the liquid crystal display device of FIG. 3 is driven.

FIG. 5 is a block diagram showing a circuit configuration of a conventional active matrix type liquid crystal display device.

FIG. 6 is a circuit configuration diagram of a display pixel PIX.

FIG. 7 is a circuit configuration diagram of a shift register included in each row scan electrode drive circuit.

8 is a timing chart showing operation timing when the liquid crystal display device shown in FIG. 5 is driven by sequential scanning.

9 is a timing chart showing operation timing when the liquid crystal display device shown in FIG. 5 is driven by interlaced scanning.

FIG. 10 is an explanatory diagram of a connection defect generated in display pixels arranged continuously in the vertical direction.

[Explanation of symbols]

10, 100, 200 liquid crystal display device, 11 column signal electrode drive circuit, 13, 14 row scan electrode drive circuit, 15
Pixel electrode, 16: common electrode, LC: liquid crystal layer, PIX: display pixel, Cs: storage capacitor, Tr: switching transistor

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) G09G 3/20 670 G09G 3/20 670A F term (Reference) 2H093 NA45 NA46 NC10 NC22 NC34 ND16 ND60 NG02 NH15 5C006 AC22 AC29 AC30 BB16 BC03 BF03 BF11 BF26 EB04 EC11 5C080 AA10 BB05 BB08 DD01 DD09 DD23 FF11 JJ01 JJ02 JJ03 JJ04

Claims (2)

[Claims] A switching element provided for each of a plurality of display pixels arranged in a matrix; a plurality of column signal electrodes connected to one main terminal of the switching element; and a control terminal of the switching element. A plurality of connected row scanning electrodes, an auxiliary capacitor and a pixel electrode connected to the other main terminal of the switching element, a column signal electrode driving circuit for sequentially sampling a display signal to the plurality of column signal electrodes, and an odd number A first row scan electrode drive circuit for supplying a row selection pulse to a control terminal of the switching element connected to the first row scan electrode, and a control terminal of the switching element connected to the even-numbered row scan electrode A second row scan electrode driving circuit for supplying a row selection pulse to the plurality of pixel electrodes; a common electrode disposed to face the plurality of pixel electrodes; A liquid crystal display device comprising a liquid crystal member held between the first and second row scan electrode driving circuits and a corresponding one of the row scan electrodes. And a gate circuit for controlling an ON period of a row selection pulse supplied to a control terminal of the liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein the first row scan electrode drive circuit turns on the switching elements connected to odd-numbered row scan electrodes for two line periods. The second row scan electrode driving circuit supplies a selection pulse, and sets the switching element connected to the even-numbered row scan electrodes to an on state for two line periods, and outputs the row selection pulse to the first row scan electrode. A gate circuit connected to the odd-numbered row scan electrodes and a gate circuit connected to the even-numbered row scan electrodes are supplied with a phase delay of one line period from the row selection pulse supplied from the electrode drive circuit. By turning on / off alternately for each line period, the ON period of the row selection pulse supplied to the adjacent row scan electrode is only the latter one line cycle. A liquid crystal display device.