JP2002049349A - Method for driving plural pdp modules - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving plural PDP(plasma display panel) modules by which the sum total of the capacity of power sources can be made smaller than heretofore when one set of a power source is used in common for power sources of the plural PDP modules. SOLUTION: At the time of driving plural PDP modules simultaneously by using one set of a common power source, it is controlled so that generation positions of peak currents of respective PDP modules do not overlap each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plurality of PDP modules.

[0002]

2. Description of the Related Art In order to operate a plurality of plasma displays, one plasma display module driving power supply (hereinafter abbreviated as PDP module power supply) is provided for each plasma display module (hereinafter abbreviated as PDP module). Was needed one by one.

[0003]

FIG. 3 shows the waveform of the load current of the PDP module. For example, in an AC type PDP module, a large peak current flows during the sustain period of each subfield. Although the sustain period differs for each subfield, the address period is generally longer than the sustain period, and therefore, here, it is assumed that the cycle Ta during which the peak current flows is constant. That is, FIG. 3 shows that the average current Ia is small, but the large peak current Ip flows every time Ta.

Table 1 shows an example of the load voltage, average current consumption, peak current, and cycle of the peak current of the PDP module.

[0005]

[Table 1]

[0006] As a power supply for a PDP module to cope with such a load current (load capacity), it is not sufficient to simply have an ability to supply an average load current.
Since it is necessary to supply a peak current, it is necessary to increase the power supply capacity.

Assuming that the power supply capacity corresponding to the average current consumption is Wa and the power supply capacity corresponding to the peak current is Wp, the power supply capacity for the PDP module needs to be Wa + Wp.

Here, when a plurality of PDP modules are arranged and displayed like a multi-screen, one PDP module power supply having a large power supply capacity is required for each PDP module.

[0009]

SUMMARY OF THE INVENTION The present invention provides a plurality of P
It is an object of the present invention to provide a method of driving a plurality of PDP modules that can reduce the total power supply capacity as compared with the related art when the power supply of the DP module is shared by one power supply.

[0010]

A plurality of Ps according to the present invention are provided.
When driving a plurality of PDP modules at the same time using one common power supply, the driving method of the DP module is as follows.
The peak current generation positions of the DP module are controlled so that they do not overlap each other. Each PD
The refresh position of each PDP module is controlled so that the peak current generation positions of the P modules do not overlap each other.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a configuration of a signal processing circuit in a case where the power supplies of two PDP modules are shared.

In FIG. 1, reference numeral 100 denotes a signal processing circuit of a first PDP module, and 200 denotes a second PDP module.
This is the signal processing circuit of the module.

Signal processing circuit 1 of first PDP module
The flow of signal processing at 00 will be described. The Y, Pb, Pr (or Y, Cb, Cr) signals input to the input terminals are converted into RGB signals by the matrix converter 101, and then converted into digital data by the AD converter 102.

On the other hand, Y, Pb, P
The r (or Y, Cb, Cr) signal is supplied to the synchronization separation circuit 11
1 and the vertical synchronization signal Vs1 and the horizontal synchronization signal H
s1 is extracted. The vertical synchronization signal Vs1 and the horizontal synchronization signal Hs1 extracted by the synchronization separation circuit 111 are
The signal is sent to the timing generation circuit 112.

The timing generation circuit 112 generates a vertical synchronizing signal W-Vs1 and a horizontal synchronizing signal W-Hs1 which constitute a timing signal for writing to the resolution conversion and frame rate conversion block 103 (Write Timing signal). And a read timing signal (Read Timing) from the frame rate conversion block 103.
Signal) constituting a vertical synchronizing signal R-Vs1 and a horizontal synchronizing signal R-Hs1.

The RGB data converted into digital data by the AD converter 102 is sent to a resolution conversion and frame rate conversion block 103, and is adapted to adapt to the specifications (vertical cycle, horizontal cycle, clock frequency, etc.) of the PDP module. A resolution conversion and a frame rate conversion process are performed. The resolution conversion and frame rate conversion block 103 includes a resolution conversion and frame rate conversion circuit 103a and a frame memory 103b.

The data subjected to resolution conversion and frame rate conversion processing is subjected to error diffusion processing by an error diffusion processing circuit 104,
5 performs subfield processing. The data subjected to these processes is supplied to the driver driving waveform generation circuit 1
06 and a driver drive waveform is generated. The driver driving waveform generated by the driver driving waveform generation circuit 106 is supplied to the driver 107, so that an image is displayed on a plasma display panel (not shown).

Signal processing circuit 2 of second PDP module
Since the flow of signal processing at 00 is the same, description thereof is omitted.

Next, a method of controlling the positions of the peak currents of the two PDP modules will be described with reference to FIG.

The cycle Ta of the peak current depends on the refresh cycle Tb of the PDP module and the number M of subfield divisions, and is expressed by the following equation (1). Here, α is a constant. The refresh cycle Tb depends on the PDP module, and the subfield division number M and the constant α depend on the configuration of the subfield processing circuits 105 and 205.

Ta = Tb / (M + α) (1)

The peak current generation position Tp is determined by the PDP
It depends on the refresh position Tr of the module and is expressed by the following equation (2). Here, β is a constant.

Tp = Tr + β (2)

One PDP module power supply and two PDPs
When operating the DP module, in order to reduce the power supply capacity of the power supply for one PDP module, the position Tp1 of the peak current of the first PDP module and the position Tp2 of the peak current of the second PDP module are required. Is preferably not overlapped.

In order to prevent the peak current position Tp1 of the first PDP module from overlapping with the peak current position Tp2 of the second PDP module, the condition of the following equation (3) may be satisfied. Here, N is an integer.

Tp1 = Tp2 ± Ta (N + ／) (3)

From the above equations (1), (2) and (3), the first
Of the peak current of the PDP module Tp1 and the second
In order to prevent the position Tp2 of the peak current of the PDP module from overlapping, the refresh position Tr1 of the first PDP module and the refresh position Tr2 of the second PDP module satisfy the relationship of the following equation (4). It will be good if it is satisfied.

Tr1 = Tr2 ± Tb (N + ／) / (M + α) (4)

That is, in order that the position Tp1 of the peak current of the first PDP module does not overlap with the position Tp2 of the peak current of the second PDP module, the refresh position Tr of the first PDP module is not changed.
Refresh position Tr of first and second PDP modules
It suffices that there is a difference of Tb (N + 1/2) / (M + α) between the two.

The refresh signal that defines the refresh position Tr1 of the first PDP module has the same period as the vertical synchronization signal R-Vs1 of the Read Timing signal output from the timing generation circuit 112 of FIG. The refresh signal that defines the refresh position Tr2 of the second PDP module has the same period as the vertical synchronization signal R-Vs2 of the Read Timing signal output from the timing generation circuit 212 in FIG.

Therefore, the first PDP module and the second PDP module are
Frame memory 103 in the resolution conversion and frame rate conversion blocks 103 and 203 of the PDP module
b, 203b read timing R-Vs1, R-Vs
The difference ΔTr of 2 may be set to Tb (N + ／) / (M + α).

In the example of FIG. 2, the refresh cycle Tb = 1
/ 60 sec, N = 0, number of subfield divisions M = 1
0, α = 1, and control is performed so that ΔTr = 11/120 sec.

Assuming that the power supply capacity for coping with the average current consumption is Wa and the power supply capacity for coping with the peak current is Wp, one PDP module is shared by two PDP modules.
The capacity required for the DP module power supply is (2Wa + Wp)
And PDPs for two PDP modules separately
This is smaller than the total power supply capacity (2Wa + 2Wp) of the power supplies for the two PDP modules when the module power supplies are provided.

Note that k (k is an integer of 2 or more) PDPs
When the module is operated by one PDP module power supply, the refresh position Trx of the x-th (2 ≦ x ≦ k) PDP module is next to the refresh position Tr1 of the first PDP module. It is set so as to satisfy the relationship of Expression (5).

Trx = Tr1 ± Tb {N + (x−1) / k} / (M + α) (5)

In this case, the capacity required for the power supply for one PDP module common to k PDP modules is k × Wa + Wp. k when power supplies for PDP modules are separately provided for k PDP modules
The total power supply capacity of the PDP module power supplies is k ×
(Wa + Wp).

[0038]

According to the present invention, when the power supplies of a plurality of PDP modules are shared by one power supply, the total power supply capacity can be reduced as compared with the conventional power supply.

[Brief description of the drawings]

FIG. 1 shows a configuration of a signal processing circuit when a common power supply is used for two PDP modules.

FIG. 2 is a time chart for explaining a method of controlling a peak current.

FIG. 3 is a waveform diagram showing a load current of the PDP module.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Signal processing circuit of first PDP module 200 Signal processing circuit of second PDP module 111, 211 Sync separation circuit 112, 212 Timing generation circuit 103, 203 Resolution conversion and frame rate conversion block

Claims (2)

[Claims] When a plurality of PDP modules are simultaneously driven by using one common power supply, peak current generation positions of the PDP modules are controlled so that they do not overlap with each other. Driving method of PDP module. 2. The method of driving a plurality of PDP modules according to claim 1, wherein the refresh positions of the PDP modules are controlled so that the peak current generation positions of the PDP modules do not overlap each other.