JP2001338998A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To realize an inexpensive and high-performance Bi-CMOS process. SOLUTION: A TEOS silicon oxide film 117 is anisotropically etched (RIE) so that a sidewall 119A is left on a side wall of an opening and a MOS is formed.
A spacer 119B is formed at the step between the gate portion of the transistor and the Poly-Si film, and the entire surface is made of Pol.
A y-Si film 120 is deposited. Thereafter, a silicon oxide film 125 is deposited, and patterning is performed to form a low-resistance diffusion layer for taking out an emitter and a MOS source / drain. As + ions are formed in the emitter of the bipolar transistor and the source / drain take-out of the NMOS transistor. Is implanted, and BF2 + ions are implanted into the source / drain extraction portion of the PMOS transistor.
Then, a heat treatment is performed to form emitter and source / drain extraction regions by self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Bi-type transistor in which a high-speed bipolar transistor and a MOS transistor are mixed.
The present invention relates to a semiconductor device having a MOS structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, higher frequencies in various communications,
As the power consumption and digitalization of V devices have evolved, the importance of high frequency / low power consumption analog-digital hybrid ICs has been increasing. In order to realize high frequency and low power consumption of a bipolar transistor, it is necessary to form a shallow emitter-base junction, reduce the base resistance, and reduce the parasitic capacitance. Formation of a low-resistance external base region (graft base) using silicon (Si), formation of a shallow emitter-base (intrinsic base region) junction by impurity diffusion from Poly-Si,
Emitter formation by self-alignment has become mainstream.

A conventional analog-digital mixed IC
Is achieved by a pure bipolar transistor. Further, in order to improve switching speed or to achieve low power consumption, there is an increasing need to use a CMOS for a switch unit. To achieve this, it is necessary to further improve the characteristics of the conventional bipolar transistor and add a CMOS. Bi- combining CMOS with conventional established double polysilicon structure bipolar transistor
In CMOS, it is necessary to add a process required for CMOS while improving bipolar characteristics in a shortest development period.

Further, in order to realize a further shallow junction, it is necessary to reduce the total heat treatment amount, and attention has been paid to high-temperature short-time annealing by a lamp annealing technique. Along with the realization, a reduction in junction leakage current and a reduction in resistance of the impurity diffusion layer by a low-energy ion implantation method have been achieved. However, this lamp annealing step is optimal for shallow junction, but has a problem of deteriorating the gate oxide film. As a result, there is a concern that device degradation (lifetime problem) due to hot carriers may occur.

Next, a Bi-type transistor in which COMS is combined with a conventional bipolar transistor having a double polysilicon structure is used.
A part related to the present invention in the COMS process will be extracted and described with reference to the drawings in accordance with a manufacturing process. First, FIG.
In FIG. 1A, an NPN collector buried layer 2, a PMOS, and an NM are formed on a P-type Si substrate 1 by using a conventional photolithography technique, an ion implantation technique, and an oxidation diffusion technique.
An OS buried layer 3 is formed, and an epitaxial layer 4 is formed using an epitaxial growth technique.
An OCOS layer 5 is formed. After that, the gate oxide film 8 is
10 to 20 nm is deposited by thermal oxidation.
The state of (A) is obtained.

Next, a photoresist (hereinafter referred to as PR)
To form a resist mask, and N-type W
Ion implantation for forming an ELL (FIG. 10B) and for forming a P-type WELL (FIG. 11C) in an NMOS region is performed under predetermined conditions. That is, this combines the formation of the P-type well and the ion implantation for element isolation. Thereafter, the Poly-Si film 9 having a thickness of about 100 to 400 nm is
A phosphorus silicate glass (PSG) 10 having a phosphorus concentration of about 10 to 20 wt% is deposited by CVD (C
chemical Vapor Deposition
After depositing over the entire surface using a technique, a 300 nm oxide film 10 ′ is deposited by CVD to prevent contamination during diffusion,
This phosphorus is diffused into the Poly-Si film 9 (FIG. 11).
(D)).

After that, only the gate region of the N + Poly-Si film 9 is patterned by a PR technique so as to leave a resist, and RIE (Reactive E) is performed.
By using the selection ratio between the Poly-Si film 9 and the gate oxide film 8, etching is performed so as not to penetrate the gate oxide film 8 by using the (tching) technique. Then, N + Poly
After removing portions other than the gate oxide film 8 under the -Si film 9 by wet etching, a buffer film for damage caused by ion implantation and an oxide film 11 for preventing ion channeling are deposited to about 10 to 20 nm (FIG. 12).
(E), ion implantation of the source / drain of the MOS transistor portion using a resist mask (for example, As +,
Energy 50 keV, dose 3.0E15 (1 / cm
² )) (FIG. 12 (F)). Note that the ion implantation into the source / drain is illustrated only in the PMOS portion, but NM
Similarly, N-type ion implantation is performed on the OS portion.

Then, a TEOS oxide film 12 having a thickness of about 100 nm is deposited, and a portion to be an active region of the bipolar transistor is opened by PR and RIE techniques.
Low resistance external base region of N transistor and P + P
The Poly-Si film 14 serving as an Poly-Si resistor is
Deposited on the order of nm and ion-implanted according to the conditions for obtaining a desired resistance value (for example, BF2 +, 40 keV, 2.0E1
5 (1 / cm ² )), patterning by PR, R
Process by IE technology. At this time, a silicon nitride film 13 is provided above the MOS transistor portion (FIGS. 13G and 13H). Then, a 400 nm oxide film 15 is formed.
Is deposited by the CVD method, the opening of the intrinsic base region of NPN is patterned by PR, and the opening is formed by RI.
Etching (silicon oxide film etching and Poly-Si etching) is performed by E (FIG. 14 (I)). Next, a thermal oxide film 16 for preventing channeling during ion implantation is used.
Is deposited on the intrinsic base region by ion implantation (for example, B +, 30 keV, 7.0E12).
(1 / cm ² )) (FIG. 14 (J)).

In the following steps from FIG. 15 and FIG. 16 onward, only the diffusion layer is formed at the ion-implanted portion in the MOS transistor, and the structure does not fluctuate due to the repeated deposition and removal of the film. Illustration is omitted. Then, Si
A TEOS film 17 is deposited to a thickness of about 550 nm by a CVD method of O 2, and poly-Si (B + ion implantation) is
Heat treatment (N2 gas, 900 ° C., 15 ′) is performed to diffuse boron into ngle-Si (Si substrate), that is, to form an intrinsic base and a graft base region of NPN. Thereby, the base region 1 of the NPN transistor
8. The emitter and collector of the LPNP transistor (not shown) and the source and drain of the MOS section are formed (FIG. 1).
5 (K)).

Next, the TEOS silicon oxide film 17 of about 550 nm deposited before diffusion is anisotropically etched (RIE) to leave a silicon oxide film (called a sidewall) 19 on the side wall of the opening. (FIG. 15 (L)), and a Poly-Si film 2 is further formed on the entire surface.
0 is deposited, for example, by about 150 nm by a CVD method or the like. Then, the As + ions forming the emitter are converted to Po
Ion implantation into the ly-Si film 20 (60 keV, 2E16
(1 / cm ² )) (FIG. 16 (M)).
Heat treatment (1050 ° C., 10 seconds) is performed to diffuse into the As + base region injected into the Si film 20, and an emitter region is formed by self-alignment. Thereafter, the PolySi other than the portion where the emitter is taken out is removed (FIG. 16).
(N)).

Thereafter, although not shown, a base extraction electrode, a collector extraction electrode, a source / gate / drain extraction electrode are further formed, and a metal wiring is formed.
Sintering, which is a heat treatment in a forming gas atmosphere composed of% N2 and 5% H2, is performed. Considering the cost performance and the development period, the conventional M
The process to which the OS is added is an existing high-speed bipolar process and a low-speed CM called a single drain structure.
Forming with a combination of OS was effective. The single drain structure has a simple structure itself, and the transistor itself becomes large because the effective gate length in process is determined by the ability of photo phosphorus (controllability of the line width by the resolution of the exposure apparatus). In addition, the hot carrier resistance is L
DD (Lightly Doped Drain) structure and DDD (Double Diffused Drain)
n) There is a disadvantage that the structure is lower than that of the structure. But L
The use of the DD structure increases the number of steps required for forming the LDD, which may increase the cost.

[0012]

As described in the above prior art, considering the cost performance and the development period, the conventional process in which a MOS is added is called an existing high-speed bipolar process or a single drain structure. It has been effective to form a low-speed CMOS combination. However, in order to achieve a high-speed bipolar transistor, it is necessary to obtain a shallow junction. Therefore, the use of a lamp annealing technique is indispensable. However, the use of the lamp annealing technique has a problem that hot carrier resistance is deteriorated. Also, in the single-drain structure, the effective gate length is determined by the ability of photolithography (the controllability of the line width by the resolution of the exposure apparatus), so that the transistor itself becomes large and the hot carrier resistance becomes severe. Power regulation was occurring. The present invention
Bipolar transistor and CMOS realizing the above items
It is an object of the present invention to provide an inexpensive and high-performance Bi-CMOS process incorporating the above-described technology.

An object of the present invention is to provide an inexpensive and high-performance B
It is an object of the present invention to provide a semiconductor device capable of realizing an i-CMOS process and a method for manufacturing the same.

[0014]

According to the present invention, there is provided a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate in a self-aligned manner with a side wall of an emitter opening of the bipolar transistor. And an insulating film formed in a self-aligned manner on the side wall of the gate electrode of the MOS transistor is an insulating film formed by the same process. Further, according to the present invention, in a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, a step of forming an insulating film formed in a self-aligned manner on a side wall of an emitter opening of the bipolar transistor; Forming the self-aligned insulating film on the side wall of the gate electrode of the MOS transistor in the same step. Further, according to the present invention, in a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, an impurity introducing step for forming an emitter of the bipolar transistor and forming a source / drain of the MOS transistor And the impurity introducing step is performed in the same step.

In the semiconductor device according to the present invention, the insulating film formed in a self-aligned manner on the side wall of the emitter opening of the bipolar transistor is a side wall for separating the emitter / base region, and is formed on the side wall of the gate electrode of the MOS transistor. The insulating film formed in conformity is a spacer for the LDD of the MOS transistor. Further, since the same insulating film is used for both the emitter / base separation sidewall of the bipolar transistor and the LDD spacer of the MOS transistor, the function of the high-speed bipolar transistor can be maintained with a minimum increase in the number of steps. By improving the carrier resistance, it is possible to achieve the hybrid mounting of the CMOS which achieves the expansion of the power supply voltage region to be used and the improvement of the degree of integration.

In the method of manufacturing a semiconductor device according to the present invention, the emitter / base separation sidewall of the bipolar transistor and the LDD spacer of the MOS transistor are formed in the same step, and further, the emitter for the bipolar transistor is formed. Impurity introduction step and M
By performing the impurity introduction step for forming the source and drain of the OS transistor in the same step, the number of steps can be reduced, and an inexpensive and high-performance Bi-CMOS process can be realized.

[0017]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below. Figure 1
FIG. 9 is a cross-sectional view showing main steps in a method for manufacturing a semiconductor device in the present embodiment. In the embodiment described below, an example in which an NPN / PNP bipolar transistor and an N-channel MOS transistor are formed on the same substrate will be described.

First, in FIG. 1A, an N + type buried layer 102 is selectively formed on a P type silicon substrate 101.
After the formation of the buried layers 102 and 103, an N-type epitaxial layer 104 having a thickness of about 1.
It is formed with a thickness of 0 μm and a resistivity of about 1.0 Ωcm. afterwards,
Si having a thickness of about 30 nm is formed on the epitaxial layer 104.
O2 film 116 and LP-Si3N4 having a thickness of about 65 nm
Film (ie, Si3N4 by low pressure plasma CVD)
A film 113 is deposited. After that, in FIG.
After forming a resist film on the entire surface, the single element isolation region (L
The resist film corresponding to the formation of the OCOS) is patterned so that the resist film 106 remains only in a portion to be an element formation region. Using the resist film 106 as a mask, L
The P-Si3N4 film 113 and the SiO2 film 116 are removed by etching. Further, by etching 0.45 times the thickness of the epitaxial layer 104 to be oxidized, a shape as shown in FIG. 1B is obtained. In this example, since the oxidation of 800 nm is assumed, the epitaxial layer 104 is etched by about 350 nm.

Thereafter, although omitted in the figure, the resist film 1
06 is peeled off, and a silicon oxide film is deposited by thermal oxidation to a thickness of about 800 nm on a portion opened by etching in FIG. 1B, thereby forming a LOCOS oxide film 107. next,
The silicon nitride film 113 is peeled off with phosphoric acid (hot phosphoric acid) at 150 ° C. Thereafter, in order to form a collector plug of the NPN transistor and a base plug of the PNP transistor, the resist film is patterned, and N-type phosphorus ions are implanted at an energy of, for example, 50 keV and a dose of about 4.5E15 (1 / cm ² ). I do.

After stripping the resist, the implanted phosphorus ions are prevented from diffusing (out diffusion) to the outside of the wafer, and further, the capping is performed to smooth the coverage of the surface of the LOCOS oxide film 107.
g silicon oxide film (eg, TEOS-CVD film) 1
08 is formed to a thickness of 300 nm. Then, heat diffusion (100
0 ° C., 30 ′) to activate the implanted phosphorus ions (FIG. 1C). Further, a resist film 109 or the like is applied to smooth the LOCOS surface. And LOC
The oxide film other than the OS oxide film 107 is removed by wet etching over the entire surface to obtain the state shown in FIG.

Next, as shown in FIG. 2E, a thermal oxide film 109 of about 30 nm is deposited on the entire surface to form a portion corresponding to the formation of an element isolation region (Isoltion), and
The resist film 110 is patterned in the PWELL region of the NMOS. There, implantation conditions for connecting boron ions to the wafer substrate (P-type substrate), for example, 40
It is implanted at 0 keV and 4.0E13 (1 / cm ² ). After that, the resist film 110 is peeled off. That is, in this example, the steps of the element isolation and the PWELL region are simply used. Then, as shown in FIG. 3F, a resist film 111 is formed in the same manner, and the NWE of the PMOS transistor is formed.
Phosphorus ions are implanted into the LL region.

Next, as shown in FIG.
nm silicon oxide film (eg, TEOS SiO
2 CVD film) 112 is deposited. Then, FIG.
As shown in (I), the active region of the NPN transistor and the emitter and collector of the LPNP transistor (not shown) are opened by PR and RIE techniques. Thereafter, a Poly-Si film 114 is deposited on the entire surface by about 150 nm, for example, by a CVD method or the like, and has a predetermined resistance value (ρs
Value) is obtained. Here, in order to form a high resistance and a low resistance, BF in FIG.
2+ (40 keV, 5E14 (1 / cm ² )) ions and B + (15 keV, 2.5E1) in FIG.
5 (1 / cm ² )) ions are implanted.

As shown in FIG. 5 (K), a Poly-Si film 114 is provided for taking out the external base of the NPN transistor.
Patterning using PR to leave a part of
Unnecessary portions are removed by etching using RIE technology. Next, as shown in FIG. 6L, after depositing a silicon oxide film 115 by CVD, the MOS transistor portion is patterned and removed by wet etching, and as shown in FIG. 5 to be an oxide film
A silicon oxide film 131 of about 15 nm is deposited by a thermal oxidation method. Next, as shown in FIG. 7 (N), a Poly-Si film 132 serving as a gate electrode is deposited to a thickness of about 200 to 400 nm by, for example, a CVD method, and as shown in FIG. After patterning, RIE
The Poly-Si film 132 is removed by etching using a method.

Next, the patterned resist film 13
3 is removed, and a TEOS silicon oxide film 121 of about 50 nm is deposited by a CVD method as shown in FIG.
In order to improve the interface state between the silicon film 132 and the silicon oxide film 121, a thermal oxidation process of about 10 nm is performed. Thereafter, to form a diffusion layer for LDD, FIG.
As shown in (R), phosphorus was 100 keV, 4.0E1.
Ion implantation is performed in eight directions at 45 ° in the rotation direction at about 3 / cm ² . Thereafter, as shown in FIG.
A CVD film 117 of SiO 2 of S is deposited to a thickness of about 550 nm, and a Poly-Si film (B + ions are implanted) 11
4 is diffused into Single-Si (Si substrate) 101 by heat treatment (N2 gas, 90) so as to form an intrinsic base and graft base region of NPN.
0 ° C., 15 ′). Thereby, the base region 118 of the NPN transistor and the LDD of the MOS transistor
Source / drain regions 123 and 124 are formed.

Next, in FIG. 9 (T), a TEOS silicon oxide film 117 of about 550 nm deposited before diffusion.
Is anisotropically etched (RIE) to form a spacer 119B so as to leave the sidewall 119A on the side wall of the opening and to form a spacer 119B at the step between the gate portion of the MOS transistor and the Poly-Si film. Further, a Poly-Si film 120 is deposited on the entire surface by, for example, about 150 nm by a CVD method or the like. Thereafter, in FIG. 9 (U), the silicon oxide film 125 is
D is deposited by a method D, and patterning is performed to form a low-resistance diffusion layer for extracting an emitter and MOS source / drain.
A at the source / drain extraction part of the MOS transistor
s + ions are implanted at 60 keV and 2E16 / cm ² ,
B at source / drain extraction part of MOS transistor
F2 + ions are implanted at 60 keV and 5E15 / cm ² . Heat treatment (1050 ° C., 10 seconds) for diffusing As + implanted into the Poly-Si into Si is performed to form the emitter 126 and the source / drain extraction region by self-alignment.

After that, the Poly-Si other than the portion for taking out the emitter and the portion for taking out the source / drain external electrode is removed. Further, the base extraction electrode and the collector extraction electrode are patterned, opened by the RIE method, a metal wiring 127 is formed, and sintering which is a heat treatment in a forming gas atmosphere consisting of 95% N2 and 5% H2 is performed. The state shown in FIG. 9 (U) is obtained. Further, although not shown, the plasma CV is similarly formed on the two-layer wiring after forming the metal wiring (from metal wiring deposition to processing to interlayer film).
An insulating film of about 750 nm is deposited over the entire surface as an overpassivation film by the D method, and the overpassivation film for the bonding pad is etched by the RIE method. Then, the film is formed in an atmosphere of a forming gas composed of 95% N2 and 5% H2. Sintering, which is a heat treatment, is performed to complete the semiconductor device.

In the semiconductor device and the method of manufacturing the same according to the present embodiment, the following effects can be obtained. First, since the LDD spacer in the MOS portion and the sidewall for separating the emitter and the base in the bipolar portion are shared, the hot carrier resistance is improved as compared with the MOS having the single drain structure formed in the same number of steps. , The LDD structure can achieve a high degree of integration. In addition, the power supply voltage used increases in the direction of higher power due to the improvement of the hot carrier resistance described above.
The range of use has expanded. In other words, it is possible to cope with a high power supply.

Further, the side wall of the bipolar portion and the M
The number of steps can be reduced as compared with the case where the LDD spacers of the OS portion are individually formed. Also, by forming the sidewalls of the bipolar portion and the spacers for the LDD of the MOS portion in the same process, the polycrystalline film of the emitter portion of the NPN transistor and the extraction electrode of the source / drain of the NMOS can be shared, thereby reducing the number of processes. Connect. In the above, the combination of NPN and NMOS has been described, but the same can be applied to the combination of PNP and PMOS.

[0029]

As described above, the semiconductor device according to the present invention is a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate.
An insulating film formed in a self-aligning manner on the side wall of the emitter opening of the bipolar transistor and an insulating film formed in a self-aligning manner on the side wall of the gate electrode of the MOS transistor by the same process. It is characterized by. Therefore, in the semiconductor device according to the present invention, the function of the high-speed bipolar transistor can be achieved with a minimum increase in the number of steps by using the same insulating film as the side wall for separating the emitter and base of the bipolar transistor and the LDD spacer of the MOS transistor. By maintaining the hot carrier resistance, there is an effect that it is possible to achieve the hybrid mounting of the CMOS which achieves the expansion of the used power supply voltage region and the improvement of the high integration.

According to a method of manufacturing a semiconductor device according to the present invention, the bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, and the semiconductor device is formed in a self-aligned manner on the side wall of the emitter opening of the bipolar transistor. Forming an insulating film,
The step of forming the self-aligned insulating film on the side wall of the gate electrode of the OS transistor is performed in the same step. Therefore, in the method of manufacturing a semiconductor device according to the present invention, by forming the emitter / base separation sidewall of the bipolar transistor and the LDD spacer of the MOS transistor in the same step, the man-hour can be reduced, and the inexpensive and high-performance Bi -A CMOS process can be realized.

Further, according to the method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, wherein an impurity introducing step for forming an emitter of the bipolar transistor is performed. Transistor source
It is characterized in that the impurity introduction step of forming the drain is performed in the same step. Therefore, in the method of manufacturing a semiconductor device according to the present invention, the step of introducing an impurity for forming the emitter of a bipolar transistor and the step of introducing an impurity for forming the source and drain of a MOS transistor are performed in the same step. And an inexpensive and high-performance Bi-CMOS process can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a step of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 11 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 12 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 13 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 14 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 15 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

FIG. 16 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

[Explanation of symbols]

101 ... P-type silicon substrate, 102, 103 ... Buried layer, 104 ... Epitaxial layer, 107 ... LO
COS oxide film, 109 thermal oxide film, 113 silicon nitride film, 114, 120, 132 Poly-Si
Membrane, 116, 108, 112, 115, 117, 12
1, 122, 131 ... silicon oxide film, 119A ...
Side wall, 119B ... spacer.

Claims (8)

[Claims] 1. A semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, an insulating film formed in a self-aligned manner on a side wall of an emitter opening of the bipolar transistor, and a gate electrode of the MOS transistor. Wherein the insulating film formed in a self-aligned manner on the side wall of the semiconductor device is an insulating film formed by the same process. 2. The semiconductor device according to claim 1, wherein a silicon oxide film is used as said insulating film. 3. A method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, wherein a step of forming an insulating film formed in a self-aligned manner on a side wall of an emitter opening of the bipolar transistor. Forming a self-aligned insulating film on the side wall of the gate electrode of the MOS transistor in the same step. 4. The method according to claim 3, wherein a silicon oxide film is used as the insulating film. 5. A method for manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, wherein: an impurity introducing step for forming an emitter of the bipolar transistor; and forming a source / drain of the MOS transistor. A method of manufacturing a semiconductor device, wherein the step of introducing an impurity is performed in the same step. 6. The method according to claim 5, wherein the impurity introducing step is performed by diffusion from a polycrystalline film. 7. The bipolar transistor is an NPN transistor, and the MOS transistor is an NMOS transistor.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the method is a transistor. 8. The bipolar transistor is a PNP transistor, and the MOS transistor is a PMOS transistor.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the method is a transistor.