JP2001333034A - Device for demodulating multiplexed signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplexed signal demodulating device which maintains satisfactory separation even though a digital detected signal is reduced. SOLUTION: An FM multiplex demodulating device having a pilot signal extracting means for extracting a pilot signal of 19 kHz from the digital detected signal, a reference signal generating means for generating a reference signal from the extracted pilot signal of 19 kHz, an audio processing means for performing audio processing of the detected signal, a demodulating means for multiplexing the output from the audio processing means by the reference signal and demodulating the multiplexed signal, and a stereo demodulating means for obtaining a stereo signal from the output signal from the audio processing means and the output signal from the demodulating means is provided with a decimation filter for reducing the data speed of the detected signal and an interpolation filter for increasing the data speed of the outputs of the pilot signal extracting means and the audio processing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplexing demodulator such as an FM multiplex demodulator for demodulating an (LR) signal multiplexed on a reference (L + R) signal to obtain an L signal and an R signal. The present invention relates to a multiplexed signal demodulator that demodulates a multiplexed signal included in a multiplexed detection signal.

[0002]

2. Description of the Related Art As a conventional example of a multiplex signal demodulator, a conventional FM multiplex demodulator will be described with reference to FIG. FIG.
, 1 is an analog-to-digital converter (A / D) that converts a received FM reception signal into a digital signal, 2 is an FM detector that performs FM detection on the digital signal output from the A / D 1, and 3 is an FM detection A decimation filter for reducing the data rate of the digital signal FM-detected by the demodulator 2, and an audio processing unit (ARC: Auto Recepti) 4 for controlling frequency characteristics, amplitude and the like according to the received electric field strength.
on Controller), 5 is a 19KHz band-pass filter (BPF) for extracting a 19KHz pilot signal contained in the signal detected by FM detection, and 20 is a 19KHzP for generating a signal synchronized with the 19KHz signal extracted from the 19KHz BPF5.
LL, 21 is a 38 KHz generator for generating a carrier signal of 38 KHz from the generated 19 KHz, and 22 is a 3 KHz generator.
A demodulator that demodulates a multiplexed (LR) signal by multiplying 8 KHz by the output signal of the ARC 4, 13 is an adder,
14 is a subtractor, 6 and 7 are interpolation filters for increasing the data rate of digital signals, 15 and 1
6 is a digital-to-analog converter.

In an FM stereo broadcast, a baseband band FM-detected by the FM detector 2 has a (L + R) signal as a 19 KHz pilot signal and (LR) as shown in FIG. The signal is multiplexed. The multiplexed 19 KHz pilot signal is 19 KHz BP
The carrier signal of 38 KHz is extracted by the F5 and reproduced by the 38 KHz generator.

When the reproduced carrier signal is multiplied by the output signal from the ARC 4 by the multiplier 22, the multiplexed (LR) signal is demodulated as shown in FIG. Is done. In the adder 13, (L + R)
The signal and the (LR) signal are added to obtain an L signal of 2L, and the subtractor 14 subtracts the (LR) signal from the (L + R) signal.
The signal is subtracted to obtain an R signal of 2R, and the stereo signal is demodulated.

In order to perform FM detection on a received signal by digital processing, it is necessary to use data sampled at a high frequency of, for example, 11.4 MHz. However, the ARC 4, the 19 KHz BPF 5, and the demodulator 22 after FM detection do not need to process with such high-speed data.
By processing at such a high speed, a processor that performs digital signal processing must operate at a high speed.

For this reason, the decimation filter 3
In order to reduce the data output at a data rate of 11.4 MHz output from the M detector 2 to a data rate of, for example, 228 KHz, the data is thinned out and the ARC4,
The 19 KHz BPF 5, the 38 KHz generator 21, the demodulator 22 and the like are operated at a low speed.

The decimation filter 3 is 228 KHz, which is 12 times the 19 KHz pilot signal shown in FIG.
Down-sampling is performed with the clock.

The 228 KHz of this clock is asynchronous with the 19 KHz pilot signal, and is completely 19 KHz ×
It does not match the frequency of 12 times. Therefore, jitter is generated in the 19 KHz pilot signal of the data output from the decimation filter 3.

That is, when FIG. 7A is a 19KHz pilot signal (actually a sine wave but shown as a rectangular wave) included in the signal output from the FM detector 2, it is shown in FIG. 7B. As described above, when the clock of the decimation filter 3 is synchronized with the 19 KHz pilot signal shown in FIG. 7A, the 19 KHz pilot signal included in the signal reduced by the decimation filter 3 is shown in FIG.
As shown in FIG. 7C, no jitter occurs, corresponding to FIG. 7A.

However, when the clock frequency of the decimation filter 3 is different from 228 KHz, which is 19 KHz × 12 times, the sampling position is as shown in FIG. 7D, and the 19 KHz pilot signal sampled at such a clock frequency is shown in FIG. e), a phase shift occurs, and α
Jitter occurs.

This phase shift is not fixed, but is 1
Since the phase of the clock signal of 228 KHz + Δf changes with time with respect to the 9 KHz pilot signal, a phase shift of the 19 KHz pilot signal occurs as shown in FIG.

When the 19 KHz pilot signal has a phase shift, that is, jitter occurs, the R signal and the L signal output from the adder 13 and the subtractor 14 include the L component and the R component, respectively. The separation of the R signal and the L signal is deteriorated, and the stereo feeling is deteriorated.

[0013] That is, multiplexed shown in FIG. 6 (A) (L-R ) _{signal, Acos (2πf s t) cos} (2πf c t) = A {cos 2π (f s -f c) t + cos 2π (f _s + f _c)} However, a: is represented by the multiplexed carrier frequency (38KHz) ... (1): (L-R) signal amplitude f _s: (L-R) signal of frequency f _c .

[0014] The multiplexed (L-
To R) signal, is multiplied by entering a carrier signal of 38 KHz (f _c) generated from the pilot signal of 19KHz generated jitter described above _{cos (2πf s t + α)} ... (2) to the demodulator 7, demodulates the _{output, A {cos 2π (f s} -f c) t + cos 2π (f s + f c) t} × cos (2πf s t + α) = A {cos (2πf s t + α) + cos (2πf s t-α)} = A cos (α) cos 2πf _s st (3)

That is, the demodulated output has its amplitude A multiplied by cos (α) as shown in equation (3).
Since α changes as described above, the demodulated (L−
R) The amplitude of the signal also changes.

Therefore, the output of the adder 13 is (L + R) + cos α (LR) = (1 + cos α) L + (1-cos α) R (4), and the output of the subtractor 14 is L + R) -cos α (LR) = (1−cos α) L + (1 + cos α) R (5), and the separation is degraded, and the degradation of the separation fluctuates.

For this reason, conventionally, as shown in FIG. 5, a 19 kHz PLL 20 synchronizing with a 19 kHz pilot signal output from the 19 kHz BPF 5 is provided.
The carrier signal is generated by the 38 KHz generator 21 based on the 19 KHz signal reproduced by the Hz PLL 20, and the device configuration is complicated.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiplexed signal demodulator which maintains a good separation even if the digitized detection signal is reduced.

[0019]

According to the first aspect of the present invention, there is provided a pilot signal extracting means for extracting a pilot signal having a single frequency from a digitized detection signal, and a reference signal is generated from the extracted pilot signal. A multiplexed signal, comprising: a reference signal generating unit that performs signal processing on the detected signal; and a demodulating unit that demodulates a multiplexed signal by multiplying an output from the signal processing unit by the reference signal. In the demodulation device, a low-speed filter for reducing the data rate of the detection signal and a high-speed filter for increasing the data rate are provided at the outputs of the pilot signal extracting means and the signal processing means.

According to a second aspect of the present invention, the reference signal generating means includes a first phase shifting means for shifting the phase of the extracted pilot signal by 90 degrees, an output of the first phase shifting means and the extracted pilot signal. First logic means for obtaining an exclusive OR of signals, second phase shift means for shifting an output signal from the first logic means by 90 degrees, output of the first logic means and output of the second phase shift means A second logical means for obtaining an exclusive OR of the second logical means, an inverting means for inverting an output of the second logical means, a third phase shifting means for shifting an output signal from the inverting means by 90 degrees, and Third logic means for obtaining an exclusive OR of the output of the phase shift means and the output of the first logic means, and a first means for multiplying the output of the first logic means and the output signal of the signal processing means.
Multiplying means; second multiplying means for multiplying the output of the third logic means and the output signal of the signal processing means; third multiplying means for multiplying the output of the second multiplying means by √2-1;
A first operation for adding the output of the multiplication means and the output of the third multiplication means
It comprises an adding means, a second adding means for adding the output signal of the signal processing means and the output of the first adding means, and a subtracting means for subtracting the output of the first adding means from the output signal of the signal processing means. .

According to a third aspect of the present invention, the multiplication by the third multiplication means is multiplied by 2 ^-1 instead of √2-1.

According to a fourth aspect of the present invention, when the output from the first logic means is "1", the first multiplying means passes the output signal of the signal processing means, and outputs "0".
When the output from the first logic means is "0", the signal processing means output signal is inverted, or when the output is "1", the signal processing means output signal is passed. Invert the output signal.

According to a fifth aspect of the present invention, when the output from the third logic means is "1", the second multiplying means passes the signal processing means output signal and outputs "0".
In this case, the signal processing means output signal is inverted, or when the output from the third logic means is "0", the signal processing means output signal is passed and output, and when the output is "1", the signal processing means is output. Invert the output signal.

According to a sixth aspect of the present invention, the single frequency of the pilot signal is 19 KHz, and the signal processing means is constituted by audio processing means for performing audio processing on the detected signal.

[0025]

1 to 4 show an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a configuration diagram of an embodiment of the present invention,
FIG. 2 is a specific example of the decimation filter of the embodiment, FIG. 3 is a configuration diagram of the approximate sine wave source generator of the embodiment, and FIG. 4 is a time chart of the approximate sine wave source generator.

In FIG. 1, 1 is an A / D, 2 is an FM detector, 3 is a decimation filter, 4 is an ARC, and 5 is 1
9 KHz BPF, 6 and 7 are interpolation filters, 8 is an approximate sine wave source generator, 9, 10, and 11 are multipliers, 12 and 13 are adders, 14 is a subtractor, and 15 and 16 are D / A.

The decimation filter 3 reduces the digital data output from the FM detector 2 at a data rate of 11.4 MHz to a data rate of 228 KHz, as in the conventional example. A specific example is shown in FIG.

In FIG. 2, reference numeral 31 denotes N stages (31A to 31).
N) is a shift register for recording digital data output from the FM detector 2 to 11.4 MHz.
To shift. 32 is a coefficient multiplier, which is a shift register 3
The data value recorded in each stage (31A to 31N) is multiplied by a coefficient K and output.

An adder 33 adds N data values output from the coefficient multiplier 32. 34 is a sampler,
The output added by the adder 32 is read and output in synchronization with a sampling pulse of 228 KHz.

The interpolation filters 6 and 7 have the same configuration. Digital data is input at a data rate of 228 KHz, read at a sampling pulse of 5.7 MHz, and the digital data is increased to a data rate of 5.7 MHz. .

FIG. 3 shows a configuration example of the approximate sine wave source generator 8.
Shown in In FIG. 3, 81 is a 90-degree phase shifter, and 82 is X
OR, 83 is a 90-degree phase shifter, 84 is an XOR, 85 is an inverter, 86 is a 90-degree phase shifter, and 87 is an XOR. When the signal of 19 KHz shown in FIG. 4A is input to the approximate sine wave source generator 8, the output of the 90-degree phase shifter 81 is shown in FIG.
Is output, and a signal shown in FIG. 4C is output to the output of the XOR 82.

The output of the 90-degree phase shifter 83 is shown in FIG.
(D) is output, and the output of XOR 84 is
(E) is output. When the output of the XOR 84 is inverted by the inverter 85 and the phase is shifted by the 90-degree phase shifter 86, a signal shown in FIG. XOR at XOR87
The exclusive OR of the output of 82 and the 90-degree phase shifter 86 is obtained, and the signal shown in FIG.

The output of the XOR 82 of the approximate sine wave source generator 8 and the signal subjected to the FM detection are multiplied by a multiplier 9. That is, when the output of the XOR 82 is “1”, the signal subjected to the FM detection is passed, and when the output of the XOR 82 is “0”, the FM
Invert the detected signal. When the output of XOR 82 is "0", the signal detected by FM detection is passed and
When the output of 82 is "1", the signal detected by FM detection may be inverted.

The output of the XOR 87 of the approximate sine wave source generator 8 and the signal subjected to the FM detection are multiplied by the multiplier 10 and then multiplied by 2 ^0.5 -1 by the multiplier 11. That is, X
When the output of the OR 87 is "1", the signal subjected to the FM detection is passed, and when the output of the XOR 87 is "0", the signal subjected to the FM detection is inverted. Then, the multiplier 11 multiplies the signal by 2 ^0.5 -1. Is done. Incidentally, when the output of XOR87 is "0" is passed through the signal FM detection, inverts the signal FM detection when the output of XOR87 is "1", followed by the multiplier 5 by 2 ^0.5 -1 May be multiplied.

The output of the multiplier 9 is added to the output of the multiplier 11 by the adder 12, output to the adder 13 and the subtractor 14, added to the signal detected by the FM in the adder 13, and
The signal is subtracted from the signal detected by the FM in the subtractor 14 to demodulate the R signal.

Signals shown in FIGS. 4C and 4G are output from the approximate sine wave source generator 8, and the multiplier 11 outputs 2 ^0.5 −
By multiplying by 1 and adding by the adder 12, an approximate sine wave of 38 KHz shown in FIG.

In this embodiment, since the output of the XOR 82 and the output of the XOR 87 are 1 bit representing "1" or "0", the 1 bit and the FM detected signal are multiplied by multipliers 9 and 10, respectively. The multiplication result is added by the adder 12.

For this reason, the multiplication can be performed by two of the multipliers 9 and 10, which perform multiplication of n × 1 bits, and the multiplication can be easily performed. The multipliers 9 and 10 pass the FM detection signal when the output of the approximate sine wave source generator 8 is "1" (or "0"), and the FM detection signal when the output is "0" (or "1"). You may comprise so that a signal may be inverted.

Further had so as to multiply the multiplier 11, √2-1, it may be caused to approximate by multiplying 2 ^-1 instead of √2-1. By doing so, the multiplier 11 can perform the multiplication by shifting the digital value output from the multiplier 10 by one bit. ^{Further, √2-1 ≒ 2 -1 -2 -4 -2} -6 -2
^It is also possible to adopt a configuration in which powers of 2 are combined and approximated, such as ^-7 .

In this embodiment, the data rate of digital data is controlled by the decimation filter 3.
ARC4 and 19 were reduced from 4 MHz to 228 KHz.
The KHz BPF is operated, and the data rates are then increased from 228 KHz to 5.7 MHz by interpolation filters 6 and 7.

The data rate is not limited to this embodiment, but may be any value as long as the value is close to an integral multiple of 19 KHz. In the present embodiment, the audio processing unit is described as an example of the signal processing unit. However, the present invention is not limited to this. For example, a data extraction unit that extracts data from a detected signal can reduce the data rate. Any signal processing means that can reduce the scale may be used. Further, in the present embodiment, a decimation filter is described as an example of the low-speed filter, but the present invention is not limited to this, and may be anything that can reduce the data rate. Similarly, in this embodiment, an interpolation filter is described as an example of a high-speed filter. However, the present invention is not limited to this, and may be anything that can increase the data rate.

As described above, by increasing the data rate in front of the multipliers 9, 10 and 11, the jitter caused by reducing the data rate by the decimation filter 3 is reduced by increasing the data rate.

[0043]

As described above, according to the present invention,
Since the data rate is appropriately changed according to the circuit, it is possible to provide a multiplexed signal demodulation apparatus capable of preventing an increase in circuit scale due to high-speed processing and occurrence of jitter caused by low-speed processing.

In particular, the multiplexed signal demodulation device of the present invention demodulates the (L-R) signal multiplexed into the (L + R) signal included in the FM detected signal to demodulate the L signal and the R signal.
A pilot signal extracting means for extracting a 19 KHz pilot signal from the digitized detection signal; a reference signal generating means for generating a reference signal from the extracted 19 KHz pilot signal;
Audio processing means for performing audio processing on the detected signal, demodulation means for multiplying an output from the audio processing means and the reference signal to demodulate a multiplexed signal,
The following effects can be obtained when a stereo demodulation unit for obtaining a stereo signal from the output signal from the audio processing unit and the output signal from the demodulation unit is provided.

That is, the data rate of the FM-detected digital signal is reduced by a decimation filter and output to the audio processing means and the 19 KHz pilot signal extracting means. The data rate is output to the audio processing means and the pilot extracting means. Since an interpolation filter for increasing the data rate is inserted, even if the data rate is reduced by the decimation filter and jitter occurs, the data rate is increased by the interpolation filter, so that the jitter can be reduced. Therefore, it is possible to provide an FM multiplex demodulator capable of maintaining a good separation even when the digital signal subjected to the FM detection is operated at a reduced data rate.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a specific example of a decimation filter of the embodiment.

FIG. 3 is a configuration diagram of an approximate sine wave source generator of the embodiment.

FIG. 4 is a time chart of the approximate sine wave source generator of the embodiment.

FIG. 5 is a configuration diagram of a conventional example.

FIG. 6 is a diagram illustrating demodulation of FM stereo broadcast.

FIG. 7 is a diagram for explaining jitter generated by data thinning of an FM detection output.

[Explanation of symbols]

1 Analog-to-digital converter (A /
D) 2 FM detector 3 Decimation filter 4 Audio processing unit (ARC) 5 19 KHz band pass filter (BPF) 6, 7 Interpolation filter 8 Approximate sine wave source generator 9, 10, 11 Multiplier 12, 13 Adder 14 Subtractor 81, 83, 86 90-degree phase shifter 82, 84, 87 Exclusive OR (XOR) circuit 85 Inverter

Claims (6)

[Claims] 1. A pilot signal extracting means for extracting a pilot signal having a single frequency from a digitized detection signal, a reference signal generating means for generating a reference signal from the extracted pilot signal, A multiplexed signal demodulation device comprising: a signal processing unit for processing; and a demodulation unit for multiplying an output from the signal processing unit by the reference signal to demodulate a multiplexed signal. A slow filter to
A multiplexed signal demodulation device, comprising: a high-speed filter for increasing a data rate at the output of the pilot signal extracting means and the signal processing means. A first phase shifter for shifting the phase of the extracted pilot signal by 90 degrees; an exclusive OR of an output of the first phase shifter and the extracted pilot signal; And first and second means for shifting the phase of the output signal from the first logic means by 90 degrees.
Phase shifting means; second logic means for obtaining an exclusive OR of the output of the first logic means and the output of the second phase shifting means; inverting means for inverting the output of the second logic means; Third phase shifting means for shifting the phase of the output signal by 90 degrees, third logic means for calculating an exclusive OR of the output of the third phase shifting means and the output of the first logic means, and the output of the first logic means. First multiplying means for multiplying the output signal of the signal processing means; second multiplying means for multiplying the output signal of the third logic means and the output signal of the signal processing means; Third multiplying means for multiplying by 1, first adding means for adding the first multiplying means output and the third multiplying means output, and adding the signal processing means output signal and the first adding means output. Second adding means, and the signal processing means 2. A multiplexed signal demodulating apparatus according to claim 1, wherein said multiplexing signal demodulating means comprises a subtracting means for subtracting an output of said one adding means. 3. The multiplication by the third multiplication means is represented by √2-1
3. The multiplexed signal demodulator according to claim 2, wherein 2 ^-1 is multiplied instead of. 4. The first multiplying means passes the signal processing means output signal when the output from the first logic means is "1", and outputs the signal processing means output signal when the output is "0". Or when the output from the first logic means is "0", the signal processing means output signal is passed and output, and when the output is "1", the signal processing means output signal is inverted. 4. The multiplexed signal demodulation device according to claim 2, wherein: 5. The second multiplying means passes the signal processing means output signal when the output from the third logic means is "1", and outputs the signal processing means output signal when the output is "0". Or when the output from the third logic means is "0", the signal processing means output signal is passed and output, and when the output is "1", the signal processing means output signal is inverted. 4. The method according to claim 2, wherein:
Or the multiplexed signal demodulator according to 4. 6. The single frequency of the pilot signal is 19
6. The multiplexed signal demodulator according to claim 1, wherein the frequency is set to KHz and the signal processing means is constituted by audio processing means for performing audio processing on the detected signal.