JP2001326289A - Nonvolatile memory and semiconductor device - Google Patents

Abstract

(57) [Summary] (Modified) [PROBLEMS] To provide a non-volatile memory capable of low power supply voltage and low power consumption, a non-volatile memory capable of high / multifunctionalization and miniaturization, and a non-volatile memory Provided is a semiconductor device having the same. SOLUTION: The nonvolatile memory is a completely depleted memory T.
It is composed of a memory cell array composed of FT (thin film transistor), a driving circuit of the memory cell, and other peripheral circuits, which are integrally formed on the same substrate. Further, a pixel portion, a driver circuit for driving the pixel portion, and a nonvolatile memory included in the semiconductor device are formed over a substrate having an insulating surface. By using a fully-depleted memory TFT, the power supply voltage and power consumption of the nonvolatile memory can be reduced.
The number of rewrites can be improved. By integrally forming with a circuit and a semiconductor component constituted by a TFT, a nonvolatile memory and a semiconductor device with high / multifunctionality and miniaturization can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to SOI (Silicon).
The present invention relates to a semiconductor non-volatile memory including thin film transistors (hereinafter, referred to as TFTs) formed by using an On Insulator technique. In particular, an electrically writable and erasable semiconductor non-volatile memory (hereinafter referred to as an EEPROM or an electrically erasable and programmable read only) integrally formed on the same substrate together with a peripheral circuit including its driving circuit.
Memory). Further, the present invention relates to a semiconductor device in which a pixel portion including a TFT, a driving circuit for driving the pixel portion, and a nonvolatile memory are formed over the same substrate.

In the specification of the present application, an electrically writable and erasable semiconductor nonvolatile memory (EEPRO)
M) literally refers to the entirety of an electrically rewritable and electrically erasable semiconductor nonvolatile memory, and includes, for example, a flash memory in its category. Further, when simply referred to as a nonvolatile memory or a semiconductor nonvolatile memory, it refers to an EEPROM unless otherwise specified. In addition,
In this specification, a thin film transistor (TFT) refers to an entire transistor formed using an SOI technique, and includes a memory element (hereinafter, referred to as a memory TFT) formed using an SOI technique in its category. Of course, even if it is formed on a substrate having an insulating surface, SO
It may be formed on an I substrate. Also,
In this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes, for example, an electro-optical device represented by a liquid crystal display device and an EL display device, and an electronic device including the electro-optical device. Included in that category.

[0003]

2. Description of the Related Art In recent years, as semiconductor devices have rapidly become multifunctional, highly functional, and miniaturized, memories have become increasingly important in semiconductor devices.

[0004] For example, a magnetic disk is one of the most frequently used storage devices at present, including an external storage device of a computer because of its large storage capacity and non-volatility. However, with the rapid spread of portable devices such as portable computers and mobile phones, the problems with magnetic disks, especially those that are difficult to reduce in size, are susceptible to vibration, and consume large amounts of power, have become more serious. I have.

[0005] A semiconductor non-volatile memory (especially EEP) has attracted attention as a memory that overcomes these disadvantages.
ROM). Semiconductor nonvolatile memory is nonvolatile like a magnetic disk, but instead of using magnetism,
It is manufactured using a semiconductor (mainly, bulk silicon), and electrically performs reading, writing, and erasing. Semiconductor non-volatile memories have a higher degree of integration, are more resistant to impacts, and consume less power than magnetic disks. The writing / reading speed is several tens of times faster than that of a magnetic disk. Previously, problems related to the number of times of rewriting and data retention time were pointed out, but recently those having sufficient performance have been developed.

In particular, in a semiconductor nonvolatile memory for performing flash-type erasing (referred to as a flash memory), a higher degree of integration is realized, and the semiconductor nonvolatile memory is currently the mainstream. The flash type erasing refers to erasing the entire memory at once or erasing the memory in block units.

[0007] Against this background, there has been an increasing trend in recent years to use semiconductor non-volatile memories as substitutes for magnetic disks. And development and commercialization in various fields are already in progress. One example is a memory card (also called a memory stick). Memory cards that do not require much storage capacity are areas where the advantages of semiconductor non-volatile memory are most utilized, and are expected to rapidly spread in the future as storage media for storing music, videos, maps, electronic books, and the like. You. On the other hand, a memory specialized for a system is also being developed. For example, a semiconductor nonvolatile memory is already used as a part of a memory in a computer or as a storage memory of a printer, a communication device, or the like.

Here, the sectional structure and operation principle of a typical memory element used in a conventional semiconductor nonvolatile memory will be briefly described. FIG. 3 shows a schematic sectional structure of the memory element. 3, a memory element 301 is formed on a p-type bulk silicon substrate 302, and has a first gate insulating film 305, a floating gate electrode 306, a second gate insulating film 307, and a control gate electrode 30.
8 are sequentially laminated. In the vicinity of the surface of the silicon substrate, source / drain regions (high concentration n
(Type impurity regions) 303 and 304 are formed.

The memory element realizes a memory function by injecting and discharging charges (mainly electrons) to and from the floating gate electrode. That is, 1-bit data is stored by utilizing the difference in threshold voltage between when charge is accumulated in the floating gate electrode and when charge is not accumulated. For writing data in a memory element, for example, a positive high voltage is applied between a drain and a source and between a control gate electrode and a source, and hot carriers (mainly hot electrons) generated by impact ionization are injected into a floating gate electrode. Done by
For erasing data from the memory element, for example, a negative high voltage is applied between the control gate electrode and the source, and electrons accumulated in the floating gate electrode by a tunnel current (FN current, Fowler-Nordheim current) are transferred to the source region. Perform by releasing.

[0010]

As described above, the non-volatile memory has been developed and commercialized in many fields, and has attracted attention as a substitute for a magnetic disk. However, on the other hand, there are many problems unique to nonvolatile memories and demands for memories.

First, as a problem peculiar to the nonvolatile memory,
Lower power supply voltage is an example. As described above, the non-volatile memory requires a high voltage at the time of writing and erasing. Therefore, if a non-volatile memory is to be incorporated into a system, a new high-voltage power supply is required, which hinders miniaturization and cost reduction of the device. Also, from the viewpoint of compatibility with other recording media and the like, reducing the power supply voltage of the nonvolatile memory is an important issue.

[0012] In addition, in application to portable equipment, miniaturization and reduction of power consumption of a nonvolatile memory and a semiconductor device having the nonvolatile memory are also important issues. Means for downsizing include miniaturization and multi-valued memory elements. On the other hand, conventional non-volatile memories are housed in packages, and miniaturization of semiconductor devices provided with the non-volatile memories. Had trouble.

The present invention has been made in view of the above circumstances. It is an object of the present invention to provide a small-sized non-volatile memory which has a low power supply voltage and low power consumption, is multifunctional or highly functional, and has a non-volatile memory. .

[0014]

According to the present invention, a nonvolatile memory is replaced with a substrate having an insulating surface or an SOI (Silicon).
n On Insulator) It is configured using a memory TFT formed on a substrate. Further, according to the present invention, as a means for reducing a large current flowing at the time of writing and erasing, which is a factor that hinders a reduction in power supply voltage and power consumption, a nonvolatile memory is configured using a completely depleted memory TFT.

In this specification, a fully depleted T
An FT (including a memory TFT) is a TFT in which the thickness of a semiconductor active layer is smaller than the thickness of a depletion layer formed in a channel region.
Refers to FT. The semiconductor active layer of a fully depleted TFT typically has a film thickness of １ ／ or less of the channel length. Therefore, in the present invention, it may be said that the nonvolatile memory is constituted by a memory TFT whose semiconductor active layer has a thickness of 1 nm or more and a channel length of 1/4 or less. Also,
The thickness of the semiconductor active layer is preferably 1 nm to 50 nm in order to bring out the characteristics of a fully depleted TFT described later more remarkably.

According to the present invention, the non-volatile memory is replaced with TF
It can be formed integrally with any circuit constituted by T. In particular, by integrally forming a memory cell driver circuit (typically, an address decoder) and other peripheral circuits, a nonvolatile memory smaller than a conventional memory can be provided. Further, in a semiconductor device having a pixel portion constituted by a TFT and a driving circuit for driving the pixel portion, a nonvolatile memory is newly formed as a memory portion and incorporated in the system,
It is possible to provide a multifunctional or high-functional and small semiconductor device.

A fully depleted memory TFT has many superior features as compared with a memory element on bulk silicon or a memory element having a semiconductor active layer thicker than a depletion layer.

First, at the time of writing, the memory TF
Impact ionization (impa) due to the thin semiconductor active layer of T
Ct ionization, impact ionization, or impact ionization) easily occur, and writing by hot carrier injection can be performed with a lower voltage and a smaller current.

At the time of erasing, there has conventionally been a problem that the current increases due to the interband tunnel current. This is because, in the case of bulk silicon, since the potential of the substrate is fixed, a high potential difference occurs between the substrate and the source or drain. However, in a fully-depleted memory TFT, the electric field applied between the source or drain region and the channel formation region is reduced because the semiconductor active layer is not given a fixed potential unlike bulk silicon. As a result, the band-to-band tunnel current is reduced, and the current flowing during erasure is reduced.

As described above, the power consumption is reduced by reducing the current at the time of writing and erasing. Also,
By reducing the current load and the voltage drop, the boosting by the boosting circuit is facilitated, and the power supply voltage can be reduced.
Further, the reduction in the current at the time of writing and erasing leads to an increase in the number of times of rewriting, and an improvement in the reliability of the nonvolatile memory.

A fully depleted memory TFT is characterized in that the junction capacitance and the depletion layer capacitance are small. When the junction capacitance is small, power consumption is reduced. Further, on / off of the current flowing through the memory element is increased. That is, the writing and reading speed by hot carrier injection is improved.
On the other hand, if the capacitance of the depletion layer is small, good subthreshold characteristics can be obtained. As a result, the change in threshold voltage due to writing / erasing is effectively increased, and operation at a lower voltage becomes possible.

In the nonvolatile memory of the present invention, the TFT constituting the memory cell drive circuit and other peripheral circuits formed integrally with the memory cell is made completely depleted, and in the semiconductor device of the present invention, It is effective to use a completely depleted TFT in a pixel portion formed integrally with a memory portion and a TFT forming a driver circuit for driving the pixel portion. As a result, it is possible to achieve high-speed operation, low power consumption, and low voltage in a circuit section other than the memory cell.

The configuration of the present invention will be described below.

A nonvolatile memory including at least a memory cell array in which a plurality of memory cells are arranged in a matrix and a memory cell driving circuit, wherein the memory cell array and the memory cell driving circuit are on the same substrate. Wherein the plurality of memory cells each have at least a memory TFT, and
Comprises at least a semiconductor active layer, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode, wherein the memory TFT is a fully depleted type. A nonvolatile memory is provided.

A non-volatile memory including at least a memory cell array in which a plurality of memory cells are arranged in a matrix and a memory cell driving circuit, wherein the memory cell array and the memory cell driving circuit are on the same substrate. Wherein the plurality of memory cells each have at least a memory TFT, and
Comprises at least a semiconductor active layer, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode. The semiconductor active layer of the memory TFT has a thickness of A non-volatile memory characterized by being at least 1 nm and not more than 1/4 of the channel length of the memory TFT.

The thickness of the semiconductor active layer of the memory TFT is preferably 1 to 50 nm.

The TFT constituting the memory cell array or the driving circuit of the memory cell may be of a completely depleted type.

The thickness of the semiconductor active layer of the TFT constituting the memory cell array or the drive circuit of the memory cell may be 1 nm or more and 1/4 or less of the channel length of the TFT.

The thickness of the semiconductor active layer of the TFT constituting the memory cell array or the drive circuit of the memory cell may be 1 to 50 nm.

Each of the plurality of memory cells has a T
The FT may be only the memory TFT.

Each of the plurality of memory cells has a T
FT may be the memory TFT and the switching TFT.

The non-volatile memory may perform flash-type erasing.

[0033] The substrate may be a substrate having an insulating surface.

[0034] The substrate may be an SOI substrate.

A semiconductor device comprising at least a pixel portion in which a plurality of pixels are arranged in a matrix, a driving circuit for driving the pixel portion, and a non-volatile memory,
The pixel unit, the drive circuit, and the nonvolatile memory,
A semiconductor device is provided which is formed over a substrate having an insulating surface.

As the semiconductor device, a liquid crystal display device or an EL display device is provided.

The semiconductor device includes a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a circuit diagram and a driving method of a nonvolatile memory according to the present invention will be described. In the present embodiment, an mxn-bit NOR type flash memory (m and n are each an integer of 1 or more) will be described as an example of a nonvolatile memory, but an example different from the present embodiment will be described in Example 2. ~ 4 can be referred to.

FIG. 1 is a circuit diagram of a nonvolatile memory according to the present invention. The nonvolatile memory according to the present embodiment includes a memory cell array 105 in which a plurality of memory cells are arranged in a matrix of m rows × n rows, an X address decoder 101, and a Y cell.
Address decoder 102, and other peripheral circuits 103,
104. Since each memory cell has one memory TFT and can store 1-bit information, the nonvolatile memory according to the present embodiment has mx
It has an n-bit storage capacity. Other peripheral circuits include an address buffer circuit, a control logic circuit, a sense amplifier, a booster circuit, and the like, and are provided as necessary. Note that the memory TFTs (1, 1) to (n,
m) may be an n-channel type or p-channel type TFT, but in this embodiment, it is an n-channel type TFT.

Since the nonvolatile memory of the present invention is formed by using the SOI technology, the driving circuit of the memory cell (the X address decoder 101 and the Y address decoder 102 in the present embodiment) and the other peripheral circuits 103 Together with the semiconductor device 104, the semiconductor device can be formed over a substrate having an insulating surface or an SOI substrate, so that a small-sized nonvolatile memory can be realized. Further, the semiconductor device can be integrally formed with any part of a semiconductor device including a TFT, and a semiconductor device including a nonvolatile memory which can be multifunctional, highly functional, and miniaturized can be provided. Becomes Embodiments 10 and 11 can be referred to for such a semiconductor device example.

In FIG. 1, the memory TFTs (i, i, i) constituting m memory cells arranged in the i-th column
In 1), (i, 2) to (i, m), a bit line Bi and a source line Si are connected to a drain electrode and a source electrode, respectively (i is an integer of 1 or more and n or less). Also,
Memory TFTs (1, j), (2, j) to (n, j) constituting n memory cells arranged in the j-th row
Has a word line Wj connected to the control gate electrode (j is an integer of 1 to m). Bit lines B1 to B
n and word lines W1 to Wm are connected to X address decoder 1
01 and the Y address decoder 102 respectively. Further, a predetermined potential Vs is commonly applied to the source lines S1 to Sn.

The non-volatile memory shown in FIG. 1 is called a NOR flash memory, and data is erased by flash-type erasing (collective erasing of the entire memory or erasing of each block). In addition, when writing and reading data, a specific memory cell is designated by the X address decoder 101 and the Y address decoder 102.
This is performed for each bit.

The nonvolatile memory according to the present invention has a structure shown in FIG.
The present invention is not limited to the NOR type flash memory shown in FIG.
Alternatively, a NOR type full-function EEPROM (see Embodiment 3) in which a memory cell is constituted by a plurality of TFTs including a memory TFT and a switching TFT, or another known nonvolatile memory may be used.

Next, a sectional structure of a memory TFT constituting the nonvolatile memory shown in FIG. 1 will be described with reference to FIG.

In FIG. 2, a memory TFT 213 includes a semiconductor active layer including a source region 202, a drain region 204, and a channel forming region 203, a first gate insulating film 205, a floating gate electrode 206, a second gate insulating film 207, And control gate electrode 20
8 In addition, a source wiring 210, a drain wiring 211, and a control gate wiring 212 are drawn out through the contact hole on the interlayer film 209.

The present invention is characterized in that the memory TFT forming the nonvolatile memory is a completely depleted type. Typically, the thickness of the semiconductor active layer of the memory TFT may be 1 nm or more and 1/4 or less of the channel length of the memory element. Further, the thickness of the semiconductor active layer of the memory TFT is 1 nm.
It is preferably in the range of 〜50 nm.

With the above structure of the memory TFT 213, a memory TFT formed on bulk silicon (see FIG. 3) or a memory TFT having a semiconductor active layer thicker than in the present embodiment can be used. Compared to,
Has many excellent features. Hereinafter, the characteristics of the memory TFT will be described along with the operation principle thereof.

First, when writing data to the memory TFT 213, the source wiring 210 is dropped to GND, and a positive high voltage (for example, 20 V) is applied to the drain wiring 211 and the control gate wiring 212. As a result, carriers moving in the channel forming region 203 of the memory TFT 213 are accelerated, impact ionization occurs, and a large number of high energy electrons (hot electrons) are generated. Then, the hot electrons cross the energy barrier of the first gate insulating film 205 and are injected into the floating gate electrode 206. In this manner, charges are accumulated in the floating gate electrode 206, and writing is performed.

The memory TFT 213 according to the present invention comprises:
Since the semiconductor active layer is thin, there is an advantage that impact ionization easily occurs during writing. Thus, writing by hot carrier injection can be performed with lower voltage and lower current. In other words, it is possible to reduce the voltage of the operation at the time of writing and reduce the power consumption.

Next, when erasing data written in the memory TFT 213, the source wiring 210 and the control gate wiring 212 are dropped to GND, and a positive high voltage (for example, 20 V) is applied to the drain wiring 211. As a result, electrons accumulated in the floating gate electrode 206 are injected into the drain region 204 by a tunnel current (also referred to as FN current or Fowler-Nordheim current), and data is erased.

The memory TFT 213 according to the present invention comprises:
Since the semiconductor active layer is not given a fixed potential unlike bulk silicon, the electric field applied between the drain region 204 and the channel formation region 203 is reduced. As a result, it becomes possible to greatly reduce the band-to-band tunnel current flowing between the substrate and the drain, which has been a cause of increasing the current at the time of erasing in the bulk silicon substrate.
As a result, power consumption is reduced.

The decrease in current at the time of writing and erasing is as follows.
It also has two important effects. The first relates to improving reliability. When the current at the time of writing and erasing decreases, the deterioration of the first gate oxide film 205 is greatly suppressed, and as a result, the number of rewritable times is greatly improved.
That is, the reliability is greatly improved.

The second relates to lowering the power supply voltage. Conventional non-volatile memory incorporates a booster circuit in a part of the peripheral circuit, so that the power supply voltage is kept low and the memory TFT
Generated the high voltage required for the operation. However, if a large current flows at the time of writing or erasing, sufficient boosting cannot be performed due to the increase in the current load on the booster circuit and the voltage drop in the memory cell, which hinders lowering the power supply voltage. I was coming. According to the present invention, as described above, it is possible to reduce the current at the time of operation requiring a high voltage. As a result, sufficient boosting becomes possible, and lower power supply voltage can be realized.

Next, when reading data from the memory TFT 213, the source wiring 210 is dropped to GND, and a predetermined voltage (for example, 5 V) is applied to the control gate electrode 208.
Is applied. At this time, according to the threshold voltage when charge is accumulated in the floating gate electrode 208 of the memory TFT 213 and when the charge is not accumulated, the memory T
When the FT 213 is turned off or on, data stored in the memory TFT is read.

In the nonvolatile memory of the present invention, the speed of the read operation can be increased. Further, effects of low power consumption and low voltage operation can be obtained.

These are common features found not only in the memory TFT but also in a normal TFT, and are based on the property that a fully-depleted TFT has a small junction capacitance and a depletion layer capacitance. When the junction capacitance is small, power consumption is reduced. Further, the on / off of the current flowing through the TFT becomes faster, and as a result, the writing speed and reading speed of the memory TFT are improved. On the other hand, if the capacitance of the depletion layer is small, good subthreshold characteristics can be obtained. Thereby, the change in the threshold voltage due to writing / erasing of the memory TFT is effectively increased, and operation at a lower voltage becomes possible.

In the present invention, the TFT forming the memory cell drive circuit and other peripheral circuits formed integrally with the memory TFT is made completely depleted, or the pixel formed integrally with the memory section in the electro-optical device. It is effective to make the TFT constituting the drive circuit for driving the pixel portion and the pixel portion completely depleted. Typically, the thickness of the semiconductor active layer of the TFT may be 1 nm or more and 1/4 or less of the channel length of the memory element. Further, the thickness of the semiconductor active layer of the TFT is preferably in the range of 1 nm to 50 nm.
As a result, it is possible to achieve high-speed operation, low power consumption, and low voltage in a circuit section other than the memory cell.

In addition, the fully depleted memory TFT has high soft error resistance. This is because element isolation is completely performed as compared with bulk silicon, and the amount of charges generated by alpha rays is reduced. Also,
The thinner the semiconductor active layer, the smaller the amount of charge generated by alpha rays and the higher the soft error resistance.

In FIG. 2, the memory TFT 213
Drain region 204 and floating gate electrode 20
6 partially overlaps with the first gate insulating film 205 interposed therebetween. This overlapping area (called an overlap area)
Is a region for erasing the memory TFT 213, and a tunnel current at the time of erasing mainly flows through this region. When erasing is performed on the source side, an overlap area is provided on the source side. In the case where a high negative voltage is applied to the gate voltage to release the entire channel formation region, the gate voltage is not necessarily provided.

In FIG. 2, the memory TFT 213
Although the control gate electrode 208 overlaps only with the floating gate electrode 206, it may overlap with both the floating gate electrode 206 and the semiconductor active layer. Such a structure is called an offset structure, and has an effect such as a reduction in off-current (see Embodiment 6).

Here, the operation of the nonvolatile memory of this embodiment will be described based on the operation principle of the memory TFT described above. Memory TFT (1, 1) in FIG.
Writing to and reading from the memory and batch erasing of the entire memory will be described.

First, when writing data to the memory TFT (1, 1), the source lines S1 to Sn are dropped to GND,
A positive high voltage (for example, 20 V) is applied to each of the bit line B1 and the word line W1. As a result, hot electrons generated by impact ionization are injected into the floating gate electrode and writing is performed. The threshold voltage of the memory TFT (1, 1) changes according to the amount of charge stored in the floating gate electrode.

When reading data stored in the memory TFT (1, 1), the source lines S1 to Sn are dropped to GND, and a predetermined voltage is applied to the word line W1. And
The data stored in the memory cell is read out from the bit line B1 corresponding to the threshold voltage when the charge is stored in the floating gate electrode of the memory TFT (1, 1) and the threshold voltage when the charge is not stored.

The predetermined voltage is in the state of “1” (state in which no electrons are stored in the floating gate electrode).
And the threshold voltage in the state of “0” (state in which electrons are accumulated in the floating gate electrode). For example, when the memory TFT in the “1” state has a threshold voltage of 0.5 V or more and 3.5 V or less, and the memory TFT in the “0” state has a threshold voltage of 6.5 V or more. For example, 5 V can be used as a predetermined voltage.

Finally, when erasing the entire memory at once, the source lines S1 to Sn and the word lines W1 to Wm are
Drop to ND. When a positive high voltage (for example, 20 V) is applied to the bit lines B1 to Bn, electrons accumulated in the floating gate electrode are injected into the drain region by a tunnel current in all the memory TFTs, and the stored data is stored. Is erased.

It is assumed that the potentials of the signal lines B2 to Bn and W2 to Wm which are not selected at the time of writing and reading are all 0V.

Of course, the value of the operating voltage described above is an example, and is not limited to that value. Actually, the voltage applied to the memory TFT (1, 1) depends on the thickness of the semiconductor active layer of the memory TFT, the capacitance between the control gate electrode and the floating gate electrode, and the like. Then, the operating voltage of the memory TFT (1, 1) also changes accordingly.

In addition, at the time of writing to and reading from the memory TFT (1, 1), erroneous erasure or erroneous writing may occur by applying a voltage to memory cells in the same column or row. The operating voltage needs to be set such that such write stress and read stress are minimized and erroneous erase and erroneous write do not occur.

In order to suppress over-erasing, it is preferable to perform writing to all the memory TFTs before performing the batch erasing. Further, a verifying circuit may be provided as a circuit for suppressing over-erasing and controlling the threshold value.

In the present embodiment, the memory TF
When writing / erasing T, instead of applying a positive or negative high voltage to the control gate electrode of the memory TFT at a time, a lower voltage may be applied by a plurality of pulses. In this case, deterioration of the TFT can be suppressed to some extent.

[0071]

(Embodiment 1) In this embodiment, a method for manufacturing a nonvolatile memory of the present invention on a substrate having an insulating surface will be described with reference to FIGS. A memory TFT (n-channel TFT) forming a memory cell, and two TFTs (p-channel TFT) forming a typical CMOS circuit as a driving circuit and other peripheral circuits of a memory cell are used as TFTs forming a nonvolatile memory. TFT and n-channel TFT) will be described as examples.

According to the method for manufacturing a nonvolatile memory described below, it is understood that the nonvolatile memory of the present invention can be integrally formed with any semiconductor device component that can be manufactured by using a thin film technique.

Further, in order to realize a nonvolatile memory and a semiconductor device in which a peripheral circuit composed of a TFT and other semiconductor parts are integrally formed on a substrate having an insulating surface, the mobility, the threshold voltage and the like must be improved. T with good characteristics
FT is often required. Since a TFT manufactured by the manufacturing method of this embodiment has a semiconductor active layer with excellent crystallinity and exhibits favorable characteristics, various TFTs which cannot be realized by integral formation with a TFT including an amorphous silicon semiconductor active layer are used. The non-volatile memory and the semiconductor device can also be integrally formed.

First, a quartz substrate 401 is prepared as a substrate having an insulating surface (FIG. 4A). Instead of the quartz substrate, a quartz substrate on which a silicon nitride film is formed as an insulating film, a silicon substrate on which a thermal oxide film is formed, a ceramic substrate, or the like may be used.

Next, an amorphous silicon film 402 having a thickness of 45 nm is formed by a known film forming method (FIG. 4A). Note that the present invention is not limited to an amorphous silicon film, and may be any amorphous semiconductor film (including a compound semiconductor film including an amorphous structure such as a microcrystalline semiconductor film and an amorphous silicon germanium film). .

The thickness of the semiconductor active layer depends on the memory TF
What is necessary is just to form so that T may become a complete depletion type. Typically, the thickness of the final semiconductor active layer is 1 nm or more and 1/4 or less of the channel length of the memory element (preferably 1 nm to 50 nm).
m). If the thickness of the semiconductor active layer does not satisfy such a condition, the occurrence of impact ionization peculiar to a fully depleted TFT is reduced, and a lower voltage and a smaller current at the time of writing in a nonvolatile memory are obtained. This is not preferable because the effect cannot be sufficiently obtained. In this embodiment, the final thickness of the semiconductor active layer is 30
nm.

Next, a crystallization step of the amorphous silicon film 402 is performed. The steps from here to FIG. 4B can be referred to Japanese Patent Application Laid-Open No. Hei 10-247735 by the present applicant. This publication discloses a technique relating to a method for crystallizing a semiconductor film using an element such as Ni as a catalyst.

First, protective films 411 to 413 having openings 415 and 416 (a silicon oxide film having a thickness of 150 nm in this embodiment) are formed. Then, a layer (referred to as a Ni-containing layer) 414 containing nickel (Ni) is formed on the protective films 411 to 413 by a spin coating method. Note that an ion implantation method, a plasma doping method, or a sputtering method using a resist mask may be used.

Further, as a catalytic element, in addition to nickel, cobalt (Co), iron (Fe), palladium (P
d), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb), indium (In), or the like can be used.

Next, as shown in FIG. 4C, a heat treatment is performed at 570 ° C. for 14 hours in an inert atmosphere to crystallize the amorphous silicon film 402. At this time, crystallization proceeds from the regions (referred to as Ni-added regions) 421 and 422 in contact with Ni as starting points and substantially parallel to the substrate. The crystalline silicon film 423 formed in this way has an advantage of excellent overall crystallinity because individual crystals are aggregated in a relatively uniform state (see Example 7). The heat treatment temperature is preferably 500 to 700 ° C. (typically 55 to 700 ° C.).
0 to 650 ° C.), and the treatment time is preferably 4 to 24.
It should be time.

Next, as shown in FIG.
Elements belonging to Group 15 (preferably, phosphorus) are added to the Ni-added regions 421 and 422 using the masks 11 to 413 as they are. Thus, regions 431 and 432 to which phosphorus is added at a high concentration (referred to as phosphorus added regions) are formed.

Then, as shown in FIG. 4D, heat treatment is performed at 600 ° C. for 12 hours in an inert atmosphere. This heat treatment is a gettering step of the metal element (Ni in this embodiment) with phosphorus, and finally almost all Ni is captured in the phosphorus added regions 431 and 432 as shown by arrows. By this step, the concentration of Ni remaining in the crystalline silicon film 433 is reduced to at least 2 × 10 ¹⁷ atoms / cm ³ as measured by SIMS (secondary mass ion analysis).

Thus, it is crystallized using a catalyst, and
A crystalline silicon film 433 whose catalyst is reduced to a level that does not hinder the operation of the TFT is obtained. After that, the protective films 411 to 413 are removed, and the phosphorus added regions 431 and 431 are removed.
And an island-shaped semiconductor layer (hereinafter, referred to as a semiconductor active layer) 501 to 503 using only the crystalline silicon film 433 that does not include 32
Is formed by a patterning process (FIG. 5A).

Next, the semiconductor active layer 501 is covered with resist masks 511 and 512 except for a region 513 which will be a drain region of a memory TFT later, and an n-type impurity element (also referred to as an n-type impurity element) is added. (Figure 5
(B)). N-type impurity region 5 formed by this step
13 has an n-type impurity element of 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm
³ ) Adjust the dose so that it is included in the concentration. As the n-type impurity element, phosphorus (P) or arsenic (As) may be used, and in this embodiment, phosphorus (P) is used.

After that, the resist masks 511 and 512 are removed, and the first gate insulating film 5 made of an insulating film containing silicon is removed.
21 are formed (FIG. 5C). First gate insulating film 5
The film thickness of 21 is 1 in consideration of the increase due to the subsequent thermal oxidation step.
What is necessary is just to adjust in the range of 0-250 nm. Note that the memory T
The thickness of the first gate insulating film constituting the FT is 10 to 50
nm, and the thickness of the first gate insulating film forming other elements may be 50 to 250 nm. As a film formation method, a known gas phase method (a plasma CVD method, a sputtering method, or the like) may be used. In this embodiment, a 50-nm-thick silicon nitride oxide film is formed by a plasma CVD method.

Next, a heat treatment is performed in an oxidizing atmosphere at 950 ° C. for one hour to perform a thermal oxidation step. In this thermal oxidation step, oxidation proceeds at the interface between the active layer and the silicon nitride oxide film, and the thickness of the semiconductor active layer finally becomes 30 nm.
Note that the oxidation atmosphere may be an oxygen atmosphere or an oxygen atmosphere to which a halogen element is added. When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Further, there is also an effect of preventing formation failure (edge thinning) of a thermal oxide film at an end of the active layer.

Next, a conductive film of 200 to 400 nm is formed and patterned to form gate electrodes 522 to 524 (FIG. 5C). At this time, the gate electrode 522 of the memory TFT (to be a floating gate electrode later)
Is formed so as to partially overlap the n-type impurity region 513 with the gate insulating film 521 interposed therebetween. This overlapping region is a region for passing a tunnel current when erasing the memory TFT.

Note that the gate electrode may be formed of a single conductive film, but it is preferable to form a stacked film such as two layers or three layers as necessary. A known conductive film can be used as a material for the gate electrode. Specifically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a nitride of the element (Typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film combining the above elements (typically, a Mo—W alloy, a Mo—Ta alloy), or a silicide film of the above element (Typically, a tungsten silicide film or a titanium silicide film) can be used.

In this embodiment, a laminated film composed of a 50 nm-thick tungsten nitride (WN) film and a 350 nm-thick tungsten (W) film is formed by a sputtering method. At this time, if an inert gas such as xenon (Xe) or neon (Ne) is added as a sputtering gas, film peeling due to stress can be prevented. Note that when the first gate insulating film is thin (typically, 30 nm or less), a silicon film containing an impurity imparting n-type or p-type conductivity is formed by a CVD method (pressure reduction C).
VD, plasma CVD, etc.) is also effective.

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, phosphorus (P) or arsenic (As) for n-type, boron (B) for p-type,
Gallium (Ga) or indium (In) may be used.

First, as shown in FIG. 5D, n-type impurity elements (phosphorus in this embodiment) 531 to 536 are added in a self-aligned manner using the gate electrodes 522 to 524 as masks.
A low concentration impurity region (n-region) is formed. This low concentration impurity region has a phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ³ to 1
Adjust so as to be × 10 ¹⁹ atoms / cm ³ .

Next, the gate insulating film 521 is etched by dry etching using the gate electrodes 522 to 524 as a mask, and is patterned into 601 to 603 (FIG. 6).
(A)).

Next, as shown in FIG. 6A, resist masks 604 and 605 are formed so as to cover the whole of the p-channel TFT and a part of the n-channel TFT. In this embodiment, phosphorus is added to form impurity regions 606 to 609 containing phosphorus at a high concentration. At this time, the concentration of the n-type impurity element is 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / c
m ³ ).

By this step, the source of the memory TFT is
Drain regions 606 and 607, and source / drain regions 608 and 609 of an n-channel TFT forming a CMOS
Then, an LDD region 610 is formed.

Next, as shown in FIG.
The masks 604 and 605 are removed and a new resist mask
611 and 612 are formed. And a p-type impurity element
(Boron in this embodiment), and contains boron at a high concentration.
Impurity regions 613 and 614 are formed. Here is Jibo
Run (B_TwoH₆1) by ion doping method using
²⁰~ 1 × 10^{twenty one}atoms / cm^Three(Typically 2 × 10²⁰~ 5
× 10²⁰atoms / cm^ThreeBoron is added to achieve a concentration of
I do. Thus, the source / drain of the p-channel TFT
Regions 613 and 614 are formed (FIG. 6B).

Next, as shown in FIG. 6C, after removing the resist masks 611 and 612, an insulating film 621 containing silicon is formed. The insulating film 621 becomes a second gate insulating film between the floating gate electrode and the control gate electrode in the memory TFT. The thickness of the insulating film 621 may be 10 to 250 nm. As a film formation method, a known gas phase method (a plasma CVD method, a sputtering method, or the like) may be used. Note that in this embodiment, a silicon nitride oxide film having a thickness of 50 nm is formed by a plasma CVD method.

Thereafter, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, lamp annealing, or a method combining these may be used. In this embodiment, 550 in a nitrogen atmosphere in an electric furnace is used.
Heat treatment at 4 ° C. for 4 hours. At this time, the damage of the active layer in the adding step is also repaired.

Next, a conductive film of 200 to 400 nm is formed and patterned to form a control gate electrode 622.
Is formed (FIG. 6C). Control gate electrode 6
22 is formed so as to overlap a part or the whole of the floating gate electrode with the insulating film 621 interposed therebetween.

Note that the control gate electrode 622 may be formed of a single-layered conductive film, but it is preferable that the control gate electrode 622 be formed of a stacked film such as two layers or three layers as necessary. A known conductive film can be used as a material for the gate electrode. In this embodiment, a tungsten nitride (WN) film having a thickness of 50 nm,
A laminated film of a 350 nm thick tungsten (W) film is formed by a sputtering method. Xenon (X
e), addition of an inert gas such as neon (Ne) can prevent the film from peeling due to stress. When the first gate insulating film is thin (typically, 30 nm or less), a silicon film containing an impurity imparting n-type or p-type conductivity is formed by a CVD method (low-pressure CVD, plasma CVD, or the like). It is also effective to form a film.

Next, an interlayer insulating film 631 is formed (FIG. 6).
(D)). As the interlayer insulating film 631, an insulating film containing silicon, an organic resin film, or a stacked film of a combination thereof may be used. Further, the thickness may be 400 nm to 1500 nm. In this embodiment, a silicon nitride oxide film having a thickness of 500 nm is used.

Next, as shown in FIG. 6D, contact holes are formed in the interlayer insulating film 631 and the insulating film 621, and source / drain wirings 632 to 636 and control gate wirings 637 are formed. In this embodiment, a three-layer laminated film in which a Ti film is continuously formed by sputtering, a 100 nm thick Ti film, an 300 nm thick aluminum film containing Ti, and a 150 nm thick Ti film. Of course, other known conductive films may be used. In this embodiment, the control gate wiring 6
Although 37 is provided separately from the control gate electrode 622, the control gate electrode may be used as it is as a control gate wiring.

Finally, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating dangling bonds of the semiconductor film with thermally excited hydrogen.
In this embodiment, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 2 hours to perform hydrogenation treatment. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Through the above steps, a TFT having a structure as shown in FIG. 6D can be manufactured.

Embodiment 2 In this embodiment, an example which is different from the circuit diagram of the memory cell described in the embodiment mode will be described with reference to FIG. First, FIG. 7A is a circuit diagram of a memory cell representing the memory cell array described in the embodiment. Two adjacent memory cells are the memory TFT 70
1a and 701b, source lines Sa and Sb, and bit lines Ba and Bb.

A characteristic of the circuit diagram of the memory cell shown in FIG. 7B is that adjacent memory cells share a source line. That is, the memory TFTs 702a and 702b
Are connected to a common source line S.

By adopting such a circuit configuration,
As compared with the circuit diagram shown in FIG.
/ 2, and memory cells can be arranged at a higher density. As a result, the size and capacity of the nonvolatile memory can be reduced.

As a method of operating the nonvolatile memory having the memory cell shown in FIG. 7B, writing and reading for each bit and erasing of a flash type can be performed as in the embodiment mode. . This is clear from the fact that the source line is a common wiring in the embodiment (FIG. 7A).

Note that the nonvolatile memory of this embodiment can be manufactured by the manufacturing method of Embodiment 1 similarly to the nonvolatile memory shown in the embodiment.

Embodiment 3 In this embodiment, an example which is different from the circuit diagram of the memory cell shown in FIGS. 7A and 7B will be described with reference to FIG. 7C. FIG. 7C is a circuit diagram of two adjacent memory cells representing a memory cell array. The corresponding signal lines are shown in FIG.
The same symbols as in (A) and (B) are used.

The memory cell shown in FIG.
As compared with the case of (A), the TFs constituting each memory cell
New switching TFTs 704a and 704b as T
Has a circuit configuration arranged in series with the memory TFT. A nonvolatile memory having such a structure is called a NOR type full-function EEPROM.

Looking at the left memory cell in FIG. 7C, the drain region of the memory TFT 703a is connected to the source or drain region of the switching TFT 704a, and the source region of the memory TFT 703a is connected to the source line Sa. I have. The other of the source region and the drain region of the switching TFT 704a is connected to the bit line Ba. And the memory T
The control gate electrode of the FT 703a is a word line W
The gate electrode of the switching TFT 704a is connected to the selection line V.

The memory cell on the right side has the same circuit configuration as the memory cell on the left side.
T703b, switching TFT 704b, source line S
b, a bit line Bb, a word line W, and a selection line V.

N having the memory cell shown in FIG.
A feature of the OR type full-function EEPROM is that writing, reading, and erasing can all be performed for each bit. In this embodiment, the memory TFT and the switching T
The operation method of the left memory cell will be described in the case where the FTs are all n-channel TFTs.

Data can be written to and read from the memory TFT 703a in the same manner as in the NOR flash memory.
The selection line V is set so that T704a is turned on.
Should be set.

That is, when writing is performed, the source line S
a is dropped to GND, and a positive high voltage (for example, 20 V) is applied to each of the bit line Ba, the word line W, and the selection line V. As a result, hot electrons due to impact ionization are accumulated in the floating gate electrode and writing is performed. When performing reading, the source line Sa is dropped to GND, and a predetermined voltage (for example, 5 V) is applied to the word line W.
Is applied. In order to turn on the switching TFT 704a, a positive voltage (for example, 5
V). As a result, data stored in the memory cell can be read from the bit line Ba according to the state of the memory TFT 703a.

When erasing data, the source line Sa
And the word line W is dropped to GND. Then, when a positive high voltage (for example, 20 V) is applied to the selection line V and the bit line Ba, electrons accumulated in the floating gate electrode of the memory TFT 703a are emitted to the drain region by a tunnel current, and the stored data is erased. Will be erased. Note that data is not erased for other memory cells in the same column because the switching TFT is in an off state. As a result, erasing is performed only in the memory TFT 703a.

In the above operation, all the non-selected signal lines may be set to 0V. In addition, the value of the operating voltage described above is an example, and is not limited to the value.

In this embodiment, the memory TFT and the switching TFT are n-channel TFTs. However, by setting the operating voltage to an appropriate value, each of the n-channel TFT and the p-channel TFT can be used. Is also possible. Further, the switching TFT may be arranged on both sides of the memory TFT. By arranging on both sides, the current during non-operation is reduced, and malfunctions are less likely to occur.

The NOR type full function EEP of this embodiment
The ROM can be manufactured by using the manufacturing method of Embodiment 1 by changing the mask.

(Embodiment 4) In this embodiment, a circuit diagram of a NAND flash memory will be described as an example different from the circuit diagrams of the memory cells shown in the embodiment mode and the embodiment 3.

FIG. 8 is a circuit diagram of a NAND-type memory cell array in which memory cells are arranged in a matrix of 8 rows × n rows (only columns at both ends are shown). Each memory cell is constituted by one n-channel type memory TFT.

In FIG. 8, eight memory TFTs (for example, (1, 1) to (1,
8)) are connected in series, and the respective channel forming regions are connected to the substrate wirings G1 to Gn. The substrate wirings G1 to Gn are common wirings. The control gate electrodes of n memory TFTs (for example, (1, 1) to (n, 1) in the first row) arranged in the same row are connected to the word line W1.

At both ends of eight memory TFTs (for example, (1, 1) to (1, 8) in the first column) connected in series, selection TFTs (1, 0) and (1, 9) are provided. They are connected in series. That is, the selection TFTs (1, 0) to (n, 0) are above the memory cells in the first row, and the selection TFTs (1, 9) are below the memory cells in the eighth row. To (n, 9) are respectively arranged. Selection TFT (1, 0)-
Bit lines B1 to Bn are connected to the other of the source electrode and the drain electrode of (n, 0), and a selection gate line S1 is connected to the gate electrode. A common source potential Vs is applied to the other of the source electrode and the drain electrode of the selection TFTs (1, 9) to (n, 9), and the selection gate line S2 is connected to the gate electrode. ing.

An operation method of the NAND flash memory will be described. Here, a description will be given of a method of batch erasing by a tunnel current and simultaneous writing of one row by a tunnel current.

In this embodiment, the state “0” indicates a state in which electric charges are accumulated in the floating gate electrode of the memory TFT, and the state “1” indicates that electric charges are accumulated in the floating gate electrode of the memory TFT. Not in a state. Further, it is assumed that the threshold voltage of the memory TFT in the “0” state is 0.5 V to 3 V, and the memory TFT in the “1” state is
Is -1 V or less.

First, one-row simultaneous writing will be described.
As a specific example, consider the simultaneous writing of the first row,
"0" is set to FT (1, 1), and the memory TFT (2, 1) to
A case where "1" is written to (n, 1) will be described. Immediately before writing, all are in the state of “1”. First, the board wiring G
1 to Gn and the source potential Vs are dropped to GND. Also, 20V and 0V are applied to the selection gate lines S1 and S2, respectively, and the selection TFTs (1, 0) to (n, 0) are turned on, and the selection TFTs (1, 9) to (n, 9) is turned off. Then, 20 V is applied to the word line W1, and the word lines W2
7V is applied to W8, 0V is applied to bit line B1, and 7V is applied to bit lines B2 to Bn.

As a result, a high voltage (approximately 20 V) is applied only between the floating gate electrode and the channel forming region of the memory TFT (1, 1), and charge injection into the floating gate electrode is performed by a tunnel current. That is, "0" is written. In addition, the memory TFT (2,
Although a potential difference of 14 V is generated between the floating gate electrode and the channel formation region in 1) to (n, 1), charge injection into the floating gate electrode by a tunnel current is hardly performed. That is, the memory TFTs (2, 1) to
(N, 1) remains in the state of "1". Also, for the memory TFTs other than the first row, only a potential difference of at most 7 V occurs between the floating gate electrode and the channel formation region, and no charge is injected into the floating gate electrode. In this way, one-row simultaneous writing is performed.

When reading from the memory TFT (1, 1), first, the substrate wirings G1 to Gn are dropped to GND, and 0V is applied to the word line W1 and 5V is applied to the word lines W2 to W8. Thereby, the memory TF of the second to eighth rows
T are all turned on. Also, the memory TF in the first row
T is in an on state when the state is "1", and is in an off state when the state is "0". That is, conduction and non-conduction of the eight memory TFTs connected in series are determined by the state of the memory TFTs in the first row. Then, 5V is applied to the selection gate lines S1 and S2 to turn on the selection TFT, and the source potential Vs is dropped to GND, so that the memory TFT (1,.
It becomes possible to read data from 1).

When performing batch erase, all word lines W
1 to W8 are set to 0V, and the substrate wirings G1 to Gn are set to 20V. As a result, a high voltage is applied between the floating gate electrode and the channel formation region, and erasing is performed by a tunnel current. The potential of the selection gate line may be freely determined, but in order to prevent a strong electric field from being generated in the gate oxide film,
It is preferable to apply the same voltage as the substrate wirings G1 to Gn.

The above-described values of the operating voltage are merely examples, and are not limited to the values. Further, in the present embodiment, a description has been given of a memory cell array of 8 × n memory cells, but the present invention is not limited to this configuration.

The configuration of this embodiment can be implemented by freely combining with any of the configurations shown in Embodiments 1 to 3. In particular, the memory portion can be formed in combination with the NOR flash memory described in the embodiment. Further, the substrate wiring may be formed at the same time when the island-shaped semiconductor layer is formed.

(Embodiment 5) In this embodiment, the top structure of a memory cell constituting a nonvolatile memory according to the present invention will be described. FIG. 9 illustrates an example of a top view of a memory cell included in the NOR flash memory (see FIG. 1) described in the embodiment.

In FIG. 9, since the four memory cells have the same structure, the memory cell at the upper left will be described. The region 901 is a semiconductor active layer. The word line 904 and the floating gate electrode 903 are formed at the time of forming the first wiring layer, and the source line 905 and the bit line 903 are formed.
7 and control gate electrode 902 and word line 90
The wiring 906 connecting to the wiring 4 is formed when the second wiring layer is formed. In the figure, a black portion indicates that a contact is made with a wiring or a semiconductor layer therebelow.

The cross-sectional structure of the memory cell described in the embodiment (FIG. 2) is considered to be a cross-sectional structure obtained by cutting the top view of the memory cell shown in FIG. 9 along, for example, line AB. Can be.

This embodiment is an example of a top view of a memory cell according to the embodiment. Of course, any other top view may be used as long as it is the circuit diagram (FIG. 1) shown in the embodiment.

(Embodiment 6) In this embodiment, an example different from that of the embodiment will be described for a cross-sectional structure of a memory cell constituting a nonvolatile memory of the present invention. Figure 1 for explanation
0 is used.

In FIG. 10, a substrate 1 having an insulating surface
The memory TFT 1013 formed on the 001 includes a semiconductor active layer including a source region 1002, a drain region 1004, and a channel formation region 1003, a first gate insulating film 1005, a floating gate electrode 1006, a second gate insulating film 1007, A control gate electrode 1008 is provided. The source wiring 1010, the drain wiring 1011 and the control gate wiring 1012 are formed on the interlayer film 1009 through contact holes.
Has been pulled out.

The memory TFT shown in FIG. 10 is of a fully depleted type. Typically, the thickness of the semiconductor active layer of the memory TFT is 1 nm or more and １ ／ of the channel length of the memory element.
The following may be sufficient. More preferably, the thickness of the semiconductor active layer of the memory TFT is in the range of 1 nm to 50 nm.

Since the memory TFT 1013 has such a structure, it can be compared with a memory TFT formed on bulk silicon (see FIG. 3) or a memory TFT having a semiconductor active layer thicker than this embodiment. Has various advantages, as already described in the embodiment.

In the present embodiment, the memory TFT 1
013 has an offset structure. That is, the memory TFT 1013 has a region (offset region) in which the control gate electrode 1006 and the channel formation region 204 partially overlap with the second gate insulating film 1007 interposed therebetween.

A feature of a nonvolatile memory using a memory TFT having an offset structure is that a memory TF in an overerased state is used.
That is, correct reading is possible even when T exists, and the off-state current is reduced in unselected memory cells to suppress malfunction. As a method of operating a nonvolatile memory using a memory TFT having an offset structure, writing and reading for each bit and erasing of a flash type can be performed as in the embodiment.

When the non-volatile memory is constituted by a memory TFT having no offset structure, a memory TFT in an overerased state causes a read operation to malfunction.
This is because the memory TFT in the over-erased state connected to the bit line for reading is turned on. When the memory TFT has an offset structure as in this embodiment, even if the unselected memory TFT is in an overerased state, the memory TFT is kept off by the offset region, so that a correct read operation can be performed.

As described above, when the memory TFT is allowed to be over-erased, the operation margin is increased, and the verify circuit is not required, so that the size of the peripheral circuit can be reduced.

(Embodiment 7) T prepared according to Embodiment 1
The FT semiconductor active layer is formed of a unique crystalline silicon film having continuity of the crystal structure even at the crystal grain boundaries. For details of such a crystalline silicon film, refer to Japanese Patent Application Nos. 10-044659 and 10-152316 filed by the present applicant.
No., Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-1
No. 52305 may be referred to. Hereinafter, the features of the crystal structure experimentally examined by the present applicant will be briefly described.

The crystalline silicon film is a polycrystalline silicon film in which a plurality of needle-shaped or rod-shaped crystals (hereinafter, referred to as rod-shaped crystals) are gathered and lined up microscopically. This can be easily confirmed by observation with a TEM (transmission electron microscope).

In addition, electron diffraction and X-ray (X-ray)
By using diffraction, it can be confirmed that the surface (channel formation region) of the crystalline silicon film has a {110} plane as a main orientation plane, although the crystal axis has some deviation. At this time, if analysis is performed by electron beam diffraction, it can be confirmed that diffraction spots corresponding to the {110} plane appear clearly. Further, it can be confirmed that each spot has a distribution (expansion) of about ± 1 ° on a concentric circle.

Further, by observing the crystal grain boundaries formed by contacting the individual rod-shaped crystals by HR-TEM (high-resolution transmission electron microscopy), it can be confirmed that the crystal lattices at the crystal grain boundaries have continuity. This strongly suggests that the observed lattice fringes are continuously connected at the crystal grain boundaries.

It is considered that the continuity of the crystal lattice at the crystal grain boundary is caused by the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. Note that the definition of the planar grain boundary in this specification is “Characterization of High-Efficie”.
ncy Cast-Si Solar Cell Wafers by MBIC Measurement
Ryuichi Shimokawa and Yutaka Hayashi, JapaneseJ
ournal of Applied Physics vol.27, No.5, pp.751-75
8, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary has the characteristic of being electrically inactive, and does not function as a trap that hinders the movement of carriers even though it is a crystal grain boundary. In particular, when the crystal axis (the axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called the corresponding grain boundary of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

Actually, the crystalline silicon film of this embodiment was changed in detail to T
Observation using EM shows that most (90% or more, typically 95% or more) of the crystal grain boundaries are the corresponding grain boundaries of {3}, typically {211} twin grain boundaries.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3. In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundary are continuous at an angle of about 70.5 °, and therefore, this crystal grain boundary is a corresponding grain boundary of Σ3. You can see that there is.

From the above considerations, the crystalline silicon film obtained by the manufacturing method of Example 1 has a crystal structure in which two crystal grains adjacent to each other at the crystal grain boundary are bonded with extremely good consistency (accurately, a crystal grain). Field structure). In other words, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, the crystalline silicon film obtained by the manufacturing method of Example 1 can be regarded as having substantially no crystal grain boundaries.

Further, it was found that the defects (stacking faults) existing in the crystal grains were almost completely eliminated by the heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. Confirmed by observation. This is apparent from the fact that the number of stacking faults and the like before and after this heat treatment step is greatly reduced.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, it has been found that the spin density of the crystalline silicon film of this embodiment is at least 5 × 10 ¹⁷ spins / cm ³ or less (typically 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

From the above, the crystalline silicon film manufactured according to Example 1 has extremely few defects in crystal grains and can be regarded as having substantially no crystal grain boundaries. It can be considered as a single crystal silicon film.

(Embodiment 8) As a substrate for forming the nonvolatile memory of the present invention, SIMOX, Smart-Cut
An SOI substrate such as (registered trademark of SOITEC) or ELTRAN (registered trademark of Canon Inc.) may be used.

The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure.

The configuration of this embodiment can be freely combined with any of the configurations of Embodiments 2 to 6. Further, by optimizing the process conditions for the SOI substrate, the process after the formation of the crystalline silicon film in the manufacturing method of Embodiment 1 can be applied as it is.

(Embodiment 9) The nonvolatile memory of the present invention is multifunctional, highly functional, and compact by being integrally formed with the components of a semiconductor device composed of TFTs formed on a substrate having an insulating surface. Semiconductor device can be provided. In this embodiment, as such an example,
1 illustrates an electro-optical device (typically, a liquid crystal display device and an EL display device) including a nonvolatile memory, a pixel portion, a driving circuit for driving the pixel portion, and a γ (gamma) correction circuit of the present invention.

FIG. 11 is a block diagram of the electro-optical device according to this embodiment. In FIG. 11, a nonvolatile memory 1102 of the present invention, a pixel portion 1105, a gate signal side drive circuit 1103 and a source signal side drive circuit 1104 for driving the pixel portion, and a γ (gamma) correction circuit 1101 are provided. ing. An image signal, a clock signal, a synchronization signal, and the like are transmitted via an FPC (flexible print circuit) 1106.

The γ correction circuit is a circuit for performing γ correction. The γ correction is a correction for creating a linear relationship between the voltage applied to the pixel electrode and the transmitted light intensity of the liquid crystal or the EL layer thereon by applying an appropriate voltage to the image signal.

Further, the electro-optical device of this embodiment can be integrally formed on a substrate having an insulating surface by the manufacturing method of Embodiment 1, for example. At this time, the nonvolatile memory 1
It is effective to use not only the pixel 102 but also the pixel portion 1105, the driving circuits 1103 and 1104 for driving the pixel portion, and the TFTs forming the γ correction circuit to be fully depleted. Note that a known method may be used for steps after TFT formation including formation of a liquid crystal or EL layer.

In this embodiment, one source wiring driving circuit and one gate wiring driving circuit are provided as driving circuits for driving the pixel portion. However, a plurality of driving circuits may be provided. Further, the pixel portion 110
5. A known circuit structure may be used for the driving circuits 1103 and 1104 for driving the pixel portion and the γ (gamma) correction circuit 1101.

In the electro-optical device of this embodiment, the nonvolatile memory 1102 stores (stores) correction data for performing γ correction on an image signal transmitted from a personal computer, a television receiving antenna, or the like. . γ correction circuit 1
101 performs γ correction on the image signal with reference to the correction data.

The data for γ correction may be stored once before shipping the electro-optical device, but it is also possible to periodically rewrite the correction data. Further, even in the case of an electro-optical device made in the same manner, the optical response characteristics of the liquid crystal (such as the relationship between the transmitted light intensity and the applied voltage) may be slightly different. Also in this case, in this embodiment, since different γ correction data can be stored for each electro-optical device, the same image quality can always be obtained.

Further, by storing a plurality of correction data in the nonvolatile memory and adding a new control circuit, a plurality of color tone displays based on the correction data can be freely selected.

Note that when storing the correction data of the γ correction in the nonvolatile memory 1102, the applicant of the present invention disclosed in Japanese Patent Application No.
It is preferred to use the means described in 156696. Further, a description regarding gamma correction is also made in the same application.

Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 7.

Embodiment 10 An example of a semiconductor device having a nonvolatile memory according to the present invention, which is different from the semiconductor device shown in Embodiment 9, will be described with reference to FIG.

FIG. 12 is a block diagram of an electro-optical device (typically, a liquid crystal display device and an EL display device) according to this embodiment. The electro-optical device according to the present embodiment includes a nonvolatile memory 1203, an SRAM 1202, and a pixel unit 12 according to the present invention.
06, a gate signal side driving circuit 1204 for driving the pixel portion
A source signal side driving circuit 1205 and a memory controller circuit 1201 are provided. An image signal, a clock signal, a synchronization signal, and the like are transmitted via an FPC (flexible print circuit) 1207.

The memory controller circuit 1201 in this embodiment is a control circuit for controlling operations such as storing and reading image data in the SRAM 1202 and the nonvolatile memory 1203.

An SRAM 1202 is provided for writing data at high speed. D instead of SRAM
A RAM may be provided, and an SRAM may not be particularly provided as long as the nonvolatile memory is capable of high-speed writing.

The electro-optical device of this embodiment can be integrally formed on a substrate having an insulating surface by, for example, the manufacturing method of Embodiment 1. At this time, the nonvolatile memory 1203
In addition, it is effective that the pixel portion 1206, the driving circuits 1204 and 1205 for driving the pixel portion, the SRAM 1202, and the TFT included in the memory controller circuit 1202 be completely depleted. Note that steps after forming the TFT including formation of a liquid crystal or an EL layer may be manufactured using a known method.

In this embodiment, one source line drive circuit and one gate line drive circuit are provided as drive circuits for driving the pixel portion. However, a plurality of drive circuits may be provided. Also, the SRAM 120
2. Pixel unit 1206, driving circuit 120 for driving the pixel unit
4, 1205, and memory controller circuit 1201
A known circuit structure may be used.

In the electro-optical device of this embodiment, the image signal sent from the personal computer, the television receiving antenna or the like is stored (stored) in the SRAM 1202 for each frame.
The image signal is supplied to the memory controller circuit 1201
Are sequentially input to the pixel unit 1206 and displayed. S
The RAM 1202 stores at least image information for one frame of an image displayed on the pixel portion 1206. For example, when a 6-bit digital signal is transmitted as an image signal, a memory capacity corresponding to at least the number of pixels × 6 bits is required. Also, the memory controller circuit 1
According to 201, the image signal stored in the SRAM 1202 can be stored in the non-volatile memory 1203, or the image signal stored in the non-volatile memory 1203 can be input to the pixel portion 1206 and displayed as necessary.

Since the image data stored in the SRAM 1202 and the non-volatile memory 1203 is a digital signal, a D / A converter or an A / D
It is desirable to form the converter on the same substrate.

In the structure of this embodiment, the image displayed on the pixel portion 1206 is always stored in the SRAM 1202,
The image can be paused easily. Further SR
The image signal stored in the AM 1202 is stored in the nonvolatile memory 1
By storing the image signal in the pixel unit 203 or the image signal stored in the nonvolatile memory 1203 to the pixel portion, operations such as recording and reproduction of an image can be easily performed. Then, it is possible to freely pause the television broadcast, record and reproduce without recording on a video deck or the like.

The amount of images that can be recorded and played back is
M1202 and the storage capacity of the nonvolatile memory 1203. Storing at least one frame of image signal enables recording and reproduction of a still image. further,
If the memory capacity of the nonvolatile memory 1203 can be increased to such an extent that image information such as several hundred frames or several thousand frames can be stored, it is possible to reproduce (replay) an image several seconds or several minutes ago.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 7 and 9.

(Embodiment 11) The non-volatile memory according to the present invention is integrally formed with the components of the semiconductor device composed of TFTs, thereby realizing the multi-function, high-function and small-size as shown in Embodiments 9 and 10. An electro-optical device can be provided. In this embodiment, an active matrix liquid crystal display device will be described as a semiconductor device which can be formed integrally with the nonvolatile memory of the present invention.

FIG. 13A is a circuit diagram of an active matrix type liquid crystal display device. In FIG. 13A, an active matrix liquid crystal display device includes a pixel portion 1301 in which pixels 1304 are arranged in a matrix, a source signal driver circuit 1302, and a gate signal driver circuit 130.
And 3. A plurality of drive circuits may be provided as each of the source signal side drive circuit and the gate signal side drive circuit.

The pixels 13 forming the pixel portion 1301
FIG. 13B shows an enlarged view of FIG. Pixel 1304 is
A switching TFT 1311 having a switching TFT 1311, a liquid crystal element 1314, and a capacitor 1315;
One gate electrode is connected to the gate signal line 1312 and one of the source electrode and the drain electrode is connected to the source signal line 1313.
It is connected to the. The other of the source electrode and the drain electrode of the switching TFT 1311 is connected to the liquid crystal 1314 and the capacitor 1315. Further, a predetermined potential is applied to one of the remaining electrodes of the liquid crystal element 1314 and the capacitor 1315.

Note that one of the electrodes of the capacitor 1315 may be connected to a dedicated power supply line without being connected to the wiring 1316. Further, the capacitor 1315 may not be provided. The switching TFT 1311 has n
A channel TFT or a p-channel TFT may be used.

When the nonvolatile memory of the present invention is formed integrally with the active matrix type liquid crystal display device of this embodiment, any of the structures of Embodiments 1 to 10 may be combined.

(Embodiment 12) The nonvolatile memory of the present invention is integrally formed with the components of a semiconductor device composed of TFTs, so that it has a multifunctional, high-functionality and small size as shown in Embodiments 9 and 10. An electro-optical device can be provided. In this embodiment, an active matrix EL display device will be described as a semiconductor device which can be formed integrally with the nonvolatile memory of the present invention.

FIG. 14A shows an active matrix type E.
It is a circuit diagram of an L display device. In FIG. 14A, an active matrix EL display device includes a pixel portion 1401 in which pixels 1404 are arranged in matrix, a source signal driver circuit 1402, and a gate signal driver circuit 140.
And 3. There may be a plurality of source signal side drive circuits and a plurality of gate signal side drive circuits.

Also, the pixels 14 constituting the pixel portion 1401
FIG. 14B shows an enlarged view of No. 04. Pixel 1404 is
Switching TFT 1411, EL driving TFT 141
4, a switching TFT 14 having an EL element 1416
11 has a gate electrode connected to a gate signal line 1412, and one of a source electrode and a drain electrode connected to the source signal line 14112.
3 is connected. The other of the source electrode and the drain electrode of the switching TFT 1411 is an EL driving TF.
Connected to the gate electrode of T1414. Also, EL
The source electrode of the driving TFT 1414 is connected to the power supply line 141.
5, the drain electrode is connected to the EL element 1416. A predetermined potential is applied to the other electrode of the EL element 1416.

Note that a capacitor may be provided between the gate electrode of the EL driving TFT 1414 and the power supply line 1415.

In the active matrix type EL display device of this embodiment, an n-channel type TF
Use T. Further, the switching TFT 1411 may be an n-channel TFT or a p-channel TFT.

When the nonvolatile memory of the present invention is formed integrally with the active matrix type EL display device of this embodiment, any of the structures of Embodiments 1 to 10 may be combined.

Embodiment 13 The nonvolatile memory of the present invention has various uses. In this embodiment, an electronic device using the nonvolatile memory of the present invention will be described.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display, a goggle type display, a game machine, a car navigation system, a personal computer, and a portable information terminal (mobile computer, A mobile phone or an electronic book). Examples of those are shown in FIGS.

FIG. 15A shows a display, which includes a housing 2001, a support 2002, a display portion 2003, and the like.
The nonvolatile memory of the present invention may be formed integrally with the display portion 2003 and other signal control circuits.

FIG. 15B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The nonvolatile memory of the present invention may be formed integrally with the display portion 2102 and other signal control circuits.

FIG. 15C shows a part (one side on the right) of the head mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, and a display section 220.
4, including an optical system 2205, a display device 2206, and the like. The nonvolatile memory of the present invention may be formed integrally with the display device 2206 and other signal control circuits.

FIG. 15D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, a recording medium 2302, operation switches 2303, display units 2304 and 2305, and the like. This device uses a DVD (Digital Versatile Disc) as a recording medium and a C
Using D or the like, music viewing, movie viewing, games, and the Internet can be performed. The nonvolatile memory of the present invention may be formed integrally with the display portion 2304 and other signal control circuits.

FIG. 15E shows a goggle type display, which comprises a main body 2401, a display section 2402, and an arm section 240.
3 inclusive. The non-volatile memory of the present invention is a display unit 2402
And other signal control circuits.

FIG. 15F shows a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503,
It is composed of a keyboard 2504 and the like. The nonvolatile memory of the present invention may be formed integrally with the display portion 2503 and other signal control circuits.

FIG. 16 (A) shows a mobile phone,
01, audio output unit 2602, audio input unit 2603, display unit 2604, operation switch 2605, antenna 2606
including. The nonvolatile memory of the present invention may be formed integrally with the display portion 2604 and other signal control circuits.

FIG. 16B shows a sound reproducing device, specifically, a car audio.
2, including operation switches 2703 and 2704. The nonvolatile memory of the present invention may be formed integrally with the display portion 2702 and other signal control circuits. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the embodiments 1 to 12.

[0203]

According to the present invention, by making the memory TFT a completely depleted TFT, it is possible to reduce the power consumption of the nonvolatile memory, reduce the power supply voltage, and greatly improve the number of times of rewriting. At the same time, effects such as lower operating voltage of the nonvolatile memory, higher speed of the read operation, and improvement of soft error resistance can be obtained.

Further, according to the present invention, the size of the nonvolatile memory can be reduced by integrally forming the memory cell with its driving circuit and other peripheral circuits.

Furthermore, the nonvolatile memory of the present invention is
By being integrally formed with another semiconductor component formed of T, a semiconductor device including a nonvolatile memory capable of achieving high functionality, multifunction, and miniaturization can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a nonvolatile memory of the present invention.

FIG. 2 is a cross-sectional view of a memory TFT constituting a nonvolatile memory according to the present invention.

FIG. 3 shows a memory T constituting a conventional nonvolatile memory;
Sectional drawing of FT.

FIG. 4 is a diagram showing a manufacturing process of the nonvolatile memory of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the nonvolatile memory of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the nonvolatile memory of the present invention.

FIG. 7 is a circuit diagram of a memory cell constituting the nonvolatile memory of the present invention.

FIG. 8 is a circuit diagram of a memory cell constituting the nonvolatile memory of the present invention.

FIG. 9 is a top view of a memory cell included in the nonvolatile memory of the present invention.

FIG. 10 is a cross-sectional view of a memory TFT constituting a nonvolatile memory according to the present invention.

FIG. 11 is a block diagram of an electro-optical device using the nonvolatile memory of the present invention.

FIG. 12 is a block diagram of an electro-optical device using the nonvolatile memory of the present invention.

FIG. 13 illustrates a structure of an active matrix liquid crystal display device.

FIG. 14 illustrates a structure of an active matrix EL display device.

FIG. 15 shows an electronic device using the nonvolatile memory of the present invention.

FIG. 16 shows an electronic device using the nonvolatile memory of the present invention.

[Explanation of symbols]

 101 X address decoder 102 Y address decoder 103, 104 Peripheral circuit 201 Substrate 202 Source region 203 Channel formation region 204 Drain region 205 First gate insulating film 206 Floating gate electrode 207 Second gate insulating film 208 Control gate electrode 209 Interlayer insulation Film 210 Source wiring 211 Drain wiring 212 Control gate wiring 213 Memory TFT

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/322 H01L 27/08 321C 21/8238 321L 27/092 27/10 434 27/08 331 29/78 612B 27/115 613B 29/786 613A

Claims (14)

[Claims] 1. A non-volatile memory comprising at least a memory cell array in which a plurality of memory cells are arranged in a matrix and a memory cell driving circuit, wherein the memory cell array and the memory cell driving circuit The plurality of memory cells are integrally formed on the same substrate, and each of the plurality of memory cells has at least a memory TFT. The memory TFT includes a semiconductor active layer, a first gate insulating film, a floating gate electrode, A non-volatile memory comprising at least a gate insulating film and a control gate electrode, wherein the memory TFT is a completely depleted type. 2. A non-volatile memory comprising at least a memory cell array in which a plurality of memory cells are arranged in a matrix, and a memory cell driving circuit, wherein the memory cell array and the memory cell driving circuit are: The plurality of memory cells are integrally formed on the same substrate, and each of the plurality of memory cells has at least a memory TFT. The memory TFT includes a semiconductor active layer, a first gate insulating film, a floating gate electrode, At least a gate insulating film and a control gate electrode, wherein the thickness of the semiconductor active layer of the memory TFT is at least 1 nm and at most １ ／ of the channel length of the memory TFT. Characteristic nonvolatile memory. 3. The nonvolatile memory according to claim 1, wherein the thickness of the semiconductor active layer of the memory TFT is 1 to 50 nm. 4. The non-volatile memory according to claim 1, wherein a TFT forming the memory cell array or a driving circuit of the memory cell is a completely depleted type. 5. The semiconductor device according to claim 2, wherein the semiconductor active layer of the TFT constituting the memory cell array or the driving circuit of the memory cell has a thickness of 1 nm or more, and
A non-volatile memory, wherein the length of the non-volatile memory is not more than 1/4 of the channel length of T. 6. The nonvolatile memory according to claim 4, wherein a thickness of a semiconductor active layer of a TFT constituting the memory cell array or a drive circuit of the memory cell is 1 to 50 nm. . 7. The nonvolatile memory according to claim 1, wherein the plurality of memory cells each have only the memory TFT. 8. The non-volatile memory according to claim 1, wherein the TFTs included in each of the plurality of memory cells are the memory TFT and a switching TFT. 9. The nonvolatile memory according to claim 1, wherein a flash-type erase is performed. 10. The nonvolatile memory according to claim 1, wherein the substrate is a substrate having an insulating surface. 11. The nonvolatile memory according to claim 1, wherein the substrate is an SOI substrate. 12. A pixel section in which a plurality of pixels are arranged in a matrix, a driving circuit for driving said pixel section,
A nonvolatile memory according to claim 1, wherein the pixel unit, the driving circuit, and the nonvolatile memory are:
A semiconductor device which is formed over a substrate having an insulating surface. 13. The semiconductor device according to claim 12, wherein the semiconductor device is a liquid crystal display device or an EL display device. 14. The semiconductor device according to claim 12, wherein the semiconductor device is a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, and a car audio.