JP2001314076A - Control circuit and method for maintaining high efficiency in buck-boost switching regulator - Google Patents

Abstract

A high-efficiency buck-boost switching regulator that can regulate an output voltage that is higher, lower, or equal to an input voltage. A method for controlling a buck-boost switching regulator circuit to supply a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor;
Generating a feedback signal, comprising: a first switch, a second switch, a third switch, and a fourth switch; and using the first drive signal to set a duty cycle of the first switch. Controlling the duty cycle of the second switch using the second drive signal; controlling the duty cycle of the third switch using the third drive signal; Controlling the duty cycle of the fourth switch using the drive signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a switching regulator. More particularly, the present invention relates to a control circuit and method for controlling a buck-boost switching regulator that maintains high efficiency.

[0002]

2. Description of the Related Art A switching regulator is an unregulated input power supply.
Pressure V_INFrom the adjusted output voltage V_{OU T}To the load
You. Synchronous switching regulators have at least two switches
And these switches are out of step with each other (out
 of phase with other)
Switch on and off to provide current to the load. System
The control circuit controls switching of the switches.

With reference to FIGS. 1A-1C, three types of prior art synchronous switching regulators will be described. FIG. 1A shows a typical buck switching regulator 10, which can only regulate an output voltage V _OUT that is lower than the input voltage V _IN . FIG. 1B shows a typical boost switching regulator 12, which can only regulate an output voltage V _OUT that is higher than the input voltage V _IN . FIG. 1C illustrates a typical buck-boost switching regulator 14, which may regulate an output voltage V _OUT that is higher, lower, or equal to the input voltage V _IN .

Referring to FIG. 1A, a synchronous buck switching regulator 10 has two switches A and B. A control circuit (not shown) switches A and B on (closed) and off (open) in a step-out state with each other, and supplies a current to the load 19. The switching regulator 10 includes an input capacitor 16
, Synchronous switches A and B, inductor 17,
And an output capacitor 18. Input voltage source V _IN and input capacitor 16 are coupled between the first terminal of switch A and ground. Switch B is coupled between the second terminal of switch A and ground. A first terminal of the inductor 17 is coupled to a second terminal of the switch A, and an output capacitor 18 and a load 19 are coupled between the second terminal of the inductor 17 and ground.

Referring to FIG. 1B, the synchronous boost switching regulator 12 has two switches C and D. A control circuit (not shown) switches C and D on (closed) and off (open) out of step with each other, and supplies a current to the load 19. The switching regulator 12 includes an input capacitor 16
, Synchronous switches C and D, inductor 17,
And an output capacitor 18. Input voltage source V _IN and input capacitor 16 are coupled between a first terminal of inductor 17 and ground. Switch C is coupled between the second terminal of inductor 17 and ground. Switch D has a first terminal coupled to a second terminal of inductor 17 and a second terminal coupled to a first terminal of output capacitor 18. Output capacitor 18 has a second terminal coupled to ground, and load 19 is coupled between the first terminal of output capacitor 18 and ground.

Referring to FIG. 1C, synchronous buck-boost switching regulator 14 includes an input capacitor 16, an inductor 17, an output capacitor 18, and switches A, B, C and D. Switches A, B, C and D are, for example, metal oxide semiconductor field effect transistors (MOSFE).
T) or a bipolar junction transistor (BJT). The input voltage V _IN and the input capacitor 16 are
Coupled between the first terminal of switch A and ground. Switch B is coupled between the second terminal of switch A and ground. Inductor 17 is coupled between a second terminal of switch A and a first terminal of switch D. Switch C is coupled between the first terminal of switch D and ground. Output capacitor 18 and load 19 are coupled between the second terminal of switch D and ground.

The switching regulator 14 has four switches (A,
B, C and D). The control circuit (not shown)
A, B, C and D are switched on and off to supply current to the load 19. Prior art control circuits typically switch both switches A and C on and both B and D on. When switches B and D are turned on, switches A and C are turned off, and when switches A and C are turned on, switches B and D are turned off. Prior art control circuits use the following switching sequence iterations: turn on A and C, then turn on B and D, then turn on A and C, then turn on B and D, and so on. It is. As described above, the control circuit of the related art switches on / off of all four switches in the regulator 14 so that the load 1
9 to supply current.

One example of a prior art control circuit that can be used with the regulators of FIGS. 1A-1C is to compare a control voltage at its non-inverting input with a symmetric triangular (or asymmetric sawtooth) waveform at its inverting input. A pulse width modulator having one comparator for generating a digital pulse width modulation signal is included. The control voltage is generated from the output voltage of the regulator.
When the control voltage is swept from the bottom of the waveform signal to the top,
The duty cycle of this pulse width modulated signal increases from 0% to 100%. In the buck-boost regulator, the pulse width modulated signal is used to drive switches A and C together, and the inverted pulse width modulated signal is used to drive switches B and D together. The control voltage changes the duty cycle of the pulse width modulated signal, and thus also changes the input-output voltage ratio of the regulator.

[0009] Synchronous buck-boost regulators, such as regulator 14, can advantageously operate to provide a regulated output voltage for a wide variety of output-input voltage requirements. However, the control circuit of the prior art synchronous buck-boost switching regulator disadvantageously switches on and off by constantly driving all four switches in each cycle, regardless of output current and output-input voltage ratio. ,
Adjust V _OUT . More power is consumed to drive the switch on and off than if the switch remained either on or off. More power is consumed by the synchronous buck-boost regulator 14 than is consumed by the synchronous buck regulator 10 or the synchronous boost regulator 12. Because the regulators 10 and 12
This is because there are only two switches that need to be turned on and off. Therefore, the synchronous buck-boost switching regulator 14 used for the control circuit of the prior art is the synchronous buck regulator 10 or the synchronous boost regulator 12.
Less efficient than

[0010]

The control circuit of the prior art
A further disadvantage of the switching regulator 14 used is that the average
That is, the inductor current is high. Average inductor current is
The higher, the more power to adjust the output voltage
Is consumed in the inductor, which is undesirable. Conventional
The average input of the switching regulator 14 used with the control circuit of the technology
Ductor current / I_{IN D}(/ In this specification
-) And average output current / I_OUTThe relationship between
It is represented by the following equation.

[0011]

(Equation 1) Here, V _OUT is the output voltage, and V _IN is the switching regulator 1
4 is the input voltage. For example, if V _IN = V _OUT , then the average inductor current is twice the average output current in switching regulator 14, assuming zero loss.

However, whether it is higher or lower than the input voltage,
Alternatively, it would be desirable to provide a highly efficient buck-boost switching regulator control circuit that can regulate the same output voltage. It is also desirable to provide a buck-boost switching regulator control circuit that saves power by driving fewer than all switches when the input voltage is higher or lower than the output voltage. It is also desirable to provide a buck-boost switching regulator with low average inductor current.

It is an object of the invention to determine whether the input voltage is higher than
It is to provide a high efficiency buck-boost switching regulator that can regulate an output voltage that is low or the same.

It is a further object of the present invention to provide a buck-boost switching regulator control circuit that saves power by driving fewer than all switches when the input voltage is higher or lower than the output voltage. It is.

[0015] It is a further object of the present invention to provide a buck-boost switching regulator having a low average inductor current.

[0016]

SUMMARY OF THE INVENTION A method of controlling a buck-boost switching regulator circuit according to the present invention to provide a regulated output voltage to an output node comprises the steps of: And the first of the inductors
A first switch coupled between the first terminal of the inductor and a ground, a second switch coupled between the first terminal of the inductor and ground, and a second switch coupled between the second terminal of the inductor and ground. And a fourth switch coupled between the second terminal of the inductor and the output node, the feedback signal being proportional to the output voltage of the switching regulator. And controlling a duty cycle of the first switch using a first drive signal generated in response to the feedback signal; and generating a second drive signal in response to the feedback signal. The second drive signal is used to control the duty cycle of the second switch, such that when the first switch is on, the second switch is off and the second switch is on. Sometimes the first Controlling the duty cycle of the third switch using a third drive signal generated in response to the feedback signal and the step of turning off the switch, thereby controlling the output voltage at the output node. Is adjusted, the duty cycle of the first switch is not equal to the duty cycle of the third switch, and using a fourth drive signal generated in response to the feedback signal, Controlling the duty cycle of the fourth switch, such that when the fourth switch is on, the third switch is off, and when the third switch is on, the fourth switch is Turning off, thereby achieving the above object.

Generating first and second voltage signals proportional to the feedback signal;
Providing the first and second periodic waveform signals, and comparing the first voltage signal with the first periodic waveform signal to generate a first control signal, wherein the first and second A drive signal is generated in response to the first control signal;
Generating a second control signal by comparing the second voltage signal with the second periodic waveform signal, wherein the third and fourth drive signals include: And a step generated in response.

The step of providing the first and second periodic waveform signals includes the step of providing the first periodic waveform signal offset from the second periodic waveform signal by a DC offset voltage. It may further include.

The step of generating the first and second voltage signals may further include the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage. .

[0020] Providing the first and second periodic waveform signals further comprises providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. May be.

The step of providing the first and second periodic waveform signals further comprises the step of providing the second periodic waveform signal having a waveform different from the waveform of the first periodic waveform signal. May be included.

The step of providing the first and second periodic waveform signals includes the step of providing the second periodic waveform signal having a peak-to-peak amplitude different from the first periodic waveform signal. It may further include.

[0023] The first and second periodic waveform signals may be sawtooth waveform signals.

[0024] The first and second periodic waveform signals may be triangular waveform signals.

The method comprises the steps of generating first and second voltage signals proportional to the feedback signal;
Providing first and second periodic waveform signals;
Comparing the first voltage signal with the first periodic waveform signal to generate a first control signal; and comparing the second voltage signal with the second periodic waveform signal. , Generating a second control signal; and selecting the first and second control signals to generate a first selection signal, wherein the first selection signal is substantially Having a constant propagation delay, wherein the first and second drive signals are generated in response to the first select signal; and selecting the first and second control signals to generate a second drive signal. Generating a second select signal, wherein the second select signal has a substantially constant propagation delay, and wherein the third and fourth drive signals are responsive to the second select signal. May be further included.

A method of controlling a buck-boost switching regulator circuit in accordance with the present invention to provide a regulated output voltage to an output node includes the step of providing a buck-boost switching regulator comprising an inductor, an input voltage and a first voltage of the inductor. A first switch coupled between the first terminal of the inductor; a first diode having an anode coupled to ground and a cathode coupled to the first terminal of the inductor; and a second switch of the inductor. A second switch coupled between a terminal and ground; a second diode having an anode coupled to the second terminal of the inductor and a cathode coupled to the output node; Generating a feedback signal proportional to the output voltage of the switching regulator; and using the first drive signal generated in response to the feedback signal to generate a feedback signal for the first switch. Controlling a duty cycle of the second switch using a second drive signal generated in response to the feedback signal to control a duty cycle of the second switch, thereby adjusting the output voltage at the output node. While the duty cycle of the first switch is not equal to the duty cycle of the second switch, thereby achieving the above object.

The method comprises the steps of generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. Generating a first control signal as compared to the first periodic waveform signal, wherein the first drive signal is generated in response to the first control signal. Comparing the second voltage signal with the second periodic waveform signal to generate a second control signal, wherein the second drive signal is responsive to the second control signal. May be further included.

[0028] The step of providing the first and second periodic waveform signals comprises the step of:
Providing the first periodic waveform signal offset from the first periodic waveform signal.

The step of generating the first and second voltage signals may further include the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage.

[0030] Providing the first and second periodic waveform signals further comprises providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. May be.

The step of providing the first and second periodic waveform signals further comprises the step of providing the second periodic waveform signal having a waveform different from the waveform of the first periodic waveform signal. May be included.

The step of providing the first and second periodic waveform signals includes the step of providing the second periodic waveform signal having a peak-to-peak amplitude different from the first periodic waveform signal. It may further include.

[0033] The first and second periodic waveform signals may be sawtooth waveform signals.

[0034] The first and second periodic waveform signals may be triangular waveform signals.

The method includes the steps of generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. Generating a first control signal by comparing the first periodic waveform signal; and comparing the second voltage signal to the second periodic waveform signal to generate a second control signal. Generating, and selecting the first and second control signals to generate a first select signal, wherein the first select signal has a substantially constant propagation delay. , The first
Generating a drive signal in response to the first selection signal; and selecting the first and second control signals;
Generating a second select signal, wherein the second select signal has a substantially constant propagation delay, and wherein the second drive signal is responsive to the second select signal; Generated step may be further included.

A method of controlling a buck-boost switching regulator circuit according to the present invention to provide a regulated output voltage to an output node includes the steps of: providing a buck-boost switching regulator comprising an inductor, an input voltage and a first of the inductor. A first switch coupled between the first terminal of the inductor and a ground, a second switch coupled between the first terminal of the inductor and ground, and a second switch coupled between the second terminal of the inductor and ground. And a diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the method comprising: Generating a feedback signal proportional to the output voltage; and controlling a duty cycle of the first switch using a first drive signal generated in response to the feedback signal. , Using the second drive signal generated in response to the feedback signal to control the duty cycle of the second switch, thereby, the first
The second switch is turned off when the second switch is turned on, and the first switch is turned off when the second switch is turned on; and a third switch generated in response to the feedback signal. Control the duty cycle of the third switch so that while the output voltage is being regulated at the output node, the duty cycle of the first switch is Unequal to the duty cycle of the switch, thereby achieving said objective.

The method includes the steps of generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. The first periodic waveform signal is compared with the first periodic waveform signal.
Wherein the first and second drive signals are generated in response to the first control signal, and the second voltage signal is generated in the second period. Generating a second control signal in comparison with a dynamic waveform signal, wherein the third drive signal is generated in response to the second control signal. .

The step of providing the first and second periodic waveform signals includes the step of providing the first periodic waveform signal offset from the second periodic waveform signal by a DC offset voltage. It may further include.

[0039] The step of generating the first and second voltage signals may further include the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage.

Providing the first and second periodic waveform signals further comprises providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. You may.

Providing the first and second periodic waveform signals further comprises providing the second periodic waveform signal having a different waveform than the first periodic waveform signal. You may.

[0042] Providing the first and second periodic waveform signals includes providing the second periodic waveform signal having a peak-to-peak amplitude different from the first periodic waveform signal. It may further include.

[0043] The first and second periodic waveform signals may be sawtooth waveform signals.

[0044] The first and second periodic waveform signals may be triangular waveform signals.

The method includes generating first and second voltage signals that are proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. Generating a first control signal by comparing the first periodic waveform signal; and comparing the second voltage signal to the second periodic waveform signal to generate a second control signal. Generating, and selecting the first and second control signals to generate a first select signal, wherein the first select signal has a substantially constant propagation delay. , The first
And a second driving signal is generated in response to the first selection signal; and selecting the first and second control signals to generate a second selection signal. Wherein the second selection signal has a substantially constant propagation delay, and wherein the third drive signal is generated in response to the second selection signal. Good.

A method of controlling a buck-boost switching regulator circuit according to the present invention to provide a regulated output voltage to an output node includes the steps of: providing a buck-boost switching regulator comprising an inductor, an input voltage and a first voltage of the inductor. A first switch coupled between the first terminal of the inductor and a cathode coupled to the first terminal of the inductor and a second terminal of the inductor and a ground. And a third switch coupled between the second terminal of the inductor and the output node, said second switch being proportional to the output voltage of the switching regulator. Generating a feedback signal to control the duty cycle of the first switch using a first drive signal generated in response to the feedback signal; Controlling a duty cycle of the second switch using a second drive signal generated in response to the first signal while the output voltage is being regulated at the output node. Controlling the duty cycle of the third switch using a step that is not equal to the duty cycle of the second switch, and using a third drive signal generated in response to the feedback signal. And when the third switch is on, the second switch is off, and when the second switch is on, the third switch is off. Objective is achieved.

The method comprises the steps of generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. Generating a first control signal as compared to the first periodic waveform signal, wherein the first drive signal is generated in response to the first control signal. Generating a second control signal by comparing the second voltage signal with the second periodic waveform signal, wherein the second and third drive signals comprise the second control signal. Generating in response to the signal.

The step of providing the first and second periodic waveform signals further comprises the step of providing the first periodic waveform signal offset from the second periodic waveform signal by a DC offset voltage. May be included.

The step of generating the first and second voltage signals may further include the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage.

Providing said first and said second periodic waveform signals further comprises providing said first and said second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. May be.

The step of providing the first and second periodic waveform signals further includes the step of providing the second periodic waveform signal having a waveform different from the first periodic waveform signal. You may.

Providing the first and second periodic waveform signals includes providing the second periodic waveform signal having a peak-to-peak amplitude different from the first periodic waveform signal. It may further include.

[0053] The first and second periodic waveform signals may be sawtooth waveform signals.

[0054] The first and second periodic waveform signals may be triangular waveform signals.

The method comprises the steps of generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal. Generating a first control signal by comparing the first periodic waveform signal; and comparing the second voltage signal to the second periodic waveform signal to generate a second control signal. Generating, and selecting the first and second control signals to generate a first select signal, wherein the first select signal has a substantially constant propagation delay. , The first
Is generated in response to the first selection signal, and selecting the first and second control signals to generate a second drive signal.
Generating a second select signal, wherein the second select signal has a substantially constant propagation delay, and wherein the second and third drive signals are responsive to the second select signal. May be further included.

A control circuit for controlling the buck-boost switching regulator circuit according to the present invention to supply the regulated output voltage to the output node comprises: a buck-boost switching regulator comprising an inductor, an input voltage and a second voltage of the inductor. A first switch coupled between the first switch and the first terminal of the inductor;
A second switch coupled between the second terminal of the inductor and ground, and a third switch coupled between the second terminal of the inductor and ground.
And a fourth switch coupled between the second terminal of the inductor and the output node, wherein the control circuit comprises an input coupled to the output node of the switching regulator circuit. A signal generator circuit comprising: a node; a waveform generator providing a periodic waveform at a waveform output node; and first, second, third, and fourth output nodes.
And a second output node is coupled to the input node of the signal generator circuit, and the third and fourth output nodes are coupled to the waveform output node of the waveform generator; A first comparator circuit having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit; and second and fourth outputs of the signal generator circuit A second comparator circuit having first and second inputs respectively coupled to the node; and a logic circuit having a logic gate, the logic circuit comprising a second comparator circuit coupled to an output of the first comparator circuit. 1 and an output of a second comparator circuit coupled to the output of the second comparator circuit.
And first, second, third, and fourth outputs respectively coupled to the first, second, third, and fourth switches, wherein the second switch is turned on when the second switch is turned on. The first switch is off, the first switch is on, the second switch is off, the fourth switch is on, the third switch is off, and the third switch is off. When turned on, the fourth switch comprises a logic circuit that is turned off, thereby achieving the above object.

A DC offset may be generated between the third output node and the fourth output node of the signal generator circuit.

[0058] The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a current coupled between the fourth output node and ground. And the resistor and the current source may generate the DC offset.

[0059] A DC offset may be generated between the first output node and the second output node of the signal generator circuit.

[0060] The signal generator circuit includes a resistor coupled between the first output node and the second output node, and a current coupled between the second output node and ground. And the resistor and the current source may generate the DC offset.

[0061] The waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node; A periodic waveform generator for providing a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node; The fourth output node of the signal generator circuit may be coupled to the second waveform output node.

[0062] The periodic waveform may be a sawtooth waveform.

[0063] The periodic waveform may be a triangular waveform.

The control circuit further comprises a first and a second multiplexer circuit, the first multiplexer circuit comprising: a first input of the logic circuit and a first and a second comparator; And the second multiplexer circuit may be coupled between the second input of the logic circuit and the output of each of the first and second comparators.

The control circuit includes an amplifier circuit having first and second inputs and an output coupled to the input node of the signal generator circuit; an output node of the switching regulator circuit; The circuit may further comprise a first resistor coupled between the first input of the circuit and a second resistor coupled between the first input of the amplifier circuit and ground. Good.

A control circuit for controlling the buck-boost switching regulator circuit according to the present invention to supply the regulated output voltage to the output node comprises: A first switch coupled between the first terminal of the inductor; a first diode having an anode coupled to ground and a cathode coupled to the first terminal of the inductor; A second switch coupled between the terminal of
A second diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node; and an input node coupled to the output node of the switching regulator circuit. , A waveform generator providing a periodic waveform at a waveform output node, and first, second, third and fourth output nodes, wherein the first and second outputs are provided. A signal generator circuit, wherein a node is coupled to the input node of the signal generator circuit, and wherein the third and fourth output nodes are coupled to the waveform output node of the waveform generator; A first comparator circuit having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit; and a first comparator circuit coupled to the second and fourth output nodes of the signal generator circuit, respectively. First and A second comparator circuit having two inputs, and a logic circuit comprising a logic gate, the logic circuit having a first input coupled to an output of the first comparator circuit, and a second comparator circuit. A logic circuit having a second input coupled to an output of the circuit and first and second outputs respectively coupled to the first and second switches, thereby achieving the above object. You.

[0067] A DC offset may be generated between the third output node and the fourth output node of the signal generator circuit.

[0068] The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a current coupled between the fourth output node and ground. And the resistor and the current source generate a DC offset between the first output node and the second output node of the signal generator that may generate the DC offset. May be done.

[0069] The signal generator circuit includes a resistor coupled between the first output node and the second output node, and a current coupled between the second output node and ground. And the resistor and the current source may generate the DC offset.

[0070] The waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node; Of the second waveform output node at the second waveform output node
And the third output node of the signal generator circuit is coupled to the first waveform output node, and the fourth output node of the signal generator circuit is connected to the second waveform It may be coupled to an output node.

[0071] The periodic waveform may be a sawtooth waveform.

[0072] The periodic waveform may be a triangular waveform.

The control circuit further includes a first and a second multiplexer circuit, wherein the first multiplexer circuit is provided for each of the first input of the logic circuit and each of the first and second comparators. Coupled to an output, the second multiplexer circuit may be coupled between the second input of the logic circuit and the output of each of the first and second comparators.

The control circuit includes an amplifier circuit having first and second inputs, an output coupled to the input node of the signal generator circuit, the output node of the switching regulator circuit and the amplifier circuit. The circuit may further comprise a first resistor coupled between the first input of the circuit and a second resistor coupled between the first input of the amplifier circuit and ground. Good.

A control circuit for controlling the buck-boost switching regulator circuit according to the present invention to supply the regulated output voltage to the output node comprises: a buck-boost switching regulator comprising: an inductor; A first switch coupled between the first switch and the first terminal of the inductor;
A second switch coupled between the second terminal of the inductor and ground, and a third switch coupled between the second terminal of the inductor and ground.
And a diode having an anode coupled to the second terminal of the inductor and a cathode coupled to the output node; and an input node coupled to the output node of the switching regulator circuit. A waveform generator for providing a periodic waveform at a waveform output node;
And a third and fourth output node, wherein the first and second output nodes are coupled to the input node of the signal generator circuit, and wherein the third and fourth output nodes are
An output node of the signal generator circuit is coupled to the waveform output node of the waveform generator;
And a first comparator circuit having first and second inputs respectively coupled to the first and second output nodes, and a first and a second circuit respectively coupled to the second and fourth output nodes of the signal generator circuit. A second comparator circuit having a second input; and a logic circuit having a logic gate, the logic circuit comprising: a first input coupled to an output of the first comparator circuit; A second input coupled to an output of the comparator circuit; and first, second, and third outputs coupled to the first, second, and third switches, respectively, the second switch. When the first switch is turned on, the first switch is turned off, and when the first switch is turned on, the second switch is turned off.

[0076] A DC offset may be generated between the third output node and the fourth output node of the signal generator circuit.

[0077] The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a current coupled between the fourth output node and ground. And the resistor and the current source may generate the DC offset.

[0078] A DC offset may be generated between the first output node and the second output node of the signal generator circuit.

The signal generator circuit includes a resistor coupled between the first output node and the second output node, and a current coupled between the second output node and ground. And the resistor and the current source may generate the DC offset.

[0080] The waveform generator comprises first and second waveform generators, the first waveform generator providing a first periodic waveform at a first waveform output node, and Of the second waveform output node at the second waveform output node
And a third waveform of said signal generator circuit is provided.
Output node is coupled to the first waveform output node;
The fourth output node of the signal generator circuit may be coupled to the second waveform output node.

[0081] The periodic waveform may be a sawtooth waveform.

[0082] The periodic waveform may be a triangular waveform.

The control circuit further comprises a first and a second multiplexer circuit, the first multiplexer circuit comprising a first input of the logic circuit and the first and second comparators. And the second multiplexer circuit may be coupled between the second input of the logic circuit and the output of each of the first and second comparators.

The control circuit includes an amplifier circuit having first and second inputs, an output coupled to the input node of the signal generator circuit, the output node of the switching regulator circuit and the amplifier circuit. The circuit may further comprise a first resistor coupled between the first input of the circuit and a second resistor coupled between the first input of the amplifier circuit and ground. Good.

A control circuit for controlling the buck-boost switching regulator circuit according to the present invention to supply the regulated output voltage to the output node comprises: A first switch coupled between the first terminal of the inductor, a diode coupled to the first terminal of the inductor and a cathode coupled to the first terminal of the inductor, and a second terminal of the inductor. A second switch coupled to ground; and a third switch coupled between the second terminal of the inductor and the output node, the output node of the switching regulator circuit. And a waveform generator for providing a periodic waveform at a waveform output node;
And a third and fourth output node, wherein the first and second output nodes are coupled to the input node of the signal generator circuit, and wherein the third and fourth output nodes are coupled to the third and fourth output nodes.
An output node of the signal generator circuit is coupled to the waveform output node of the waveform generator;
And a first comparator circuit having first and second inputs respectively coupled to the first and second output nodes, and a first and a second circuit respectively coupled to the second and fourth output nodes of the signal generator circuit. A second comparator circuit having a second input; and a logic circuit having a logic gate, the logic circuit comprising: a first input coupled to an output of the first comparator circuit; A second input coupled to an output of the comparator circuit; and first, second, and third outputs coupled to the first, second, and third switches, respectively, the second switch. When the third switch is turned on, the third switch is turned off, and when the third switch is turned on, the second switch is turned off.

[0086] A dc offset may be generated between the third output node and the fourth output node of the signal generator circuit.

[0087] The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a current coupled between the fourth output node and ground. And the resistor and the current source may generate the DC offset.

[0088] A DC offset may be generated between the first output node and the second output node of the signal generator circuit.

[0089] The signal generator circuit may include a resistor coupled between the first output node and the second output node, and a current coupled between the second output node and ground. And the resistor and the current source may generate the DC offset.

The waveform generator includes first and second waveform generators, the first wave generator providing a first periodic waveform at a first waveform output node, and Providing a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node; The fourth output node of the signal generator circuit may be coupled to the second waveform output node.

The periodic waveform may be a sawtooth waveform.

[0092] The periodic waveform may be a triangular waveform.

The control circuit further includes first and second multiplexer circuits, and the first multiplexer circuit is configured to control the first input of the logic circuit and each of the first and second comparators. Coupled to an output, the second multiplexer circuit may be coupled between the second input of the logic circuit and the output of each of the first and second comparators.

The control circuit includes an amplifier circuit having first and second inputs, an output coupled to the input node of the signal generator circuit, the output node of the switching regulator circuit and the amplifier circuit. The circuit may further comprise a first resistor coupled between the first input of the circuit and a second resistor coupled between the first input of the amplifier circuit and ground. Good.

The above and other objects of the present invention are to provide a high efficiency buck-boost switching regulator in buck mode when the input voltage is higher than the desired output voltage, and Is provided in a boost mode by a control circuit capable of operating in a buck-boost mode when the input voltage is higher, lower or equal to the desired output voltage. The present invention also includes a method of adjusting the output voltage of a high efficiency buck-boost switching regulator in buck, boost, and buck-boost modes. During buck and boost modes, less than all switches are turned on and off, thereby providing current to the load. The remaining switches remain on or off during buck or boost mode operation. During the buck-boost mode, all switches are turned on or off. This scheme saves power because not all switches are turned on and off in each cycle in buck-boost mode.

The control circuit of the present invention can control a synchronous buck-boost switching regulator and an asynchronous buck-boost switching regulator. The control circuit of the present invention includes a pulse width adjuster circuit and a logic circuit. This pulse width adjuster circuit
The control voltage indicating the output voltage is monitored to determine when to operate the switching regulator in buck, boost, or buck-boost mode. The pulse width adjuster circuit is coupled to logic that drives the switches on and off. The present invention also generates first and second voltage signals proportional to the regulated voltage output of the switching regulator, provides first and second periodic waveform signals, and converts the first voltage signal to a first voltage signal. A first control signal is generated by comparing the first control signal with the first periodic waveform signal; a second control signal is generated by comparing the second voltage signal with the second periodic waveform signal; And controlling the first switch with a first drive signal proportional to the second control signal, and controlling the second switch with a second drive signal proportional to the second control signal.

[0097]

BRIEF DESCRIPTION OF THE DRAWINGS The above objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the accompanying drawings. In the drawings, like reference numbers refer to like components.

Referring to FIG. 2A, a control circuit according to the present invention will be described. The power supply 15 is a synchronous switching regulator 14
And a control circuit 20. Synchronous switching regulator 14
It receives an input voltage V _IN and provides a regulated output voltage V _OUT . Input voltage V _IN may be higher, lower, or substantially the same as output voltage V _OUT . The control circuit 20 may operate the switching regulator 14 in a buck mode, a boost mode, or a buck-boost mode. Synchronous switching regulator 14 has four switches coupled between V _IN and V _OUT . These switches are connected to V _OUT
Controls the supply voltage of the current to the output node at which the output voltage is maintained at the regulated value. The control circuit is
The four drive signals (V _A , V _B , V _C and V _D ) which receive the output voltage V _OUT and control the switching of the four switches (A, B, C and D) in the synchronous switching regulator 14 are output. provide.

Referring to FIG. 2B, an exemplary schematic of power supply 15
The figure is shown. The circuit 15 has four switches (A, B,
C and D) and synchronous switching with control circuit 20
It includes a regulator 14. Switches A, B, C and D
The drive signal V_A, V_B, V _CAnd V_DControlled by
You. The control circuit 20 determines that the resistors 21A and 21B
Amplifier 22, a pulse width modulator 25, and a logic circuit 29
And The pulse width modulator 25 is connected to the signal generator 24
And comparators 27 and 28.

In the back mode, the power supply 15
Voltage V_INOutput voltage V smaller than_{OU T}Provide and control times
Road 20 turns on switch D and turns off switch C
Switching frequency f of the regulator_sSwitch A and
And switch B on and off. In boost mode
And the power supply 15 has the input voltage_INOutput voltage V greater than
_OUTAnd the control circuit 20 turns on the switch A.
With the switch B turned off,
Wave number f_sTurn switches C and D on and off with
You. In the buck-boost mode, the power supply 15
Voltage V_INLess than, greater than or the same output voltage
V_OUTAnd the control circuit 20 controls the switching frequency of the regulator.
Number f_sSwitches on and off of all four switches.
Therefore, if the power supply operates in buck-boost mode
ON / OFF switching of all four switches
Therefore, the control circuit 20 saves power.

Control circuit 20 allows only four switching states: A and C are both turned on, A and D are both turned on, B and C are both turned on, and B and D are turned on. Are switched on. No three or more switches are turned on at the same time, and if a switch is not indicated as on, the switch is off. It is impossible to turn on both switches A and B. This is because such a configuration shorts V _IN to ground. It is impossible to turn on both switches C and D.
This is because such a configuration shorts V _OUT to ground. When switches A and C are turned on, current flows through inductor 17 between V _IN and ground. When switches A and D are turned on, current flows through inductor 17 through V _IN and V _OUT . When switches B and C are turned on, inductor 1
7 are coupled to ground. When switches B and D are turned on, current flows through inductor 17 between V _out and ground.

The steady state operating point of the synchronous switching regulator according to the present invention is easily obtained by considering the average voltage across the inductor 17 and can be expressed as:

[0103]

(Equation 2) Where / V _IND is the average voltage across inductor 17, and t _AC , t _AD , t _BC and t _BD are switches A and C, A and D, B and C respectively in one switching cycle. And B and D are both turned on. V _AC , V _AD , V _BC and V
_BD is the time t in one switching cycle
It is the voltage applied to the inductor 17 between _AC , t _AD , t _BC and t _BD . T is the duration of one switching cycle.

The following are the voltages across inductor 17 during each possible switching state.

[0105]

[Table 1] In the steady state, the average voltage across inductor 17 is zero (/ V _IND = 0). Therefore, equation (2)
By setting == zero and substituting values from the table above, the steady state ratio of output voltage-input voltage can be expressed as:

[0106]

(Equation 3) Here, t _A represents the total time during one period T during which switch A is turned on in combination with either switch C or switch D. t _D represents the total time in one period T during which switch D is turned on in combination with either switch A or switch B. Equation (3) describes switches A-D, diode 32 of FIG.
Assuming ideal components such as and 34 and inductor 17, the switching regulator of the present invention allows t _A to be greater than, less than, or substantially greater than t _D during a single switching cycle. Verify the ability to regulate the output voltage above, below or substantially the same as the input voltage, depending on

When switches A and B switch on and off at switching frequency f _s , switch C remains off during each switching cycle T and switch D switches off each switching cycle T (t _D = T). The power supply 15 operates in the buck mode. Duty cycle D _A switch A is _{/ t A T, / t A} T , since the switch A becomes shorter on than the period T, it is smaller than 1. From equation (3), the output-input voltage ratio can be expressed as:

[0108]

(Equation 4) Since D _A is less than 1, V _OUT is V
_Less than _IN .

When the switches C and D switch on and off at the switching frequency f _s , the switch A remains on for each switching cycle T (t _A = T), and the switch B remains on during each switching cycle T. It remains off, and power supply 15 operates in boost mode. Duty cycle D _D switch D is _{/ t D T, / t D} T , the switch D is to become shorter on than the period T, it is smaller than 1. From equation (3), the output-input voltage ratio can be expressed as:

[0110]

(Equation 5) Since D _D is less than 1, V _OUT is equal to V in boost mode.
Greater than _IN .

[0111] During each switching frequency cycle f _s, switches A, B, if C and D are turned on in a period shorter than the period T, the power supply 15 operates in buck-boost mode. The duty cycle of each of the four switches is 1
Smaller (and greater than 0). This is because these switches are on for a period shorter than the period T in each cycle. In the buck-boost mode, the switching regulator 14 controls the switch A in each cycle.
Depending on the relative on-time (t _A and t _D ) of _D and _D , the output voltage-input voltage ratio, as shown in equation (3), is greater than, less than, or substantially equal to 1. Can be adjusted. Thus, V _OUT can be greater than, less than, or substantially equal to V _IN in buck-boost mode.

Referring again to FIG. 2B, resistors 21A and 21B form a resistor divider between V _OUT and ground. Error amplifier 22 has an inverting input coupled to the junction of resistors 21A and 21B, a non-inverting input coupled to reference voltage V _REF , and an output terminal coupled to signal generator 24. Comparator 27 includes an inverting input and a non-inverting input coupled to signal generator 24, and a logic circuit 29.
And an output terminal coupled to the output terminal. Comparator 28
Has an inverting input and a non-inverting input coupled to signal generator 24, and an output terminal coupled to logic circuit 29. Logic circuit 29 provides four logic signals (V _A , V _B , V _C and V _D ) that drive switches A, B, C and D.

The resistors 21A and 21B output the output voltage V
Form a voltage divider that produces a voltage feedback signal V _FB that is proportional to _OUT . Error amplifier 22 amplifies the difference between V _REF and V _FB to generate control voltage V _CL . Control voltage V _CL
Determines the duty cycle of these four switches. V _CL varies inversely with V _OUT and varies with changes in load current or input voltage. Therefore, V _CL is
Indirectly coupled to V _OUT through error amplifier 22 and a voltage divider.

[0114] The signal generator 24 generates two periodic waveforms V _X and V _Y having the same frequency and period. Signal generator 24 generates a waveform signal V _X which is coupled to the inverting input of comparator 27. The signal generator 24 also
Waveform signal V _Y coupled to the inverting input of comparator 28
Occurs. Period of the waveform V _X and V _Y determines the period of the switching cycle. These periodic waveforms may be, for example, symmetrical triangular waveforms as shown in FIG. 6A, or
For example, it may be an asymmetric sawtooth waveform as shown in FIGS. 6B and 6C. Signal generator 24 also generates quasi-static signals V _U and V _V that are proportional to V _CL . The signal generator 24 generates V _U at the inverting input of the comparator 27 and generates V _V at the non-inverting input of the comparator 28.

Waveform signal V_XAnd V_YOr signal V_UAnd
And V_V(Or both) are direct current (DC) offsets.
Voltage V_DCThere is a difference by minutes. Signal V_UAnd V_VAnd
Waveform V _XAnd V_YIs further described below for FIGS.
Switching regulator is in buck mode, booth
Operating in boost mode or buck-boost mode
To decide. 2C, 7 and 8A, the signal
An embodiment of the generator 24 is shown and described.

Referring again to FIG. 2B, comparator 27
Generates a control signal V _Z1 by comparing the waveform signals V _X and V _U, and this control signal V _Z1 controls switching of the switches A and B. Comparator 28, a control signal V _Z2 generated by comparing the waveform signal V _Y and V _V, the control signal V _Z2 controls the switching of switches C and D. FIG. 6A shows an example of the waveform signals V _X and V _Y and the control voltage V _CL.
It is a quasi-static signal that changes with _OUT . As shown in FIG. 6A, V _X has a period T, and has a minimum value V ₁ and a maximum value V _1.
3 is a triangular waveform having ₃ respectively. V _Y is a triangular waveform having a period T and having a minimum value V ₂ and a maximum value V ₄ , respectively. As shown in FIG. 6A, a _{V 1 <V 2 <V 3} <V 4. As described in more detail below, V ₁ <V _CL ≦
In the case of V _2, the regulator 14 controlled by the control circuit 20
Operates in the buck mode. When V ₂ <V _CL <V ₃ , the regulator 14 controlled by the control circuit 20 operates in the buck-boost mode, and when V ₃ ≦ V _CL <V ₄ ,
Operates in a boost mode. If V _CL ≦ V ₁ or V _CL ≧ V ₄ , the regulator 14
Operates in a degenerate mode. As shown in FIG.
_X and V _Y are synchronized to the in-phase state and (V ₂ −V ₁ ) =
It has a DC offset difference V _DC equal to (V ₄ −V ₃ ).

The logic circuit 29 (FIG. 2B) receives the drive signal
V_A, V_B, V_CAnd V_DOccurs. FIG._Two<
V_CL<V_ThreeControl signal V in the case of_Z1And V_Z2And the drive signal
No. V_A, V_B, V_CAnd V_DHere is an example. 6A-6D,
8B and 9C, for illustrative purposes, switch A
Is V_AIs on when is high and V_AIs low
The switch B is turned off,_BOn when is high
Becomes V_BIs low when is low, and switch C is
V_CIs on when is high and V_COff when low
And the switch D becomes V_DIs on when is high
And V_DTurns off when is low. Also, FIGS.
For D, 8B and 9C, for illustration purposes, V_A=
V_Z1, V_B= / V_Z1, V_C= V_Z2, V_D= / V_Z2It is.
V_Z1, V_Z2, And V_A, V _B, V_C, V_DOther relationships with
It is possible. For example, the non-inverting input of the comparator 27 is
V_XAnd the inverted input of the comparator 27 is V_UTied to
If combined, V_A= / V_Z1And V_B= V_Z1It is.
Further, the non-inverting input of the comparator 28 is V_YBound to
And the inverted input of the comparator 28 is V_VField that is combined with
If V_C= V_Z2And V_D= / V_Z2It is.

FIG. 2C shows a signal used in the present invention.
An example of the modulator 24 is shown. The signal generator 60 is shown in FIG.
3B, 4 and 5 used as signal generator 24
Can be The signal generator 60 includes a waveform generator 61 and a resistor.
62 and a constant current source 64. The waveform generator 61
Periodic waveform V coupled to the inverting input of comparator 28 _Y
Occurs. Control voltage V_CLIs the comparator 27 and
It is coupled to 28 non-inverting inputs. Therefore, V_UAnd
And V_YIs the V in circuit 60_CLbe equivalent to. Control voltage V
_CLIs the output voltage, for example, as shown in FIGS. 2B and 3B
Voltage feedback from V_FBMonitor signals
It may be generated by the error amplifier 22. Comparator 28
Is coupled to a first terminal of a resistor 62.
You.

The constant current source 64 is connected between the second terminal of the resistor 62 and the ground, and supplies a constant current. The inverting input of comparator 27 is coupled to a second terminal of resistor 62. Comparators 28 and 27 each have an output V _Z2
And provides V _Z1, each of these V _Z2 and V _Z1, FIG 2B, 3B, 4 and 5 of the logic circuits 29, 36,
46 or 56. The comparator 27
A control signal V _Z1 for controlling the switching of switches A and B (or only switch A in the case of the asynchronous embodiment)
Occurs. Comparator 28 includes switches C and D
(Or, in the case of the asynchronous embodiment, only switch C)
Generating a control signal V _Z2 for controlling the switching.

[0120] As shown in FIG. 2C, when the current flowing into or out of the inverting input of comparator 27 and 28 is assumed to substantially no, signal V _Y is equal to the signal V _X, thereon, by the constant current source 64 A constant negative DC offset substantially equal to the current passed adjusts the resistance of resistor 62. FIG 6A~6C shows an example of a waveform signal V _Y and V _X is generated by the signal generator 60. However, the signal V _X and V of the signal generator 60 _Y, since the signals V _X and V _Y in the circuit 60 has the same waveform and the same peak-to-peak amplitude, the signal V _X 'and V _Y in FIG. 6D May not be equal to '. The signals V _X and V _Y may be, for example, symmetric triangular waveforms or symmetric sawtooth waveforms. Figure 6 below
The discussion regarding A-6C applies to signal generator 60.

The overlap voltage (V ₃ -V ₂ ) of the signals V _X and V _Y can be expressed as:

[0122]

(Equation 6) Where V _pp is the peak-to-peak amplitude of V _Y ,
₆₄ is a current flowing by the constant current source 64, and R
₆₂ is a resistance of the resistor 62. Signal V _X have the same peak-to-peak amplitude and waveform as the signal V _Y.

In a further embodiment of the present invention, FIG.
The constant current source 64 of C replaced with resistors, can have a voltage offset that varies with respect to the signal V _Y to the signal V _X. In this embodiment, signals V _X and V
_Y has different peak-to-peak amplitudes.

Referring again to FIG. 2B, logic circuit 29
Drive switches A, B, C and D on and off
Drive circuit. V_Z1Goes high, the logic circuit 29
Is the logical signal V_ATo a high level and the logic signal V_BTo low,
The switch A is turned on and the switch B is turned off. V_Z1But
, The logic circuit 29 outputs the logic signal V_ATo low
And the logic signal V_BTo high, switch A off, switch
Turn on switch B. V_{Z Two}Goes high, the logic circuit 2
9 is a logic signal V_CTo a high level and the logic signal V_DTo low
Then, the switch C is turned on and the switch D is turned off. V_Z2
Becomes low, the logic circuit 29 outputs V_CTo low and V_D
High, switch C off, switch D on
You.

FIG. 2D shows an example of the logic circuit 29 used in the control circuit 20. The logic circuit 29
D gates 150, 152, 160 and 162 and inverters 151, 153, 154, 155, 161,
It has a plurality of logic gates including 163, 164 and 165. In FIG. 2D, switches A and D are shown as P-channel field effect transistors (FETs), and switches B and C are shown as N-channel FETs. Referring to FIG. 2D, switch A is turned on when _VA goes low and off when _VA goes high. Switch B is
When V _B goes high is turned on, V _B is turned off becomes low. Switch C, V _C is turned on becomes high, V _C
Is turned off when goes low. Switch D is turned on when V _D is low, V _D is turned off becomes high. In a further embodiment of the present invention, switches AD may all be N-channel FETs.

Inverters 153, 154 and 155
Is an inverter 163 coupled between V _IN and ground,
164 and 165 are coupled between V _OUT and ground. Inverter 151 has an input coupled to V _Z1 and N
And an output coupled to a first input of AND gate 152. NAND gate 150 has a first input coupled to V _Z1 , a second input coupled to the output of NAND gate 152, and an output coupled to the input of inverter 153. Inverter 153 includes inverter 154
Has an output coupled to its input. Inverter 154
Has an output coupled to the second input of NAND gate 152 and the gate of transistor A. NAND gate 152 has an output coupled to the input of inverter 155. Inverter 155 has an output coupled to the gate of transistor B. The inverter 161 is
An input coupled to V _Z2 and a first input of NAND gate 162.
And an output coupled to a first input of NAND gate 160. NAND gate 162 is connected to NAN
It has an output coupled to a second input of D-gate 160, and an input of inverter 165. The inverter 165
It has an output coupled to the gate of transistor C. N
AND gate 160 has an output coupled to the input of inverter 163. Inverter 163 has an output coupled to the input of inverter 164. Inverter 1
64 has an output coupled to the second input of NAND gate 162 and the gate of transistor D.

The logic circuit 29 shown in FIG.
And a short dead time between the time when B and B turn on and the time when switches C and D turn on,
Avoid that switches A and B are turned on at the same time,
Avoid that switches C and D are turned on at the same time. When V _Z1 goes low, for example, as shown in FIG. 6A, transistor A is turned off and transistor B is turned off.
Turns on. When V _Z1 goes high, the inverter 151
Goes low, then the output of NAND gate 152 goes high, then the output of inverter 155 goes low, and n-channel FET B turns off. NAN
When the output of D gate 152 goes high, the output of NAND gate 150 goes low, then the output of inverter 153 goes high, then the output of inverter 154 goes low, and p-channel FET A turns on. V _Z1
Rising edges of logic gates 151, 152, 15
0, 153, and then 154, and the FET A
Is longer than the time required for the rising edge of V _Z1 to propagate through logic gates 151, 152, then 155, and turn off FET B in turn.
Because, in the former case, the signal is 2 more than in the latter case.
This is because it must pass through two more logic gates.

When V _Z1 transitions low, the output of NAND gate 150 goes high, then the output of inverter 153 goes low, then the output of inverter 154 goes high, and p-channel FET A turns off. . When the output of the inverter 154 goes high and the output of the inverter 151 goes high, the output of the NAND gate 152 goes low, then the output of the inverter 155 goes high, turning on the n-channel FETB. The falling edge of V _Z1 is applied to logic gates 150, 153, and 15
4 sequentially turns off p-channel FET A, and sequentially passes through logic gates 150, 153, 154, 152 and 155, turning on n-channel FET B. Therefore, on the falling edge of V _Z1, the time required to turn on FET B is greater than the time required for turning on FET B.
It is longer than the time required to turn off A. Therefore, F
A short dead time is provided between the times when ET A and B are turned on.

The logic gates 160 to 165 are also provided with FETs.
Create a short dead time between the time C and D are turned on to avoid turning on these FETs at the same time. The rising edge of V _Z2 passes through four logic gates (in the order of 161, 160, 163 and 164) to turn off p-channel FET D, and passes six logic gates (161, 160, 163, 164, 164). 162 and 165 in that order) to turn on n-channel FET C. The falling edge of V _Z2 passes through the two logic gates (in order of 162 then 165) to turn off n-channel FET C and to pass the four logic gates (162,
160, 163 and 164 in turn) to turn on p-channel FET D.

The power supply 15 inputs all four switches.
Requires lower average inductor current than prior art buck-boost switching regulators that switch regardless of output voltage relationship. Average inductor current / I _IND and power supply 1
The relationship between the average output current / I _{OUT in} 5 and the average can be expressed as:

[0131]

(Equation 7)For example, V_IN= V_OUTAnd t_ADIf> 0, average inductance
Current / I_INDIs less than half the average output current. Time
Interval t_ADBuck mode, boost mode, and
In boost mode, the waveform V_YAnd V_XD during
C offset voltage V _DC(That is, (V of FIGS. 6A to 6D)
_Two-V₁If)) is greater than zero, greater than zero
No. Therefore, the power supply 15_DC> 0
Low compared to the buck-boost switching regulator of the control circuit
Requires average inductor current. V_DCAnd hence t
_ADIs equal to zero, the average in the synchronous switching regulator 14
The inductor current is calculated according to equations (1) and (7).
Is defined as

With reference to FIG. 3A, another control circuit according to the present invention will be described. The power supply 35 includes an asynchronous buck-boost switching regulator 30 and a control circuit 38. Asynchronous switching regulator 30 receives input voltage V _IN and produces a regulated output voltage V _OUT . Input voltage V _IN may be higher, lower, or substantially the same as output voltage V _OUT . The control circuit 38 may operate the switching regulator 30 in a buck mode, a boost mode, or a buck-boost mode. Asynchronous switching regulator 30 has two switches coupled between V _IN and V _OUT that control the supply current to the output node at V _OUT so that the output voltage can be held at a regulated value. Control circuit 38
Receives the output voltage V _OUT, and controls the asynchronous switching regulator 3
It provides two drive signals (V _A and V _C ) that control the switching of two switches within zero.

Referring to FIG. 3B, the power supply circuit of the present invention
5 is a schematic diagram. The circuit 35 includes an asynchronous switching regulator 30 having two switches (A and C) and a control circuit 38. In the switching regulator 30, the diode 3
2 and 34 replace the synchronous switches B and D of FIG. 2B, respectively. The diode 32 is connected to the switch A
Has a cathode coupled to the second terminal and an anode coupled to ground. Diode 34 has a cathode coupled to capacitor 18 and an anode coupled to inductor 17.

Control circuit 38 of FIG. 3B differs from control circuit 20 of FIG. 2B except that logic circuit 36 provides two drive signals (V _A and V _C ) to control control switches A and C, respectively. Is the same. When switch A is turned on,
Diode 32 is reverse biased and conducts very little current. When the switch A is turned off, the diode 32
Are forward biased and allow current to flow from ground through inductor 17. When the switch C is turned on, the diode 34
Are reverse biased and carry negligible current. When switch C is turned off, diode 34 is forward biased and conducts current from inductor 17 to V _OUT .

Thus, when switches A and C are on, diodes 32 and 34 are reverse biased,
Current flows through inductor 17 between V _IN and ground. When switch A is turned on and switch C is turned off, diode 32 is reverse biased, diode 34 is forward biased and current flows through inductor 17 between V _IN and V _OUT . Switches A and C
Are turned off, diodes 32 and 34 are forward-biased and current flows through inductor 17 to ground and V
It flows between _OUT . When switch A turns off and switch C turns on, diode 32 is forward biased, diode 34 is reverse biased and the current through inductor 17 does not change because both terminals are coupled to ground. . The control circuit 38 of FIG.
Depending on the value of V _CL as discussed with reference to FIG. 6D, the asynchronous switching regulator 30 may be switched to buck mode, boost mode,
Or it can be operated in buck-boost mode.

Referring to FIG. 4, another control circuit according to the present invention will be described. Power supply 40 is an asynchronous switch A
, A switching regulator 42 having diodes 32 and synchronous switches C and D. The control circuit 44 of FIG.
The logic circuit 46 has three drive signals (V _A , V _C and V _D ).
2B except for controlling the switches A, C and D, respectively. In the control circuit 44, the comparator 27 controls the switching of the switch A, and the comparator 28 controls the switching of the switches C and D. The control circuit 44 of the present invention operates the switch regulator 42 in buck, boost, or buck-boost mode in the same manner as discussed with reference to FIGS. 6A-6D, depending on the value of V _CL . obtain.

FIG. 5 shows another example of a buck-boost switching regulator having two synchronous switches, an asynchronous switch, and a diode. 5 includes a switching regulator 52 and a control circuit 54. Switching regulator 52
Are synchronous switches A and B, diode 34,
And an asynchronous switch C. The control circuit 54 is the same as the control circuit 20 of FIG. 2B except that the logic circuit 56 outputs only three drive signals (V _A , V _B and V _C ) to control the switches A, B and C, respectively. It is. In the control circuit 54, the comparator 27 controls switching of the switches A and B, and the comparator 28 controls switching of the switch C. The control circuit 54 of the present invention may cause the switching regulator 52 to operate in a buck, boost, or buck-boost mode in the same manner as discussed with reference to FIGS. 6A-6D.

The signal generator 24 includes the control circuits 20, 38,
44 and 54, the waveform signal V _XAnd V_YAnd quasi-static
Signal V_UAnd V_VAnd generate. Shown in FIGS. 6A-6C
Waveform V_XAnd V_Y(And V in FIG. 6D)_X'and
V_Y') For use with power supplies 15, 35, 40 and 50
You can be. 6A to 6D are switching regulator circuits of the present invention.
Of a periodic waveform having a period T, which can be used in
Here are two examples. Another type of waveform (for example, rising edge
Edge and asymmetric sawtooth waves with gentle falling edges
Shape) can also be used.

FIGS. 6A to 6D also show control voltages V _CL , control signals V _Z1 and V _Z2 , and drive signals _VA , V _B , V _C during the three operating modes (buck, boost and buck boost). , and showing an example of the V _D. The value of V _CL is
Determine the active steady state mode of operation. Referring to FIGS. 6A-6D, V _U and V _V are both equal to V _CL during each period T, for example, as shown in FIGS. Alternatively, referring to FIGS. 6A to 6D, V _DC is (V ₂ −V ₁ ) = (V ₄
−V ₃ ). These three active steady state operating modes are buck (V ₁ <V _CL ≦ V ₂ ), buck boost (V ₂ <V _CL <V ₃ ), and boost (V ₃ ≦ V _CL <
V ₄ ). 6A-6D, diodes 32 in regulators 30 and 42 are forward biased when switch B is on and reverse biased when switch B is off. .
Further, the diodes 34 in the regulators 30 and 52
When switch D is turned on, forward bias is applied,
When the switch D is turned off, reverse bias is applied.

FIG. 6A shows two values of the control voltage V _CL (V
Exemplary waveforms V _Y and V _X and the signal V _Z1 for _CL1 and _{V CL2), V Z2, V} A, V B, shows a V _C, and V _D. The operating mode of the switching regulator circuit of the present invention is determined by the value of the control voltage V _CL and the voltage levels V ₁ , V ₂ , V ₃ and V ₄ . Waveform V _X and V _Y are symmetrical triangular waveform for the period T. Signals V _Z1 , V _Z2 , V _A , V _B , V
The values of _C and V _D are shown by solid _lines when V _CL = V _CL1 ,
The case where V _CL = V _CL2 is indicated by a dotted line.

FIG. 6A shows the case of the buck-boost mode.
1 shows an example of the present invention. As shown in FIG._Xand
V_YAre both V_CLSignal V_Z1And V_Z2
Goes high and the signal V_AAnd V_CIs high (that is,
Switches A and C are on) and signal V_BAnd V_DIs
It goes low (ie, switches B and D are off).
V_YIs V_CLAnd V_XIs V_CLIf less than V_Z1Is
High and V_Z2Goes low and V_AAnd V_DIs high
(That is, switches A and D are turned on), and V_B
And V_CIs low (ie, switches B and C are off).
F). V_XAnd V_YAre both V_CLPlace to exceed
If V_Z1And V_Z2Goes low and V_BAnd V _DIs high
(Ie, switches B and D are turned on) and V_A
And V_CIs low (ie, switches A and C are off).
F). In the case of buck-boost mode,
To turn all switches on and off
Power is needed.

When the output-to-input voltage ratio of regulator circuit 14, 30, 42 or 52 changes, switches A, B, C and D (and / or diodes 32 and 34)
Also changes accordingly. For example, in the power supply circuit 15 of FIG. 2B, when V _IN decreases in the buck-boost mode, the output-input voltage ratio increases. As V _IN decreases, for a given duty cycle of these switches, the error amplifier 22 senses a slight decrease in V _OUT because the current into the load 19 in each period T decreases. As V _OUT decreases, V _CL increases. As can be seen from FIG. 6A, as V _CL increases to V _CL2 , the off time of V _Z1 decreases and the on time of V _Z2 increases. This increases the on-time of switches A and C and decreases the on-time of switches B and D. Thus, the control circuit of the present invention adjusts the duty cycle of the switch to maintain V _OUT at the adjusted value.
This duty cycle satisfies the relationship in equation (3), assuming ideal components.

According to [0143] the present invention, the output switching regulator operates in buck-boost mode - the input voltage ratio range is dependent on the overlap of the voltage waveform V _X and V _Y. FIG.
As shown in A～6D, the voltage overlap V _X and V _Y is the region (V ₃ -V _2). As the voltage overlap increases, the range of the output-to-input voltage ratio at which the control circuit of the present invention operates the switching regulator in buck-boost mode increases. As the voltage overlap decreases, the range of the output-to-input voltage ratio at which the control circuit of the present invention operates the switching regulator in buck-boost mode decreases.

The overlap is maximum (ie, V _DC =
When 0, and therefore V ₁ = V ₂ and V ₃ = V ₄ ), the control circuit operates the switching regulator in buck-boost mode at all output-to-input voltage ratios. In this case, switches A and D are not turned on at the same time, and the switching sequence is such that A and C are turned on, B and D are turned on, A and C are turned on, and B and D are turned on. It is.

The maximum overlap has several disadvantages. First, because t _AD is equal to zero, as shown in equation (7), the average inductor current is large for a given output current and output-input voltage ratio.
Second, in each period T, the switching regulator is disabled because all switches are on and off regardless of the output-input voltage ratio. Thus, any overlap less than the maximum overlap condition (V _DC > 0) allows the switching regulator to operate in buck, boost, and buck-boost modes, thereby increasing efficiency and increasing inductor efficiency. Reduce current.

If V _X and V _Y do not overlap at all (ie, V ₃ ≦ V ₂ ), the switching regulator does not operate in buck-boost mode. In this situation, if V _CL is greater than V ₃ and less than V ₂ , switch A
And D are on throughout each period T, and no switching occurs because the input and output nodes are coupled through an inductor (V _IN = V _OUT ). in this case,
The output voltage V _OUT is not adjusted to a constant value. If V _CL crosses any of these waveforms, buck and boost modes still exist.

The voltage overlap (V ₃ -V ₂ ) can be used to adjust the desired behavior of the switching regulator. For maximum efficiency, there should be no overlap of the waveforms (so that the voltage overlap is less than zero, ie, V ₃ ≦ V ₂ ) and the operation in buck-boost mode should be eliminated. However, in this case, there is an operation region where the control of the output-input voltage ratio by V _CL is invalid. This occurs when the input voltage is substantially equal to the output voltage. In the system configuration shown in FIG. 2B, the waveforms do not overlap (that is, V ₃ ≦ V ₂ ) and V
_{If OUT} ≒ V _IN , V _CL shifts rapidly between buck and boost modes to find a constant duty cycle for the switch. An output-to-input voltage ratio close to one does not always have one control voltage level that can accommodate this condition. Therefore,
The system behaves in a hysteretic manner to shift between buck and boost modes. This behavior is usually undesirable.

As the voltage overlap (V ₃ −V ₂ ) increases above zero, the input voltage range over which the regulator operates in the relatively inefficient buck-boost mode increases, but the mode buck mode is described above. The hysteretic mode described for the transition between and boost mode is eliminated. This makes the larger output-input voltage ratio range inefficient, but improves the transition behavior. Further, when the voltage overlap (V ₃ -V ₂₎ is larger than zero, any output at a constant switch duty cycle (the case of constant load current) - to hold the input voltage ratio.

FIG. 6B shows alternative waveforms V _X and V _Y where V ₃ ≦ V _CL <V ₄ and thus the regulator operates in boost mode. Waveforms V _X and V _Y in FIG. 6B are sawtooth waveform signals having a sharp rising edge and a period T. As long as V _CL is not less than V _3, V _CL is always waveform V _X
Higher, V _Z1 is high for the entire period T of each switching cycle. Thus, in the boost mode, V _A over the entire period T of each switching cycle is high, the switch A is turned on, V _B is low,
Switch B is off. The comparator 28 switches on and off the switches C and D in the boost mode in the power supplies 15 and 40 and the power supplies 35 and 5
It controls on / off switching of the switch C in the boost mode within 0. If V _Y is above V _CL , V _Z2 will be low and V _D will be high, thereby causing switch D
Is turned on, V _C goes low, the switch C is turned off thereby. If V _Y falls below V _CL , V _Z2 goes high, V _C goes high, causing switch C to turn on and V _D to go low, thereby turning off switch D.

FIGS. 6A and 6B show peak-to-peak amplitudes.
Waveform V of equal width_XAnd V_YHere is an example. FIG. 6A and
V at 6B_XWhere the peak-to-peak amplitudes of
6A and 6B_YThe peak-to-peak amplitude of
Equal to the voltage overlap in FIGS. 6A and 6B
(V_Three-V_Two) Are equal and the time t_AD, T_BD, And
And t_ACIs V in FIG. 6A._XAnd V_YThe shape (triangle) of Fig. 6
V of B_XAnd V_Y(Sawtooth)
Given V in two steady state condition embodiments _CLIn
And equal. In this case, switches A and D
Only the on-time of the output of a steady state as shown in equation (3)
6A and 6A to relate to the determination of the force-to-input voltage ratio.
The steady-state output-input voltage ratio of B is the same. these
The switch on-time sequence of the two embodiments is different.
Become. In FIG. 6A, in the case of the buck-boost mode,
Switching repetition sequence turns on AD and turns on BD
Turn on AD, turn on AC, and so on.
You. In FIG. 6B, the switch for the buck-boost mode
The permutation repetition sequence turns on AD, turns on AC,
For example, the BD is turned on.

FIG. 6C shows yet another waveform V _{X in} which the regulator operates in buck mode because V ₁ <V _CL ≦ V _2.
And shows a V _Y. The waveforms V _X and V _Y in FIG. 6C are sawtooth waveform signals having a fast falling edge and a period T. If V _CL does not exceed V ₂ , waveform V _Y will always be V
V _Z2 in power supplies 15, 35, 40, and 50, which is greater than _CL , is low during the entire period T of each switching cycle. Accordingly, V _C goes low, thereby, the switch C is turned off over the entire period T of each cycle,
V _D goes high, causing switch D to turn on in buck mode for the entire period T of each cycle. Comparator 27 controls the on / off switching of buck mode switches A and B in power supplies 15 and 50, and controls the on / off switching of buck mode switch A in power supplies 35 and 40. If V _X is above V _CL , V _Z1 is low and V _B is high, causing switch B to turn on and _VA low, thereby turning switch A off. V _X is V
If below _CL , V _Z1 goes high and _VA goes high,
Thus the switch A is turned on, V _B goes low, thereby switching B is turned off.

FIG. 6D is used in the control circuit of the present invention.
Another waveform signal V that can be obtained_X'And V_Y'Is shown below. Faith
The signal generator 24 outputs the waveform signal V_XAnd V_YInstead of waves
Shape signal V_X'And V_Y'Respectively. Signal
The waveform signals generated by the generator 24 must be identical
And do not have the same waveform. As shown in FIG. 6D
And V_X'Is a symmetrical triangular waveform, and the waveform V_Y′ Is asymmetric
It is a sawtooth waveform. Both of these waveforms have a period T
I do. V_X'Peak-to-peak amplitude (V_Three-V ₁)
V_Y'Peak-to-peak amplitude (V_Four-V_TwoLarger than)
No.

The buck-boost switching regulator controlled by the control circuit of the present invention with the waveforms V _X ′ and V _Y ′ of FIG. 6D, as described above in FIGS. 6A to 6C, can be in buck mode, boost mode, or buck-boost mode. Can work in mode. Equation (3) also applies to the control circuit of the present invention having a waveform and peak-to-peak amplitude is different waveforms V _X 'and V _Y'. Preferably, the waveform V _X 'and V _Y', the switch B and C are turned on at the same time (i.e., a V _CL> V _Y 'and V _CL <V _X') as never, do not cross each other To be selected.

Referring to FIGS. 6A-6D, two "degenerate"
The mode is shown. The degeneration mode occurs when the control voltage V _CL is lower than V ₁ or when V _CL is higher than V ₄ .
If V _CL is less than V ₁ , V _Z1 and V _Z2 will both remain low and switches B and D will be on all the time in cycle T of each cycle (if V _A = V _Z1 , V _B
= / V _Z1 , V _C = V _Z2 , and V _D = / V _Z2 ). This mode discharges the output voltage through inductor 17 to ground. In the second degenerate mode, V _CL is greater than or _equal to V ₄ , V _Z1 and V _Z2 both remain high, and switches A and C are on during period T of each cycle (V _A = V _Z1 , V _B = / V _Z1 , V _C = V _Z2 ,
And V _D = / V _Z2 ). In this mode, the inductor 17
To short the input voltage to ground through
Usually not desirable. These degeneration modes are not used to adjust V _OUT . Both of these modes are considered degenerate only when switches A and C are both turned on for the entire period of period T or when switches B and D are both turned on for the entire period of period T.

FIG. 7 shows an example of a signal generator 24 capable of generating waveforms V _X ′ and V _Y ′ having different waveforms and peak-to-peak amplitudes. The signal generator 65 is shown in FIGS.
B, 4, and 5 signal generators 24.
The signal generator 65 includes waveform generators 66 and 68 and an oscillator 67. In the circuit 65, the signal V _U and V _V are respectively generated in the non-inverting input of comparator 27 and 28. Signals V _U and V _V are equal to V _CL in FIG. Waveform generator 66 generates a waveform V _X 'at the inverting input of comparator 27, the waveform generator 68
Generates a waveform _VY 'at the inverting input of comparator 28. Waveforms V _X ′ and V _Y ′ can have different waveforms and different peak-to-peak amplitudes, for example, as shown in FIG. 6D. Oscillator 67 generates a periodic signal at node 69 that is received by waveform generators 66 and 68. Periodic signal at node 69 synchronizes the period T of the waveform V _X 'and V _Y', thereby, the period of these waveforms begin and end at the same time. For example, waveform generators 66 and 68 are connected to node 69
It may begin each period of the waveform V _X 'and V _Y' at the rising edge of the digital signal in. If desired, the waveform V _X 'and V _Y' in FIG. 7, DC offset voltage _{V DC = (V 2 -V 1} ) = (V 4 -V 3) For the same waveform and the same peak-to-peak amplitude May be provided.

FIG. 8A shows a further embodiment of the signal generator according to the invention. The control circuit comprising the signal generator of FIG. 8A is also used to generate control signals for a synchronous buck-boost switching regulator, an asynchronous buck-boost switching regulator, and a synchronous / asynchronous buck-boost switching regulator. obtain. The signal generator 70 of FIG.
3B, 4 and 5 may be used instead of signal generator 24. The signal generator 70 includes a waveform generator 71 and a resistor 7
6 and a constant current source 78. Waveform generator 71 generates a periodic waveform V _W at the inverting input of comparator 27 and 28. Waveform V _W is equal to V _X and V _Y. The control voltage V _CL may be generated from an error amplifier 22 that monitors a voltage feedback signal V _FB , for example, as shown in FIGS. 2B and 3B. V _CL is coupled to the non-inverting input of comparator 27 (whereby V _U equals V _CL ) and to a first terminal of resistor 76. Constant current source 78
Is coupled between the second terminal of resistor 76 and ground;
Apply a constant current. The non-inverting input of comparator 28 is coupled to a second terminal of resistor 76. The comparator 27
It generates a control signal V _Z1, the control signal V _Z1 controls the switching of switches A and B, or, in the embodiment of asynchronous, controls only the switch A. Comparator 28 generates a control signal V _Z2, the control signal V _Z2 is
It controls the switching of switches C and D or, in the case of an asynchronous embodiment, controls only switch C.

The signal generator 70 is a comparator 2 which is offset from V _CL and V _U by a fixed value in the negative direction.
Generating a voltage V _V at the non-inverting input of the 8. Runoff and inflow of current at the non-inverting input of comparator 27 and 28 is assumed that there is no constant offset between the V _U and V _V is a resistance to the current flowing through the constant current source 78 resistor 76 Equivalent to multiplying. V _V can be expressed as:

[0158]

(Equation 8) Here, I ₇₈ is a current flowing from the constant current source 78, and R ₇₆
Is the resistance of the resistor 76. Thus, the offset voltage _VDC is V _U − for the embodiment of FIGS. 8A-8B.
Equal to V _V.

[0159] Figure 8B shows an example of a signal V _W which are generated by the waveform generator 71. The signal V _W has a maximum value V ₆ and a minimum value V ₅ . FIG. 8B shows the signals V _U , V _V , V _Z1 ,
Examples of V _Z2 , V _A , V _B , V _C , and V _D are also shown. Switching regulator which is controlled by a control circuit with a signal generator 70, when V _U and V _V are both exceeds and V ₅ below V _6, operates in buck-boost mode. In the buck-boost mode, the control signals _VZ1 and _VZ2
Controls the on / off switching of each of these switches.

If V _U is greater than V ₆ and V _V is less than V ₆ , the switching regulator controlled by signal generator 70 is
V _Z1 and V _A are high, V _B is low, switch A is on, and switch B is off during the entire period of each cycle, operating in boost mode. The control signal V _Z2 controls on / off switching of the switches C and D in the boost mode. V _V is a V ₅ or less, if the V _U exceeds V _5, switching regulator which is controlled by the signal generator 70, V in the entire period of each cycle _Z2
And V _C are low, V _D is high, and switch C
Is off and the switch D is on, so it operates in buck mode. The control signal V _Z1 controls on / off switching of the switches A and B in the back mode.
Referring to FIG 8B, the switch A is turned on when V _W is less than V _U, and turned off when the V _W exceeds V _U. The switch B is turned on when V _W exceeds V _U , and V _W
There turned off in the case of less than V _U. Switch C sets V _W to V
Turned on when less than _V, and turned off when the V _W exceeds V _V. Switch D is turned on when the V _W exceeds V _V, V _W is turned off in the case of less than V _V. If V _U and V _V ≧ V ₆ or V _U and V _V ≦ V ₅ , the switching regulator operates in a degenerate mode.

In a further embodiment of the present invention, the constant current source 78 can be replaced by a resistor, thereby providing V _V
V _V is generated such that is part of V _CL and V _U.
In this embodiment, the offset voltage between V _U and V _V varies according to changes in V _CL.

The propagation delay of a comparator is the time required for its output signal to reach half of the supply voltage after its differential input voltage difference passes through zero. There are two types of propagation delays: t _PLH is the propagation delay when the output of the comparator transitions from low to high;
t _PHL is the propagation delay when the comparator output transitions from high to low. The propagation delay of a comparator can vary with overdrive (differential input voltage difference) and the time between transitions in the output signal of the comparator. For example, a larger overdrive at the input of the comparator may result in a shorter propagation delay than a smaller overdrive. The propagation delay of the comparator in the pulse width modulator changes most when the control voltage input approaches the minimum and maximum voltages of the periodic waveform input to the comparator. Variations in the propagation delay of the comparator output signal can adversely affect the ability of the pulse width modulator to accurately control the duty cycle of the switches in the switching regulator.

FIG. 9A shows a further embodiment of the pulse width modulator of the present invention. The pulse width modulator 80 of FIG.
2B, 3B, 4 and 5 may be used in place of the pulse width modulator 25. 9A pulse width modulator circuit 80
_Produces a substantially constant propagation delay in the control signals _VZ1 and VZ2 with a duty cycle of 0% to 100% of the switch. Pulse width modulator 80 generates signals V _Z1 and V _Z2 using two waveform generators, each generating a periodic waveform signal, two comparators, and two multiplexers. Each of these multiplexers outputs the output of one of these comparators to signal V if the waveform signal generated by the waveform generator coupled to one of the comparators is not within 1% of its minimum or maximum voltage. Select as _Z1 and V _Z2 .
This percentage is determined by the selection signals V _S1 and V _S2 . This technique is useful to ensure a substantially constant propagation delay in control signals V _Z1 and V _Z2 . For further details of a linear pulse width modulation system, see U.S. Patent Application No. (Patent attorney no .: LT-107)
There is a description. In this specification, the entire disclosure content of the application is incorporated by reference.

The pulse width modulator 80 is shown in FIGS.
And 5 may be used in place of the pulse width modulator 25. The pulse width modulator 80 includes a signal generator 81, comparators 84 and 86, and multiplexers 88 and 9
0 is included. Signal generator 81 provides a waveform signal V _M to the inverting input of the comparator 84, provides a waveform signal V _N to the inverting input of comparator 86. Control voltage V _CL is coupled to signal generator 81 as an input signal. V _CL may be generated from an error amplifier 22 that monitors a voltage feedback signal V _FB , for example, as shown in FIGS. 2B, 3B, 4, and 5. The signal generator 81 also has a quasi-static signal V
_J is provided to the non-inverting input of comparator 84 and the quasi-static signal V _K is provided to the non-inverting input of comparator 86.

Comparator 84 provides a signal V _R at its output, and comparator 86 provides a signal V _Q at its output. The output of comparator 84 is coupled to the input terminals of multiplexers 88 and 90 at node 87. The output of comparator 86 is coupled to the input terminals of multiplexers 88 and 90 at node 89. Select signal V _S1 is coupled to the S input of multiplexer 88, and select signal V _S2 is coupled to the S input of multiplexer 90. The output of multiplexer 88 provides control signal V _Z1 . The output of multiplexer 90 provides control signal V _Z2 .

[0166] waveform signal V _M and V _N has the same shape and the same period T, are each other by a time delay half of the period T. 9C shows an example of the signal V _M and V _N. The signal generator 81 may also generate other types of periodic waveforms, for example, a sawtooth waveform with steep rising edges and a sawtooth waveform with no steep rising and falling edges.

The signal generator 100 shown in FIG. 9B is a signal generator.
81 is an example. The signal generator 100 is shown in FIG. 9C.
Periodic sawtooth with such a sharp falling edge
Type V _MAnd V_NGenerate Waveform V_MAnd V_NFigure 9
V as shown in C_MAXAnd V_MINTo change between. Signal
The livelihood 100 also has a quasi-static signal V_JAnd V_KProduces
Each of these signals is V_CLLike
New The waveform generator 100 includes a clock signal generator 104
, Constant current sources 101 and 106, and capacitor 102
And 107 and an n-channel MOS field effect transistor
Stars 103 and 108, one shot 104 and
109. The constant current source 101 has a supply voltage V_CCTied to
A combined first terminal and a first end of the capacitor 102.
, The drain of transistor 103 and V_NBound to
A second terminal. Capacitor 102 is grounded
Having a second terminal coupled to
Has a source coupled to ground. Constant current source 106
Is the supply voltage V_CCA first terminal coupled to the
The first terminal of the transistor 107, the drain of the transistor 108
And V_MAnd a second terminal coupled to the second terminal. Capacity
Sita 107 has a second terminal coupled to ground, and
Transistor 108 has a source coupled to ground
You. Clock signal generator 104 is at node 110.
Connected to the input terminals of the one shots 104 and 109
Output terminal. One shot 104
Having an output coupled to the gate of
Unit 109 is coupled to the gate of transistor 108.
Output.

The clock signal generator 104 is connected to the node 11
Generate a square wave digital clock signal with a 50% duty cycle that changes between high and low at zero. During each cycle of the clock signal, constant current source 101 charges capacitor 102 from V _MIN to V _MAX , and constant current source 106 charges capacitor 107 from V _MIN to V _MAX . When the clock signal goes high, the signal at the output of one shot 104 goes from low to high, thereby turning on transistor 103. Then, the voltage at V _N on capacitor 102 is V _MAX
To V _MIN . The output of one shot 104 is high for only a short time (eg, node 110
At 1% of the time the clock signal stays high). The output of the one-shot 104 then transitions low, turning off the transistor 103. Next, the constant current source 101
Starts charging the capacitor 102 again. The output of one shot 104 remains low until the next rising edge of the clock signal.

When the clock signal goes low, the signal at the output of one shot 109 goes from low to high, thereby turning on transistor 108. Then, the voltage at V _M of capacitor 107 is from V _MAX to V _MIN
Down to. The output of one-shot 109 is high for only a short time (eg, 1% of the time the clock signal at node 110 is low). One shot 109
Output then transitions low and transistor 108 turns off. The constant current source 106 is a capacitor 107
Start charging again. The output of one shot 109 is
It remains low until the next falling edge of the clock signal.

FIG. 9C also illustrates exemplary logic signals V _R , V _Q ,
V _Z1 , V _Z2 , V _S1 and V _S2 are shown. Signal V _Z1 controls the switching of switches A and B, and signal V _Z2 controls switch C, as described with respect to the above embodiment of the invention.
And D switching. The comparator 84 outputs V
By comparing the _J and V _M to generate the V _R. If V _J is greater than V _M, V _R becomes high. If V _J is less than V _M , V _R will be low. Comparator 86 determines V _K and V _N
To generate V _Q. If V _K is greater than V _N, V _Q is high. If V _K is smaller than V _N ,
V _Q is low. The selection signals V _S1 and V _S2 are the signals V _R
And V _Q are selected as V _Z1 and V _Z2 to be passed at predetermined time intervals during the period T using the multiplexers 88 and 90. In the examples of FIGS. 9B and 9C, V _CL is equal to V _J and V _K.

Referring to FIG. 9C, if V _CL is less than V _{4 and} greater than V ₃ , the switching regulator operates in boost mode. If V _CL is less than V ₃ and greater than V ₂ , the switching regulator operates in buck-boost mode. If V _CL is less than V ₂ and greater than V ₁ , the switching regulator operates in buck mode. As described below, the values of V ₁ and V ₃ are determined by the falling and rising edges of signal V _S1 , and the values of V ₂ and V ₄ are determined by the falling and rising edges of signal V _S2 . It is determined.

[0172] portion smaller larger moiety and V ₁ than V ₄ of the signal V _M and V _N, the control signal V _Z1 and V
Not used to generate _Z2 . Because the maximum percentage of the peak-to-peak amplitude of V _CL is V _M and V _N (e.g., 90%) than the minimum percentage of the peak-to-peak amplitude of greater than or V _M and V _N (e.g., l0%) Is also small, the propagation delay of the comparators 84 and 86 can change. Therefore, the selection of the signal V _S2 is determined by (comparators 84 and 86
The propagation delay can vary) maximum percentage of the peak-to-peak amplitude of V _M and V _N (eg, V than 90%)
₄ is made smaller. The selection of the signal V _S1
(Propagation delay of the comparators 84 and 86 may be different) minimum percentage of the peak-to-peak amplitude of V _M and V _N (e.g., 10%) is carried out as V ₁ is greater than.

Referring to FIG. 9C, V_CLIs V_FourIs over
In this case, the switching regulator switches the inductor 17 during each period T.
Operates in a degenerate mode that couples the input voltage to ground through
You. V _CLIs V₁If not, the switching regulator
Output voltage is coupled to ground through inductor 17 during T
Operate in degenerate mode.

Selection signal V_S1And V_S2Is shown in FIG. 9C
Such a digital signal. Selection signal V_S1Is no
Which of the multiplexers 88 and 89
Determines whether to combine with the output. Selection signal V_S1Is multi
The waveform signal V _MIs V₁And V_ThreeBetween
Signal at node 87_RIs the control signal V_Z1age
And send the waveform signal V_NIs V₁And V_ThreeWhen there is between
The signal V_QIs the control signal V_Z1Send as
You. Waveform signal V_MAnd V_NIs V₁And V_FourPlace between
The propagation delay of the comparator coupled to the waveform signal
t_PHLIs V_RAnd V _QTo low transition at
Is V_Z1Are used to form
And is substantially constant. Of comparators 84 and 86
Propagation delay t_PLHNeed not be substantially constant. What
If so, V_Z1Low-to-high transition at V_R
And V_QRather than a low-to-high transition at_S1
Is formed by the transition in. But,
Signal V_RAnd V_QIs V_RAnd V_QIs V_Z1Again selected as
Should transition from low to high before being selected.

Select signal V _S2 determines which of nodes 87 and 89 is coupled to the output of multiplexer 90. Selection signal V _S2 is a multiplexer 90, causing it to send a signal V _R at node 87 as a control signal V _Z2 when the waveform signal V _M is between V ₂ and V _4, the waveform signal V _N is the V ₂ If there between V _4, to send a signal V _Q at node 89 as a control signal V _Z2. When the waveform signals V _M and V _N are between V ₁ and V ₄ , the propagation delays t _PHL of the comparators coupled to the waveform signals are substantially constant with respect to each other. Since the transition from high in V _R and V _Q to low is because it is used to form a V _Z2. The propagation delay t _PLH of the comparators 84 and 86 need not be substantially constant. This is because the low-to-high transition at V _Z2 is formed by a transition at V _S2 , not a low-to-high transition at V _R and V _Q. However, the signal V _R and V _Q, before V _R and V _Q are again selected as V _Z2, should transition from low to high.

V_S1Is high, the output of comparator 84 is
The force is coupled to the output of multiplexer 88 and V_MIs
As shown in FIG.₁And V_ThreeBetween. Where
No. V_{Z 1}Is the signal V_RIs the same as V_S1Is low,
The output of the comparator 86 is the output of the multiplexer 88
And V_NIs V as shown in FIG. 9C.₁And V_ThreeWith
Between. Here, the signal V_Z1Is the signal V_QSame as
You. V_S2Is high, the output of comparator 84 is
Coupled to the output of the_MIs shown in FIG. 9C.
V as shown_TwoAnd V_FourAnd between. Here, the signal V
_Z2Is the signal V_RIs the same as V_S2Is low,
The output of the parator 86 is connected to the output of the multiplexer 90.
And V_NIs V as shown in FIG. 9C._TwoAnd V_FourBetween
is there. Here, the signal V_Z2Is the signal V_QIs the same as

[0177] buck-boost region (between V ₃ and V _2), by changing delay (D in Fig. 9C) between the falling edge the next rising edge of the edge and V _S1 of V _S2, Bending or shrinking is possible. Buck-boost region is enlarged (V ₃ ~V ₂ is enlarged) as D increases
However, the range of the output-input voltage ratio adjusted in the buck-boost mode is increased. As the buck-boost region is increased, the average inductor current increases and the efficiency of the regulator decreases as described above with reference to FIG. It doesn't scale to exist.

The buck-boost region can be eliminated by making D in FIG. 9C less than zero such that the falling edge of V _S2 occurs after the rising edge of V _S1 . Preferably, the buck-boost region is not lost so that all output-to-input voltage ratios can be adjusted with a constant duty cycle of the switch as described above with reference to FIG. 6A.

Those skilled in the art will further recognize that the circuits of the present invention can be implemented using circuit configurations other than those shown and described above. All such modifications are
It is within the scope of the present invention, which is limited only by the claims herein.

[0180]

Thus, the present invention provides a highly efficient control circuit for operating a buck-boost switching regulator. The switching regulator can regulate the output voltage high, low, or the same as the input voltage. This switching regulator can be synchronous or asynchronous. This control circuit sets the switching regulator in buck mode, boost mode,
Or it can be operated in buck-boost mode. In the case of the buck mode, the switching regulator adjusts the output voltage to be smaller than the input voltage. In boost mode, the switching regulator adjusts the output voltage to be greater than the input voltage. In buck and boost modes, fewer than all switches are turned on and off, thereby regulating the output voltage and saving power. In buck-boost mode, all switches are turned on and off to adjust the output voltage to a value that is above, below, or equivalent to the input voltage.

[Brief description of the drawings]

FIG. 1A is a schematic diagram of a prior art synchronous switching regulator.

FIG. 1B is a schematic diagram of a prior art synchronous switching regulator.

FIG. 1C is a schematic diagram of a prior art synchronous switching regulator.

FIG. 2A is a block diagram of an exemplary embodiment of a synchronous switching regulator comprising a control circuit of the present invention.

FIG. 2B is a schematic diagram of an exemplary embodiment of a synchronous switching regulator including a control circuit of the present invention.

FIG. 2C is a block diagram of an exemplary embodiment of a signal generator that may be used in the control circuit of the present invention.

FIG. 2D is a schematic diagram of an exemplary embodiment of the logic circuit of the present invention.

FIG. 3A is a block diagram of an exemplary embodiment of an asynchronous switching regulator with a control circuit of the present invention.

FIG. 3B is a schematic diagram of an exemplary embodiment of an asynchronous switching regulator with a control circuit of the present invention.

FIG. 4 is a schematic diagram of an exemplary embodiment of a synchronous / asynchronous switching regulator with a control circuit of the present invention.

FIG. 5 is a schematic diagram of another exemplary embodiment of a synchronous / asynchronous switching regulator with a control circuit of the present invention.

FIG. 6A is a graph of exemplary signals for the circuits of FIGS. 2B, 3B, 4, and 5;

FIG. 6B is a graph of exemplary signals for the circuits of FIGS. 2B, 3B, 4, and 5;

FIG. 6C is a graph of exemplary signals for the circuits of FIGS. 2B, 3B, 4, and 5;

FIG. 6D is a graph of exemplary signals for the circuits of FIGS. 2B, 3B, 4, and 5;

FIG. 7 is a block diagram of another exemplary embodiment of a signal generator that may be used in the control circuit of the present invention.

FIG. 8A is a block diagram of another exemplary embodiment of a signal generator that may be used in the control circuit of the present invention.

FIG. 8B is a graph of exemplary signals of a control circuit of the present invention comprising the circuit of FIG. 8A.

FIG. 9A is a block diagram of another exemplary embodiment of a pulse width adjuster that may be used in the control circuit of the present invention.

FIG. 9B is a block diagram of another exemplary embodiment of a signal generator that may be used in the control circuit of the present invention.

FIG. 9C is a graph of exemplary signals for the circuits of FIGS. 9A and 9B.

[Explanation of symbols]

 14 switching regulator 15 power supply 16 input capacitor 17 inductor 18 output capacitor 19 load 20 control circuit 21 resistor 22 error amplifier 25 pulse width modulator 27, 28 comparator

Continued on the front page (72) Inventor Trevor W .. Barcelo California 94040, Mountain, Number 39, California Street 2065

Claims (80)

[Claims] 1. A method for controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and a second voltage of the inductor. A first switch coupled between the first terminal of the inductor, a second switch coupled between the first terminal of the inductor and ground, and a second switch coupled to the second terminal of the inductor and ground. A third switch coupled between the second terminal of the inductor and the output node, the feedback being proportional to the output voltage of the switching regulator. Generating a signal; controlling a duty cycle of the first switch using a first drive signal generated in response to the feedback signal; generating a signal in response to the feedback signal. The second drive signal is used to control the duty cycle of the second switch, such that when the first switch is on, the second switch is off and the second switch is on. Controlling the duty cycle of the third switch using a third drive signal generated in response to the feedback signal, wherein the first switch is turned off when A step wherein the duty cycle of the first switch is not equal to the duty cycle of the third switch while the output voltage is being regulated at the output node; and a step generated in response to the feedback signal. The fourth drive signal is used to control the duty cycle of the fourth switch, such that when the fourth switch is on, the third switch is off and the fourth switch is off. 3 switches the switch of the fourth is turned off when on the steps,
A method comprising: 2. A first signal proportional to the feedback signal.
Generating a first and a second voltage signal; and providing a first and a second periodic waveform signal;
Generating the first control signal by comparing the first voltage signal with the first periodic waveform signal, wherein the first and second drive signals include: Generating in response to generating the second control signal by comparing the second voltage signal with the second periodic waveform signal, wherein the third and fourth driving are performed. Wherein the signal is generated in response to the second control signal. 3. The step of providing said first and said second periodic waveform signals comprises the step of providing said second periodic waveform signal by a DC offset voltage.
3. The method of claim 2, further comprising providing said first periodic waveform signal offset from said periodic waveform signal. 4. The method according to claim 1, wherein generating the first and second voltage signals further includes generating the second voltage signal offset from the first voltage signal by a DC offset voltage. The method according to claim 2. 5. The step of providing the first and second periodic waveform signals comprises providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. 3. The method of claim 2, further comprising: 6. The step of providing the first and second periodic waveform signals comprises providing the second periodic waveform signal having a waveform different from the waveform of the first periodic waveform signal. 3. The method of claim 2, further comprising: 7. The step of providing the first and second periodic waveform signals comprises providing the second periodic waveform signal having a different peak-to-peak amplitude than the first periodic waveform signal. 3. The method of claim 2, further comprising the step of: 8. The method of claim 2, wherein said first and second periodic waveform signals are sawtooth waveform signals. 9. The method of claim 2, wherein said first and second periodic waveform signals are triangular waveform signals. 10. Producing first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; Generating a first control signal by comparing with the first periodic waveform signal; comparing the second voltage signal with the second periodic waveform signal to generate a second control signal; Generating, selecting the first and second control signals to generate a first selection signal, wherein the first selection signal has a substantially constant propagation delay Wherein the first and second drive signals are generated in response to the first selection signal; and selecting the first and second control signals to generate a second selection signal. Wherein said second selection signal has a substantially constant propagation delay and said third and fourth drive signals Is generated in response to the second selection signal, further comprising a, a process, method according to claim 1. 11. A method for controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and a second voltage of the inductor. A first switch coupled between the first terminal of the inductor; a first diode having an anode coupled to ground and a cathode coupled to the first terminal of the inductor; A second switch coupled between the first terminal of the inductor and ground, and a second diode having an anode coupled to the second terminal of the inductor and a cathode coupled to the output node. Generating a feedback signal proportional to the output voltage of the switching regulator; and using a first drive signal generated in response to the feedback signal to de-energize the first switch. Controlling a duty cycle of the second switch using a second drive signal generated in response to the feedback signal to regulate the output voltage at the output node. While the duty cycle of the first switch is not equal to the duty cycle of the second switch. 12. A method for generating first and second voltage signals proportional to the feedback signal; providing first and second periodic waveform signals; Generating a first control signal by comparing the first control signal with the first periodic waveform signal;
A drive signal is generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal. The step, wherein the second
Wherein the drive signal is generated in response to the second control signal. 13. The step of providing the first and second periodic waveform signals comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a DC current offset voltage. 2. The method of claim 1, further comprising the step of:
3. The method according to 2. 14. The method of claim 1, wherein generating the first and second voltage signals further comprises generating the second voltage signal offset from the first voltage signal by a DC offset voltage. Item 13. The method according to Item 12. 15. The step of providing the first and second periodic waveform signals includes providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. 13. The method of claim 12, further comprising: 16. The step of providing the first and second periodic waveform signals comprises providing the second periodic waveform signal having a waveform different from the waveform of the first periodic waveform signal. 13. The method of claim 12, further comprising: 17. The step of providing the first and second periodic waveform signals provides the second periodic waveform signal having a different peak-to-peak amplitude than the first periodic waveform signal. 13. The method of claim 12, further comprising the step of: 18. The method according to claim 12, wherein said first and second periodic waveform signals are sawtooth waveform signals. 19. The method according to claim 12, wherein said first and second periodic waveform signals are triangular waveform signals. 20. A method for generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal to the second voltage signal. Generating a first control signal by comparing with the one periodic waveform signal; and generating a second control signal by comparing the second voltage signal with the second periodic waveform signal Selecting the first and second control signals to generate a first selection signal, wherein the first selection signal has a substantially constant propagation delay; Generating a first drive signal in response to the first selection signal; and selecting the first and second control signals to generate a second selection signal. , The second selection signal has a substantially constant propagation delay, and the second drive signal includes the second selection signal. In response generated, a step, a further encompasses method of claim 11. 21. A method of controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and a second voltage of the inductor. A first switch coupled between the first terminal of the inductor, a second switch coupled between the first terminal of the inductor and ground, and a second switch coupled to the second terminal of the inductor and ground. A third switch coupled therebetween, and a diode having an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the method comprising: Generating a feedback signal proportional to the output voltage of; and controlling a duty cycle of the first switch using a first drive signal generated in response to the feedback signal. Controlling a duty cycle of the second switch using a second drive signal generated in response to the feedback signal, whereby the second switch is turned on when the first switch is on. Is turned off and the first switch is turned off when the second switch is turned on; and using the third drive signal generated in response to the feedback signal, Controlling the duty cycle of a switch, whereby the duty cycle of the first switch is not equal to the duty cycle of the third switch while the output voltage is being regulated at the output node; A method comprising: 22. Generating first and second voltage signals proportional to the feedback signal; providing first and second periodic waveform signals; Generating a first control signal in comparison with one periodic waveform signal, wherein the first and second drive signals are generated in response to the first control signal. Generating a second control signal by comparing the second voltage signal with the second periodic waveform signal, wherein the third drive signal is responsive to the second control signal. 22. The method of claim 21, further comprising the steps of: 23. The step of providing the first and second periodic waveform signals comprises providing the first periodic waveform signal offset from the second periodic waveform signal by a DC offset voltage. 23. The method of claim 22, further comprising the step of:
The method described in. 24. The step of generating the first and second voltage signals further comprises the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage. Item 23. The method according to Item 22. 25. The step of providing the first and second periodic waveform signals further comprises the step of providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. 23. The method of claim 22, comprising. 26. The step of providing the first and second periodic waveform signals further comprises the step of providing the second periodic waveform signal having a different waveform than the first periodic waveform signal. 23. The method of claim 22, comprising. 27. The step of providing the first and second periodic waveform signals provides the second periodic waveform signal having a different peak-to-peak amplitude than the first periodic waveform signal. 23. The method of claim 22, further comprising the step of: 28. The method of claim 22, wherein said first and second periodic waveform signals are sawtooth waveform signals. 29. The method according to claim 22, wherein said first and second periodic waveform signals are triangular waveform signals. 30. A method for generating first and second voltage signals proportional to the feedback signal, providing first and second periodic waveform signals, and converting the first voltage signal to the second voltage signal. Generating a first control signal by comparing with the one periodic waveform signal; and generating a second control signal by comparing the second voltage signal with the second periodic waveform signal Selecting the first and second control signals to generate a first selection signal, wherein the first selection signal has a substantially constant propagation delay; Generating first and second drive signals in response to the first selection signal; and selecting the first and second control signals to generate a second selection signal Wherein the second selection signal has a substantially constant propagation delay and the third drive signal is It is generated in response to the selection signal; further encompasses method of claim 21. 31. A method for controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and a second voltage of the inductor. A first switch coupled between the first terminal of the inductor, a diode coupled to the first terminal of the inductor and a cathode coupled to the first terminal of the inductor, and a second terminal of the inductor. A second switch coupled to ground; and a third switch coupled between the second terminal of the inductor and the output node.
Generating a feedback signal proportional to the output voltage of the switching regulator; and using a first drive signal generated in response to the feedback signal to control the first switch. Controlling the duty cycle; and controlling the duty cycle of the second switch using a second drive signal generated in response to the feedback signal, whereby the output voltage at the output node is reduced. Using the third drive signal generated in response to the feedback signal, wherein the duty cycle of the first switch is not equal to the duty cycle of the second switch while being adjusted; Controlling the duty cycle of the third switch, wherein when the third switch is on, the second switch is off and the second switch is off; Turning off the third switch when is on.
Method. 32. Generating first and second voltage signals proportional to the feedback signal; providing first and second periodic waveform signals; and converting the first voltage signal to the second voltage signal. Generating a first control signal by comparing the first control signal with the first periodic waveform signal;
A drive signal is generated in response to the first control signal; and comparing the second voltage signal with the second periodic waveform signal to generate a second control signal. The step, wherein the second
And wherein the third drive signal is generated in response to the second control signal. 33. The step of providing said first and said second periodic waveform signals comprises the step of providing said second periodic waveform signal by a DC offset voltage.
Providing the first periodic waveform signal offset from the second periodic waveform signal.
The method described in. 34. The step of generating the first and second voltage signals further comprises the step of generating the second voltage signal offset from the first voltage signal by a DC offset voltage. Item 33. The method according to Item 32. 35. The step of providing the first and second periodic waveform signals comprises providing the first and second periodic waveform signals having the same waveform and the same peak-to-peak amplitude. 33. The method of claim 32, further comprising: 36. The step of providing the first and second periodic waveform signals further comprises the step of providing the second periodic waveform signal having a waveform different from the first periodic waveform signal. 33. The method of claim 32, comprising. 37. The step of providing the first and second periodic waveform signals provides the second periodic waveform signal having a different peak-to-peak amplitude than the first periodic waveform signal. 33. The method of claim 32, further comprising the step of: 38. The method of claim 32, wherein said first and second periodic waveform signals are sawtooth waveform signals. 39. The method according to claim 32, wherein said first and second periodic waveform signals are triangular waveform signals. 40. Generating first and second voltage signals that are proportional to the feedback signal; providing first and second periodic waveform signals; Generating a first control signal by comparing with the one periodic waveform signal; and generating a second control signal by comparing the second voltage signal with the second periodic waveform signal Selecting the first and second control signals to generate a first selection signal, wherein the first selection signal has a substantially constant propagation delay; Generating a first drive signal in response to the first selection signal; and selecting the first and second control signals to generate a second selection signal. , The second selection signal has a substantially constant propagation delay, and the second and third drive signals It is generated in response to the selection signal; further encompasses method of claim 31. 41. A control circuit for controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and an input voltage. A first switch coupled between the first terminal and a first terminal; a second switch coupled between the first terminal of the inductor and ground; and a second switch of the inductor and ground. And a fourth switch coupled between the second terminal of the inductor and the output node, wherein the control circuit includes a third switch coupled to the switching regulator circuit. A signal generator circuit comprising: an input node coupled to the output node; a waveform generator for providing a periodic waveform at a waveform output node; and first, second, third, and fourth output nodes. , The first and second
A signal generator circuit coupled to the input node of the signal generator circuit, and the third and fourth output nodes coupled to the waveform output node of the waveform generator; A first comparator circuit having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit; and a second comparator circuit and a second output node of the signal generator circuit, respectively. A second comparator circuit having coupled first and second inputs; and a logic circuit having a logic gate, wherein the logic circuit comprises:
A first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, the first, second, third and fourth switches; First, second, third and fourth outputs respectively coupled to the first switch, the first switch being off when the second switch is on, and the first switch being on when the first switch is on. A second switch is turned off, the fourth switch is turned on, the third switch is turned off, and the third switch is turned on, the fourth switch is turned off. , Control circuit. 42. The control circuit of claim 41, wherein a DC offset is generated between said third output node and said fourth output node of said signal generator circuit. 43. The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a resistor coupled between the fourth output node and ground. 43. The control circuit of claim 42, further comprising a current source, wherein the resistor and the current source generate the DC offset. 44. The control circuit of claim 41, wherein a DC offset is generated between said first output node and said second output node of said signal generator circuit. 45. The signal generator circuit includes a resistor coupled between the first output node and the second output node, and a resistor coupled between the second output node and ground. 45. The control circuit of claim 44, further comprising a current source, wherein the resistor and the current source generate the DC offset. 46. The waveform generator comprises first and second waveform generators, wherein the first waveform generator provides a first periodic waveform at a first waveform output node, Two periodic waveform generators provide a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node 42. The control circuit of claim 41, wherein said fourth output node of said signal generator circuit is coupled to said second waveform output node. 47. The control circuit according to claim 41, wherein said periodic waveform is a sawtooth waveform. 48. The control circuit according to claim 41, wherein said periodic waveform is a triangular waveform. 49. The control circuit further includes first and second multiplexer circuits, wherein the first multiplexer circuit includes a first input of the logic circuit and each of the first and second comparators. And the second multiplexer circuit is coupled between the second input of the logic circuit and the output of each of the first and second comparators. Item 42. The control circuit according to item 41. 50. An amplifier circuit having first and second inputs and an output coupled to said input node of said signal generator circuit; and said output node of said switching regulator circuit. A first resistor coupled between the first input of the amplifier circuit and a second resistor coupled between the first input of the amplifier circuit and ground; 42. The control circuit according to claim 41, comprising: 51. A control circuit for controlling a buck-boost switching regulator circuit to supply a regulated output voltage to an output node, the buck-boost switching regulator comprising: an inductor; A first switch coupled between the first terminal; a first diode having an anode coupled to ground and a cathode coupled to the first terminal of the inductor; 2
A second switch coupled between the second terminal of the inductor and ground, and a second diode having an anode coupled to the second terminal of the inductor and a cathode coupled to the output node. , The control circuit comprises: an input node coupled to the output node of the switching regulator circuit; a waveform generator providing a periodic waveform at a waveform output node; first, second, third, and fourth An output node, wherein the first and second output nodes are coupled to the input node of the signal generator circuit, and the third and fourth output nodes are connected to the waveform generator. A signal generator circuit coupled to the waveform output node of the signal generator; and a first comparator having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit. Circuit and the signal generator A second comparator circuit comprising a first and second inputs coupled respectively to the second and fourth output node of the road, a logic circuit comprising a logic gate, the logic circuit,
A first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and a second input coupled to the first and second switches, respectively. A logic circuit comprising a first output and a second output. 52. The control circuit of claim 51, wherein a DC offset is generated between said third output node and said fourth output node of said signal generator circuit. 53. The signal generator circuit includes a resistor coupled between the third output node and the fourth output node, and a resistor coupled between the fourth output node and ground. 53. The control circuit of claim 52, further comprising a current source, the resistor and the current source generating the DC offset. 54. The control circuit according to claim 51, wherein a DC offset is generated between said first output node and said second output node of said signal generator. 55. The signal generator circuit is coupled between a resistor between the first output node and the second output node and between the second output node and ground. 55. The control circuit of claim 54, further comprising a current source, wherein the resistor and the current source generate the DC offset. 56. The waveform generator comprises first and second waveform generators, wherein the first waveform generator provides a first periodic waveform at a first waveform output node, Second
Providing a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node;
52. The control circuit of claim 51, wherein said fourth output node of said signal generator circuit is coupled to said second waveform output node. 57. The control circuit according to claim 51, wherein said periodic waveform is a sawtooth waveform. 58. The control circuit according to claim 51, wherein said periodic waveform is a triangular waveform. 59. The control circuit further includes first and second multiplexer circuits, wherein the first multiplexer circuit is configured to control the first input of the logic circuit and the first and second comparators, respectively. And the second multiplexer circuit is coupled between the second input of the logic circuit and the output of each of the first and second comparators. 52. The control circuit according to item 51. 60. An amplifier circuit having first and second inputs and an output coupled to said input node of said signal generator circuit; and said output node of said switching regulator circuit. A first resistor coupled between the first input of the amplifier circuit and a second resistor coupled between the first input of the amplifier circuit and ground; 52. The control circuit according to claim 51, comprising: 61. A control circuit for controlling a buck-boost switching regulator circuit to supply a regulated output voltage to an output node, the buck-boost switching regulator comprising: an inductor; A first switch coupled between the first terminal and a first terminal; a second switch coupled between the first terminal of the inductor and ground; and a second switch of the inductor and ground. And a diode with an anode coupled to the second terminal of the inductor and a cathode coupled to the output node, the control circuit comprising: A signal generator comprising: an input node coupled to the output node of a regulator circuit; a waveform generator providing a periodic waveform at a waveform output node; and first, second, third, and fourth output nodes. Circuit Wherein the first and second output nodes are coupled to the input node of the signal generator circuit, and the third and fourth output nodes are coupled to the waveform output node of the waveform generator; A signal generator circuit; a first comparator circuit having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit; and a first comparator circuit of the signal generator circuit. A second comparator circuit having first and second inputs respectively coupled to the second and fourth output nodes; and a logic circuit comprising a logic gate, wherein the logic circuit comprises:
A first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and coupled to the first, second, and third switches, respectively; First, second and third outputs, the first switch being turned off when the second switch is turned on, and the second switch being turned on when the first switch is turned on.
A control circuit comprising: a logic circuit that turns off the switch. 62. The control circuit of claim 61, wherein a DC offset is generated between said third output node and said fourth output node of said signal generator circuit. 63. A signal generator circuit, wherein a resistor is coupled between the third output node and the fourth output node, and is coupled between the fourth output node and ground. 63. The control circuit of claim 62, further comprising: a current source, the resistor and the current source generating the DC offset. 64. The control circuit of claim 61, wherein a DC offset is generated between said first output node and said second output node of said signal generator circuit. 65. The signal generator circuit, wherein a resistor is coupled between the first output node and the second output node, and is coupled between the second output node and ground. 65. The control circuit of claim 64, further comprising a current source, wherein the resistor and the current source generate the DC offset. 66. The waveform generator comprises first and second waveform generators, wherein the first waveform generator provides a first periodic waveform at a first waveform output node, Second
Providing a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node; 62. The control circuit of claim 61, wherein said fourth output node of said signal generator circuit is coupled to said second waveform output node. 67. The control circuit according to claim 61, wherein said periodic waveform is a sawtooth waveform. 68. The control circuit according to claim 61, wherein said periodic waveform is a triangular waveform. 69. The control circuit further comprises a first and a second multiplexer circuit, wherein the first multiplexer circuit includes a first input of the logic circuit and each of the first and second comparators. And the second multiplexer circuit is coupled between the second input of the logic circuit and the output of each of the first and second comparators. 61. The control circuit according to item 61. 70. An amplifier circuit having first and second inputs and an output coupled to said input node of said signal generator circuit; and said output node of said switching regulator circuit; A first resistor coupled between the first input of the amplifier circuit and a second resistor coupled between the first input of the amplifier circuit and ground; 62. The control circuit according to claim 61, comprising: 71. A control circuit for controlling a buck-boost switching regulator circuit to provide a regulated output voltage to an output node, the buck-boost switching regulator comprising an inductor, an input voltage, and an inductor. A first switch coupled between the first terminal; a diode having an anode coupled to ground and a cathode coupled to the first terminal of the inductor; and a second terminal of the inductor. And a third switch coupled between the second terminal of the inductor and the output node, the control circuit comprising: A signal generator comprising: an input node coupled to the output node of a circuit, a waveform generator for providing a periodic waveform at a waveform output node, and first, second, third and fourth output nodes. In the circuit Thus, the first and second output nodes are coupled to the input node of the signal generator circuit, and the third and fourth output nodes are coupled to the waveform output node of the waveform generator. A signal generator circuit; a first comparator circuit having first and second inputs respectively coupled to the first and third output nodes of the signal generator circuit; and a first comparator circuit of the signal generator circuit. A second comparator circuit having first and second inputs respectively coupled to the second and fourth output nodes; and a logic circuit comprising a logic gate, wherein the logic circuit comprises:
A first input coupled to an output of the first comparator circuit, a second input coupled to an output of the second comparator circuit, and coupled to the first, second, and third switches, respectively; First, second, and third outputs, wherein the third switch is turned off when the second switch is turned on, and the second switch is turned on when the third switch is turned on.
A control circuit comprising: a logic circuit that turns off the switch. 72. The control circuit of claim 71, wherein a DC offset is generated between said third output node and said fourth output node of said signal generator circuit. 73. The signal generator circuit is coupled between a resistor between the third output node and the fourth output node, and between the fourth output node and ground. 73. The control circuit of claim 72, further comprising a current source, wherein the resistor and the current source generate the DC offset. 74. The control circuit of claim 71, wherein a DC offset is generated between said first output node and said second output node of said signal generator circuit. 75. The signal generator circuit includes a resistor coupled between the first output node and the second output node, and a resistor coupled between the second output node and ground. 75. The control circuit of claim 74, further comprising a current source, the resistor and the current source generating the DC offset. 76. The waveform generator comprises first and second waveform generators, wherein the first wave generator provides a first periodic waveform at a first waveform output node, A second periodic waveform generator provides a second periodic waveform at a second waveform output node, wherein the third output node of the signal generator circuit is coupled to the first waveform output node ,
72. The control circuit of claim 71, wherein said fourth output node of said signal generator circuit is coupled to said second waveform output node. 77. The control circuit according to claim 71, wherein said periodic waveform is a sawtooth waveform. 78. The control circuit according to claim 71, wherein said periodic waveform is a triangular waveform. 79. The control circuit further includes first and second multiplexer circuits, wherein the first multiplexer circuit includes a first input of the logic circuit and each of the first and second comparators. And the second multiplexer circuit is coupled between the second input of the logic circuit and the output of each of the first and second comparators. The control circuit according to claim 71. 80. The control circuit, comprising: an amplifier circuit having first and second inputs; and an output coupled to the input node of the signal generator circuit; and an output node of the switching regulator circuit. A first resistor coupled between the first input of the amplifier circuit and a second resistor coupled between the first input of the amplifier circuit and ground; 72. The control circuit of claim 71 comprising.