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JP2001313399A - Photoelectric conversion device - Google Patents

Photoelectric conversion device

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Publication number
JP2001313399A
JP2001313399A JP2000130855A JP2000130855A JP2001313399A JP 2001313399 A JP2001313399 A JP 2001313399A JP 2000130855 A JP2000130855 A JP 2000130855A JP 2000130855 A JP2000130855 A JP 2000130855A JP 2001313399 A JP2001313399 A JP 2001313399A
Authority
JP
Japan
Prior art keywords
photoelectric conversion
layer
conversion device
semiconductor layer
crystalline semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000130855A
Other languages
Japanese (ja)
Other versions
JP4540177B2 (en
Inventor
Makoto Sugawara
信 菅原
Takeshi Kyoda
豪 京田
Hisao Arimune
久雄 有宗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000130855A priority Critical patent/JP4540177B2/en
Publication of JP2001313399A publication Critical patent/JP2001313399A/en
Application granted granted Critical
Publication of JP4540177B2 publication Critical patent/JP4540177B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Abstract

(57)【要約】 【課題】 従来の結晶質半導体粒子を用いた光電変換装
置は高コスト且つ低変換効率であった。 【解決手段】 基板上に第一導電形の結晶質半導体粒子
を多数配置し、この結晶質半導体粒子上に第二導電形の
半導体層を形成し、この第二導電形の半導体層と上記基
板との間に絶縁体を介在させた光電変換装置において、
上記第二導電形の半導体層を結晶質半導体層で形成し
た。
(57) [Problem] A photoelectric conversion device using a conventional crystalline semiconductor particle has high cost and low conversion efficiency. SOLUTION: A large number of crystalline semiconductor particles of a first conductivity type are arranged on a substrate, and a semiconductor layer of a second conductivity type is formed on the crystalline semiconductor particles. In a photoelectric conversion device with an insulator interposed between
The semiconductor layer of the second conductivity type was formed of a crystalline semiconductor layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は太陽光発電に使用さ
れる光電変換装置に関し、特に結晶質半導体粒子を用い
た光電変換装置に関する。
The present invention relates to a photoelectric conversion device used for photovoltaic power generation, and more particularly to a photoelectric conversion device using crystalline semiconductor particles.

【0002】[0002]

【従来の技術】省シリコン原料の低コストな次世代太陽
電池の出現が強く望まれている。省資源に有利な粒形も
しくは球形のシリコン結晶粒子を用いる従来の光電変換
装置を図2に示す(例えば特許第2641800号公報
参照)。この光電変換装置は、基板1上に低融点金属層
7を形成し、この低融点金属層7上に第一導電形の結晶
質半導体粒子3を配設し、この結晶質半導体粒子3上に
第二導電形の非晶質半導体層6を上記低融点金属層7と
の間に絶縁層2を介して形成する光電変換装置が開示さ
れている。
2. Description of the Related Art The emergence of low-cost next-generation solar cells using silicon-saving materials is strongly desired. FIG. 2 shows a conventional photoelectric conversion device using granular or spherical silicon crystal particles advantageous for resource saving (see, for example, Japanese Patent No. 2641800). In this photoelectric conversion device, a low-melting-point metal layer 7 is formed on a substrate 1, and first-conductivity-type crystalline semiconductor particles 3 are disposed on the low-melting-point metal layer 7. There is disclosed a photoelectric conversion device in which an amorphous semiconductor layer 6 of the second conductivity type is formed between the amorphous semiconductor layer 6 and the low melting point metal layer 7 via an insulating layer 2.

【0003】また、特開昭61−124179号公報に
よれば、図3に示すように、上部アルミニウム箔10に
開口10aを形成し、その開口10aにp形核9aの表
面にn形表皮部9bを持つシリコン球9を配設し、この
シリコン球9の裏側のn形表皮部9bを除去し、上部ア
ルミニウム箔10の裏面側に絶縁層2を形成し、シリコ
ン球9の裏側のp形核9a上の絶縁層2を除去し、下部
アルミニウム箔8とシリコン球9のp形核9aとを接合
する光電変換装置が開示されている。
According to Japanese Patent Laid-Open No. 61-124179, as shown in FIG. 3, an opening 10a is formed in an upper aluminum foil 10, and an opening 10a is formed in the opening 10a on the surface of a p-type core 9a. A silicon ball 9 having a silicon ball 9b is disposed, the n-type skin portion 9b on the back side of the silicon ball 9 is removed, the insulating layer 2 is formed on the back side of the upper aluminum foil 10, and the p-type on the back side of the silicon ball 9 is formed. A photoelectric conversion device in which the insulating layer 2 on the nucleus 9a is removed and the lower aluminum foil 8 and the p-type nucleus 9a of the silicon sphere 9 are joined is disclosed.

【0004】また、特公平8−34177号公報によれ
ば、図4に示すように、基板1上に半導体微小結晶粒1
3を堆積させ、この半導体微小結晶粒13を融解させて
飽和させた上で徐々に冷却して半導体を液相エピタキシ
ャル成長させることによって多結晶薄膜13を形成する
方法が開示されている。なお、図4において11はSn
などの低融点金属膜、12はMoなどの高融点金属膜、
14は第2導電形のタ結晶あるいは非晶質半導体層、1
5は透明導電膜である。
Further, according to Japanese Patent Publication No. 8-34177, as shown in FIG.
3, a method of forming a polycrystalline thin film 13 by melting and saturating the semiconductor fine crystal grains 13 and then gradually cooling the semiconductor microcrystal grains 13 to cause liquid phase epitaxial growth of the semiconductor. In FIG. 4, reference numeral 11 denotes Sn.
12 is a high melting point metal film such as Mo,
Reference numeral 14 denotes a second conductivity type monocrystalline or amorphous semiconductor layer;
5 is a transparent conductive film.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、特許第
2641800号公報によれば、第二導電形の半導体層
6として非晶質半導体層を用いるため、非晶質半導体層
6の光吸収が大きいことに起因して、その膜厚を薄くし
なければならず、半導体層6を粒子3の表面に沿って形
成するとき、位置による膜厚分布が生じ、膜厚が薄いと
粒子3の全面を十分に覆うことができないため、粒子3
の外郭に沿ったpn接合の形成が難しくなる。粒子3と
絶縁層2を平面に研磨して露出させた後に半導体層6を
形成することで被覆性の悪さを補う場合であっても、研
磨工程や研磨屑を取り除く洗浄工程が増え、加えて粒子
3の高さにバラツキがあるとき、pn接合面積がばらつ
き、十分な特性得られない。その結果、高コスト、低変
換効率になるという問題があった。
However, according to Japanese Patent No. 2641800, since an amorphous semiconductor layer is used as the second conductivity type semiconductor layer 6, the amorphous semiconductor layer 6 has a large light absorption. Due to this, when the semiconductor layer 6 is formed along the surface of the particle 3, a film thickness distribution depending on the position occurs. Particle 3
It is difficult to form a pn junction along the outline of the pn junction. Even if the poor coverage is compensated for by forming the semiconductor layer 6 after the particles 3 and the insulating layer 2 are polished and exposed to a flat surface, the number of polishing steps and cleaning steps for removing polishing debris increases, and When the height of the particles 3 varies, the pn junction area varies, and sufficient characteristics cannot be obtained. As a result, there is a problem that the cost is high and the conversion efficiency is low.

【0006】また、図3に示す特開昭61−12417
9号公報のような光電変換装置においては、p形中心核
9aの上にn形表皮部9bをもつシリコン球9を製造す
る必要があること、およびアルミニウム箔10に開口1
0aを形成し、その開口10aにシリコン球9を押し込
んで接合させる必要があることから、シリコン球9の球
径に均一性が要求され、高コストになるという問題点が
あった。
[0006] Further, Japanese Patent Application Laid-Open No. 61-12417 shown in FIG.
In the photoelectric conversion device as disclosed in Japanese Patent Application Laid-Open No. 9-209, it is necessary to manufacture a silicon sphere 9 having an n-type skin portion 9b on a p-type central core 9a, and an opening 1 in an aluminum foil 10.
Since the silicon spheres 9 need to be formed and then bonded by pushing the silicon spheres 9 into the openings 10a, uniformity is required for the sphere diameter of the silicon spheres 9, resulting in a high cost.

【0007】また、特公平8−34177号公報によれ
ば、低融点金属膜11の成分が多結晶薄膜13へ混入し
て特性が落ち、絶縁体が無いために、上部電極15と下
部電極12との間がショートしやすいという問題点があ
った。
According to Japanese Patent Publication No. 8-34177, the components of the low melting point metal film 11 are mixed into the polycrystalline thin film 13 to deteriorate the characteristics, and since there is no insulator, the upper electrode 15 and the lower electrode 12 There is a problem that a short circuit is easily generated between them.

【0008】本発明は上記従来技術における問題点に鑑
みてなされたものであり、その目的は低コストで優れた
特性の光電変換装置を提供することにある。
The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a photoelectric conversion device having excellent characteristics at low cost.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る光電変換装置は、基板上に第一導電形
の結晶質半導体粒子を多数配置し、この結晶質半導体粒
子上に第二導電形の半導体層を形成し、この第二導電形
の半導体層と前記基板との間に絶縁体を介在させた光電
変換装置において、前記第二導電形の半導体層を結晶質
半導体層で形成したことを特徴とする。
Means for Solving the Problems To achieve the above object, a photoelectric conversion device according to the present invention comprises arranging a large number of first-conductivity-type crystalline semiconductor particles on a substrate; In a photoelectric conversion device in which a semiconductor layer of the second conductivity type is formed and an insulator is interposed between the semiconductor layer of the second conductivity type and the substrate, the semiconductor layer of the second conductivity type is a crystalline semiconductor layer. It is characterized by being formed by.

【0010】また、上記光電変換装置では、前記結晶質
半導体層の膜厚が50nm〜700nmであることが望
ましい。
In the above-mentioned photoelectric conversion device, it is preferable that the thickness of the crystalline semiconductor layer is 50 nm to 700 nm.

【0011】また、上記光電変換装置では、前記結晶質
半導体層が前記結晶質半導体粒子の表面に沿って形成さ
れることが望ましい。
In the above-mentioned photoelectric conversion device, it is preferable that the crystalline semiconductor layer is formed along the surface of the crystalline semiconductor particles.

【0012】さらに、上記光電変換装置では、前記結晶
質半導体層上に透明導電層を設けることが望ましい。
Further, in the above-mentioned photoelectric conversion device, it is desirable to provide a transparent conductive layer on the crystalline semiconductor layer.

【0013】本発明の光電変換装置によれば、基板上に
第一導電形の結晶質半導体粒子を配置し、この結晶質半
導体粒子上に第二導電形の結晶質半導体層を形成し、こ
の第二導電形の結晶質半導体層と基板との間に絶縁体を
形成したことにより、従来の特許第2641800号公
報、特開昭61−124179号公報、特公平8−34
177号公報などで開示されている光電変換装置と比較
して低コストの製造が可能であり、かつ優れた特性を実
現できる。言い換えると、単一導電形を持つ粒子を低い
粒径精度で製造すればよいため、低コストの製造が可能
で、半導体層の膜厚自由度が大きく、絶縁体で正極負極
の分離が確実にされるため、優れた特性を実現できる。
優れた特性とは、被覆性が十分で、この結晶質半導体粒
子と導電膜との間のショートがなく、高い変換効率を有
することを示す。
According to the photoelectric conversion device of the present invention, crystalline semiconductor particles of the first conductivity type are arranged on the substrate, and a crystalline semiconductor layer of the second conductivity type is formed on the crystalline semiconductor particles. By forming an insulator between the crystalline semiconductor layer of the second conductivity type and the substrate, the prior art is disclosed in Japanese Patent No. 2641800, Japanese Patent Application Laid-Open No. 61-124179, and Japanese Patent Publication No. 8-34.
As compared with the photoelectric conversion device disclosed in, for example, Japanese Patent Application Laid-Open No. 177, 177, it is possible to manufacture the device at lower cost and to realize excellent characteristics. In other words, it is only necessary to produce particles having a single conductivity type with low particle size accuracy, so that low-cost production is possible, the degree of freedom in the thickness of the semiconductor layer is large, and the separation of the positive electrode and the negative electrode by the insulator is ensured. Therefore, excellent characteristics can be realized.
The excellent properties indicate that the coatability is sufficient, there is no short circuit between the crystalline semiconductor particles and the conductive film, and the conversion efficiency is high.

【0014】[0014]

【発明の実施の形態】以下、図面に基づいて本発明を詳
細に説明する。図1において、1は基板、2は絶縁層、
3は第一導電形の結晶質半導体粒子、4は結晶質半導体
層、5は透明導電膜である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. In FIG. 1, 1 is a substrate, 2 is an insulating layer,
3 is a crystalline semiconductor particle of the first conductivity type, 4 is a crystalline semiconductor layer, and 5 is a transparent conductive film.

【0015】基板1としては、金属、セラミック、樹脂
等が用いられる。基板1は下部電極を兼ねるために、特
性として導電性を持つものであればよく、材質が金属の
場合は基板1の構成は単層または他の金属との複層があ
る。なお、基板1がセラミックや樹脂などの絶縁体の場
合には、その表面に導電層を形成する必要がある。
As the substrate 1, metal, ceramic, resin or the like is used. Since the substrate 1 also serves as a lower electrode, it has only to have conductivity as a characteristic. When the material is metal, the substrate 1 has a single-layer structure or a multilayer structure with another metal. When the substrate 1 is an insulator such as ceramic or resin, it is necessary to form a conductive layer on the surface thereof.

【0016】絶縁層2は、正極負極の分離を行うために
設ける。例えばSiO2、Al23、PbO、ZnO等
を任意な成分とするガラススラリ−を用いて形成する。
絶縁層2の膜厚は結晶質半導体粒子3の平均粒径の2/
3以下で1μm以上が好適である。絶縁層2の膜厚が結
晶質半導体粒子3の2/3以上になると、pn接合の形
成領域が小さくなり、キャリアを効率よく集めることが
できなくなるために好ましくない。また、絶縁層2の膜
厚が1μm以下のとき、基板1と結晶質半導体層4との
間の絶縁が不十分となり、基板1と結晶質半導体層4と
が一部で接触し、ショートの原因となるために好ましく
ない。
The insulating layer 2 is provided for separating the positive electrode and the negative electrode. For example, it is formed using a glass slurry containing SiO 2 , Al 2 O 3 , PbO, ZnO or the like as an optional component.
The thickness of the insulating layer 2 is 2 / the average particle size of the crystalline semiconductor particles 3.
It is preferably 3 or less and 1 μm or more. If the thickness of the insulating layer 2 is 2/3 or more of that of the crystalline semiconductor particles 3, the area where the pn junction is formed becomes small, and it is not preferable because carriers cannot be efficiently collected. Further, when the thickness of the insulating layer 2 is 1 μm or less, insulation between the substrate 1 and the crystalline semiconductor layer 4 becomes insufficient, and the substrate 1 and the crystalline semiconductor layer 4 partially come into contact with each other, causing a short circuit. Not preferred because it causes.

【0017】第一導電形の結晶質半導体粒子3は、S
i、Geにp形を呈するB、Al、Ga等、またはn形
を呈するP、As等が微量含まれているものである。半
導体粒子2の形状としては多角形を持つもの、曲面を持
つもの等があるが、例えば後述する絶縁体層2上から半
導体粒子3を押し込んで基板1に接触させる際に、絶縁
体層2を効率よく押しのけるために、曲面を持つもの、
特に球状であるものがよい。粒径分布としては均一、不
均一を問わないが、均一の場合は粒径を揃えるための工
程が必要になり、より安価に得るためには、不均一の場
合が有利である。また、粒子3の粒径は10〜500μ
mがよく、10μm未満では押しつける際に押しつけ冶
具に絶縁層2が付着して半導体粒子3の表面が汚染さ
れ、500μmを越えると従来型の平面板の光電変換装
置で使用される半導体原料の使用量と変わらなくなり、
半導体原料の節約の意味で粒子を適用する利点がなくな
る。
The crystalline semiconductor particles 3 of the first conductivity type are S
i and Ge contain p-type B, Al, Ga, or the like, or n-type P, As, or the like, in a small amount. The shape of the semiconductor particles 2 includes a polygonal shape, a curved shape, and the like. For example, when the semiconductor particles 3 are pushed into the insulator layer 2 described below and brought into contact with the substrate 1, the insulator layer 2 is formed. One with a curved surface to push away efficiently,
Particularly, those having a spherical shape are preferable. The particle size distribution may be uniform or non-uniform, but if uniform, a process for adjusting the particle size is required. In order to obtain a lower cost, the non-uniform case is advantageous. The particle 3 has a particle size of 10 to 500 μm.
When the thickness is less than 10 μm, the insulating layer 2 adheres to the pressing jig when pressing and the surface of the semiconductor particles 3 is contaminated. It is no different from quantity,
The advantage of applying particles in the sense of saving semiconductor materials is lost.

【0018】第二導電形の結晶質半導体層4は、触媒C
VD法、VHF−CVD法、プラズマCVD法等で例え
ばシラン化合物の気相にn形を呈するリン系化合物の気
相、またはp形を呈するホウ素系化合物の気相を微量導
入して形成する。なお、結晶質半導体層4は、単結晶
質、多結晶質または微結晶質であればよい。結晶質半導
体層4は半導体粒子3の表面に沿って形成し、半導体接
合を光入射表面近傍かつ粒子形状に沿って形成すること
が望ましい。半導体粒子3の表面に沿って接合を形成す
ることで、結晶質半導体粒子3の内部のどの位置で生成
したキャリアも効率よく集めることができる。半導体層
4を凹凸のある形状に成膜するとき、膜厚が薄すぎると
粒子表面に沿って粒子の露出部をすべて覆うことが難し
くなる。反対に膜厚を厚くしすぎると被覆性は良好とな
るが、半導体層4の光吸収による損失が大きくなり、変
換効率が低下する。結晶質半導体層4は非晶質半導体層
と比較して光吸収が小さいため、膜厚を厚くしても急激
に損失が大きくなることはない。膜厚は50〜700n
mが好適である。50nm以下の場合、被覆性が悪化
し、半導体粒子3と透明導電膜5が直接接触するリーク
が発生して特性が悪化するために好ましくない。また、
700nm以上の場合、変換効率が低下すること、タク
トの低下、材料費の増大によって高コストとなるために
好ましくない。
The crystalline semiconductor layer 4 of the second conductivity type comprises a catalyst C
For example, a VD method, a VHF-CVD method, a plasma CVD method, or the like is used to introduce a slight amount of an n-type phosphorus-based compound gas phase or a p-type boron-based compound gas phase into a silane compound gas phase. Note that the crystalline semiconductor layer 4 may be monocrystalline, polycrystalline, or microcrystalline. It is desirable that the crystalline semiconductor layer 4 is formed along the surface of the semiconductor particle 3 and the semiconductor junction is formed near the light incident surface and along the particle shape. By forming a junction along the surface of the semiconductor particles 3, carriers generated at any position inside the crystalline semiconductor particles 3 can be efficiently collected. When the semiconductor layer 4 is formed into an uneven shape, if the film thickness is too small, it becomes difficult to cover all the exposed portions of the particles along the particle surface. Conversely, if the film thickness is too large, the coverage is good, but the loss due to light absorption of the semiconductor layer 4 increases, and the conversion efficiency decreases. Since the crystalline semiconductor layer 4 absorbs less light than the amorphous semiconductor layer, the loss does not increase rapidly even when the thickness is increased. Film thickness is 50-700n
m is preferred. If the thickness is 50 nm or less, the coverage is deteriorated, and a leak occurs in which the semiconductor particles 3 and the transparent conductive film 5 come into direct contact with each other. Also,
A thickness of 700 nm or more is not preferable because conversion efficiency is reduced, tact is reduced, and material costs are increased, resulting in high costs.

【0019】透明導電膜5は、例えば酸化錫やITOを
スパッタリング法、プラズマCVD法等で成膜する。な
お、太陽光の吸収が大きいと、変換効率が低下するた
め、太陽光の吸収が小さいことが好ましい。また、透明
導電膜の膜厚として10〜300nmがより好ましい。
10nm以下の膜厚では抵抗が大きくなり、変換効率が
低下するために好ましくない。300nm以上の膜厚で
は光吸収が大きくなり、変換効率が低下することと、タ
クトの低下、材料費の増大によって高コストとなるため
に好ましくない。
The transparent conductive film 5 is formed of, for example, tin oxide or ITO by a sputtering method, a plasma CVD method, or the like. Note that, when the absorption of sunlight is large, the conversion efficiency is reduced. Therefore, the absorption of sunlight is preferably small. Further, the thickness of the transparent conductive film is more preferably from 10 to 300 nm.
A film thickness of 10 nm or less is not preferable because resistance increases and conversion efficiency decreases. A film thickness of 300 nm or more is not preferable because light absorption increases, conversion efficiency decreases, tact decreases, and material costs increase, resulting in high costs.

【0020】さらに透明導電膜5の上に保護膜を設けて
もよい。保護膜としては、窒化珪素、酸化チタン等をス
パッタリング法やプラズマCVD法等で形成する。多重
反射効果、反射防止効果、耐候性の改善などの役割を持
たせることも可能である。
Further, a protective film may be provided on the transparent conductive film 5. As the protective film, silicon nitride, titanium oxide, or the like is formed by a sputtering method, a plasma CVD method, or the like. It is also possible to give roles such as a multiple reflection effect, an antireflection effect, and an improvement in weather resistance.

【0021】また、基板1と半導体粒子2の境界に隣接
する半導体粒子3の外郭部分に、高い濃度の第一導電形
部を形成することが望ましい。このように、高濃度の第
一導電形部を形成することにより、半導体粒子3で形成
されたキャリアを効率よく分離し、変換効率を向上させ
ることができる。高濃度の第一導電形部を形成する方法
としては、基板1と半導体粒子3を接触させて加熱する
ことにより、基板1の元素の一部または基板1上に形成
した導電膜6が半導体粒子3の外郭に拡散させる方法な
どがある。
Further, it is desirable to form a high-concentration first conductivity type portion on the outer portion of the semiconductor particle 3 adjacent to the boundary between the substrate 1 and the semiconductor particle 2. As described above, by forming the first conductive type portion having a high concentration, the carriers formed by the semiconductor particles 3 can be efficiently separated, and the conversion efficiency can be improved. As a method of forming the first conductive type portion having a high concentration, the substrate 1 and the semiconductor particles 3 are brought into contact with each other and heated so that a part of the elements of the substrate 1 or the conductive film 6 formed on the substrate 1 becomes semiconductor particles. 3 and the like.

【0022】[0022]

【実施例】次に、本発明の光電変換装置の実施例を説明
する。
Next, an embodiment of the photoelectric conversion device of the present invention will be described.

【0023】〔実施例1〕まず、基板1上に絶縁層2を
形成する。基板1にはアルミニウムを用いた。絶縁層2
はガラスペーストを用いて80μmの厚みに形成した。
次に、その上に平均直径200μmの多結晶p形シリコ
ン粒子3を密に1層配置した。次に、絶縁層2の軟化点
以上に加熱し、シリコン粒子3を絶縁層2に沈み込ま
せ、基板1と接触させた。次に、シリコン粒子3と絶縁
層2の上にn形結晶シリコン層4を形成した。n形結晶
シリコン層4の膜厚を変化させて特性を調べた結果を表
1に示す。その上に酸化錫からなる透明導電膜5を50
0nmの厚みに形成した。その上に窒化珪素からなる保
護膜を500nmの厚みに形成した。
[Embodiment 1] First, an insulating layer 2 is formed on a substrate 1. Aluminum was used for the substrate 1. Insulating layer 2
Was formed to a thickness of 80 μm using a glass paste.
Next, one layer of polycrystalline p-type silicon particles 3 having an average diameter of 200 μm was densely arranged thereon. Next, heating was performed to a temperature higher than the softening point of the insulating layer 2, so that the silicon particles 3 were sunk into the insulating layer 2 and brought into contact with the substrate 1. Next, an n-type crystalline silicon layer 4 was formed on the silicon particles 3 and the insulating layer 2. Table 1 shows the results of examining the characteristics by changing the film thickness of the n-type crystalline silicon layer 4. A transparent conductive film 5 made of tin oxide is placed on the
It was formed to a thickness of 0 nm. A protective film made of silicon nitride was formed thereon to a thickness of 500 nm.

【0024】また、比較例として、n形結晶シリコン層
4の代わりにn形非晶質シリコン層を形成したサンプル
を作製した。これも同様にn形非晶質シリコン層の膜厚
を変化させて特性を調べた結果を表1にまとめて比較し
た。
As a comparative example, a sample in which an n-type amorphous silicon layer was formed instead of the n-type crystalline silicon layer 4 was manufactured. Table 1 also summarizes the results obtained by changing the film thickness of the n-type amorphous silicon layer, and comparing the results.

【0025】被覆性は結晶シリコン粒子と透明導電膜が
直接接触することによるリークの頻度により評価した。
n形シリコンの被覆性が十分であれば、結晶シリコン粒
子と透明導電膜が直接接触することはない。具体的に
は、サンプルを10セット作製し、全数リークを×、9
〜3リークを△、2〜1リークを○、リークなしを◎と
した。変換効率はリークしていないものを測定し、その
平均で求めた。
The covering property was evaluated based on the frequency of leakage due to direct contact between the crystalline silicon particles and the transparent conductive film.
If the coverage of the n-type silicon is sufficient, the crystalline silicon particles do not come into direct contact with the transparent conductive film. Specifically, 10 sets of samples were prepared, and all leaks were evaluated as x, 9
3 indicates リ ー ク 3 leaks, 2〜 indicates 2-1 leaks, and ◎ indicates no leaks. The conversion efficiency was measured without leakage, and the average was obtained.

【0026】[0026]

【表1】 [Table 1]

【0027】上記結果から分かるように、結晶シリコン
層を用いた場合、非晶質シリコン層を用いた場合と比較
して変換効率と被覆性を両立させることができる。変換
効率は6%以上、被覆性は○以上が実用上必要である。
非晶質シリコン層を用いた場合、被覆性が良好となる5
0nm以上の範囲で変換効率がいずれも5%以下であ
り、実用的でない。これは、非晶質シリコン層は結晶シ
リコン層と比較して光吸収率が大きいため、膜厚を厚く
すると透過率が小さくなることが原因と考えられる。一
方、結晶シリコン層を用いた場合、被覆性と変換効率が
両立可能である。更に、非晶質と比較して安定な結晶構
造を有するため、寿命や信頼性の面でも優位であること
が期待できる。膜厚は50nm〜700nmが好適であ
る。結晶シリコン層が50nm未満のときは被覆性が十
分ではなく、700nmを超えるときは変換効率が悪化
するために好ましくない。 〔実施例2〕次に、pn接合の形状による違いを評価す
る。試料No.1〜7との比較例としてpn接合の形状
が異なるサンプルを作製した。比較例は以下の通り作製
した。基板1上に絶縁層2を形成する。基板1にはアル
ミニウムを用いた。絶縁層2はガラスペーストを用いて
200μmの厚みに形成した。次に、その上に平均粒径
200μmの多結晶p形シリコン粒子3を密に1層配置
した。次に、絶縁層2の軟化点以上に加熱し、シリコン
粒子3を絶縁層2に沈み込ませて基板1に接触させた。
次に、シリコン粒子3と絶縁層2が平面に露出するよう
に研磨した。次に、シリコン粒子3と絶縁層2の上にn
形結晶シリコン層4を形成した。n形結晶シリコン層4
の膜厚を変化させて評価した結果を表3に示す。その上
に酸化錫からなる透明導電膜5を500nmの厚みに形
成した。その上に窒化珪素からなる保護膜を500nm
の厚みに形成した。
As can be seen from the above results, when the crystalline silicon layer is used, both the conversion efficiency and the coverage can be achieved as compared with the case where the amorphous silicon layer is used. A conversion efficiency of 6% or more and a covering property of ○ or more are practically necessary.
When an amorphous silicon layer is used, the coverage is improved.
In the range of 0 nm or more, all conversion efficiencies are 5% or less, which is not practical. This is probably because the amorphous silicon layer has a higher light absorption rate than the crystalline silicon layer, and therefore, the transmittance decreases as the film thickness increases. On the other hand, when a crystalline silicon layer is used, coverage and conversion efficiency can be compatible. Further, since it has a stable crystal structure as compared with amorphous, it can be expected that it is superior in terms of life and reliability. The film thickness is preferably from 50 nm to 700 nm. When the thickness of the crystalline silicon layer is less than 50 nm, the coverage is not sufficient, and when the thickness exceeds 700 nm, the conversion efficiency deteriorates, which is not preferable. [Embodiment 2] Next, the difference due to the shape of the pn junction is evaluated. Sample No. Samples having different pn junction shapes were prepared as Comparative Examples 1 to 7. The comparative example was produced as follows. An insulating layer 2 is formed on a substrate 1. Aluminum was used for the substrate 1. The insulating layer 2 was formed to a thickness of 200 μm using a glass paste. Next, one layer of polycrystalline p-type silicon particles 3 having an average particle diameter of 200 μm was densely arranged thereon. Next, the substrate was heated to a temperature higher than the softening point of the insulating layer 2 so that the silicon particles 3 were sunk into the insulating layer 2 and brought into contact with the substrate 1.
Next, polishing was performed so that the silicon particles 3 and the insulating layer 2 were exposed on a plane. Next, n is placed on the silicon particles 3 and the insulating layer 2.
Form crystal silicon layer 4 was formed. n-type crystalline silicon layer 4
Table 3 shows the results of evaluation by changing the film thickness of. A transparent conductive film 5 made of tin oxide was formed thereon to a thickness of 500 nm. A protective film made of silicon nitride is formed thereon to a thickness of 500 nm.
Formed to a thickness of

【0028】[0028]

【表2】 [Table 2]

【0029】上記結果からpn接合が平面で形成される
場合、被覆性は良好な結果を示すが、変換効率が低く、
実用的でない。一方、pn接合が粒子表面に沿って形成
される場合、n形シリコン層が50〜700nmの範囲
で、被覆性、変換効率ともに優れた特性を得ることがで
きる。
From the above results, when the pn junction is formed in a plane, the coverage is good, but the conversion efficiency is low.
Not practical. On the other hand, in the case where the pn junction is formed along the particle surface, excellent characteristics in both coverage and conversion efficiency can be obtained when the n-type silicon layer is in the range of 50 to 700 nm.

【0030】[0030]

【発明の効果】以上のように、本発明の光電変換装置に
よれば、基板上に第一導電形の結晶質半導体粒子を多数
配置し、この結晶質半導体粒子上に第二導電形の半導体
層を形成し、この第二導電形の半導体層と上記基板との
間に絶縁体を介在させた光電変換装置において、上記第
二導電形の半導体層を結晶質半導体層で形成したことか
ら、被覆性と変換効率が両立させることがで、高い特性
を得ることができる。また、p形中心核の上にn形表皮
部を形成することや粒径に高い均一性を要求する必要が
なく、安価な光電変換装置を提供できる。
As described above, according to the photoelectric conversion device of the present invention, a large number of crystalline semiconductor particles of the first conductivity type are arranged on a substrate, and a semiconductor of a second conductivity type is placed on the crystalline semiconductor particles. Forming a layer, in the photoelectric conversion device in which an insulator is interposed between the semiconductor layer of the second conductivity type and the substrate, since the semiconductor layer of the second conductivity type is formed of a crystalline semiconductor layer, High characteristics can be obtained by making the coating property and the conversion efficiency compatible. Further, there is no need to form an n-type skin on the p-type central core and to require high uniformity in the particle size, so that an inexpensive photoelectric conversion device can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明実施例の光電変換装置を示す断面図であ
る。
FIG. 1 is a cross-sectional view illustrating a photoelectric conversion device according to an embodiment of the present invention.

【図2】従来の光電変換装置を示す断面図である。FIG. 2 is a cross-sectional view illustrating a conventional photoelectric conversion device.

【図3】従来の他の光電変換装置を示す断面図である。FIG. 3 is a cross-sectional view showing another conventional photoelectric conversion device.

【図4】従来のその他の光電変換装置を示す断面図であ
る。
FIG. 4 is a cross-sectional view showing another conventional photoelectric conversion device.

【符号の説明】[Explanation of symbols]

1・・・・・基板 2・・・・・絶縁層 3・・・・・結晶質半導体粒子 4・・・・・結晶質半導体層 5・・・・・透明導電膜 6・・・・・非晶質半導体層 7・・・・・低融点金属層 8・・・・・下部アルミニウム箔 9・・・・・p形の上にn形表皮部を持つシリコン球 10・・・上部アルミニウム箔 11・・・低融点金属膜 12・・・高融点金属膜 13・・・第一導電形の液相エピタキシャル多結晶層 14・・・第二導電形の多結晶あるいは非晶質層 1 ... substrate 2 ... insulating layer 3 ... crystalline semiconductor particles 4 ... crystalline semiconductor layer 5 ... transparent conductive film 6 ... Amorphous semiconductor layer 7 Low-melting metal layer 8 Lower aluminum foil 9 Silicon sphere having n-type skin on p-type 10 Upper aluminum foil 11 ... Low melting point metal film 12 ... High melting point metal film 13 ... Liquid phase epitaxial polycrystalline layer of first conductivity type 14 ... Polycrystalline or amorphous layer of second conductivity type

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F051 AA03 AA16 BA14 CB12 CB29 DA03 DA20 EA18 FA04 GA02 GA03  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F051 AA03 AA16 BA14 CB12 CB29 DA03 DA20 EA18 FA04 GA02 GA03

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板上に第一導電形の結晶質半導体粒子
を多数配置し、この結晶質半導体粒子上に第二導電形の
半導体層を形成し、この第二導電形の半導体層と前記基
板との間に絶縁体を介在させた光電変換装置において、
前記第二導電形の半導体層を結晶質半導体層で形成した
ことを特徴とする光電変換装置。
A first conductive type crystalline semiconductor particle disposed on a substrate; a second conductive type semiconductor layer formed on the crystalline semiconductor particle; In a photoelectric conversion device with an insulator interposed between the substrate and
A photoelectric conversion device, wherein the semiconductor layer of the second conductivity type is formed of a crystalline semiconductor layer.
【請求項2】 前記結晶質半導体層の膜厚が50nm〜
700nmであることを特徴とする請求項1に記載の光
電変換装置。
2. The method according to claim 1, wherein said crystalline semiconductor layer has a thickness of 50 nm to 50 nm.
The photoelectric conversion device according to claim 1, wherein the thickness is 700 nm.
【請求項3】 前記結晶質半導体層が前記結晶質半導体
粒子の表面に沿って形成されることを特徴とする請求項
1に記載の光電変換装置。
3. The photoelectric conversion device according to claim 1, wherein the crystalline semiconductor layer is formed along a surface of the crystalline semiconductor particles.
【請求項4】 前記結晶質半導体層上に透明導電層を設
けたことを特徴とする請求項1に記載の光電変換装置。
4. The photoelectric conversion device according to claim 1, wherein a transparent conductive layer is provided on the crystalline semiconductor layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402747B2 (en) 2003-02-18 2008-07-22 Kyocera Corporation Photoelectric conversion device and method of manufacturing the device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175526A (en) * 1991-05-27 1993-07-13 Canon Inc Crystal solar cell and method of manufacturing the same
JP2001308357A (en) * 2000-04-24 2001-11-02 Mitsui High Tec Inc Method for manufacturing solar cell and solar cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175526A (en) * 1991-05-27 1993-07-13 Canon Inc Crystal solar cell and method of manufacturing the same
JP2001308357A (en) * 2000-04-24 2001-11-02 Mitsui High Tec Inc Method for manufacturing solar cell and solar cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402747B2 (en) 2003-02-18 2008-07-22 Kyocera Corporation Photoelectric conversion device and method of manufacturing the device

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