JP2001311954A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] By using wet etching, a cross section of a laminated wiring of an upper layer of a molybdenum alloy and a lower layer of an aluminum alloy is processed into a tapered shape, and collective etching by a shower method to improve coverage of an insulating film. TFT-LCD having good insulation film coverage by processing the cross-sectional shape of the Mo / Al alloy laminated wiring into a tapered shape. A gate wiring is formed on a glass substrate, a register pattern is formed on the gate wiring by photolithography, an etchant contains phosphoric acid and nitric acid in a range of 7 mol% to 12 mol%, and ammonium fluoride and fluorine are used. Wet etching is performed with a composition containing a small amount of about 0.01 to 0.1 mol% of at least one of hydrogen chloride.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display (AM-LCD) driven by a thin film transistor (TFT) and a method of forming a wiring therefor.

[0002]

2. Description of the Related Art The market for a thin film transistor driven liquid crystal display (TFT-LCD) has been expanding as an image display device which can be made thinner, lighter and more precise than a conventional cathode ray tube. The TFT-LCD includes a gate wiring, a data wiring, a thin film transistor formed near an intersection of the gate wiring and the data wiring, a pixel electrode connected to the thin film transistor, a gate insulating film, and a protective film formed on a glass substrate. It comprises a substrate and a liquid crystal layer sandwiched between the glass substrate and the counter substrate. Recently, TFT
-As LCD screens become larger and higher definition,
Requirement specifications regarding the reduction of wiring resistance and the production yield are becoming stricter. For the purpose of reducing the resistance of the wiring, aluminum or aluminum alloy has been widely used.

However, when aluminum or an aluminum alloy is applied to a wiring in a single layer, hillocks are formed on the surface in many cases, resulting in poor coverage of an insulating film covering the wiring. In addition, the contact resistance between an oxide containing indium, which is a pixel electrode material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) and aluminum or an aluminum alloy is high. It is not practical to make a direct electrical connection.

Therefore, for example, an inverted stagger type TFT-LC
In the gate wiring of D, a countermeasure is taken by a clad structure in which a wiring pattern of aluminum or an aluminum alloy is covered with a high melting point metal. Therefore, a wiring pattern of aluminum or an aluminum alloy is covered with a second conductive layer to form a clad structure, and the contact characteristics with the pixel electrode material are provided by the second conductive layer, and the conductivity as the wiring is provided by aluminum or the aluminum alloy. ing. Such examples are disclosed, for example, in JP-A-5-341299, JP-A-7-64109, JP-A-9-26602, JP-A-9-127555, and JP-A-10-21.
No. 3809.

In order to form the above-mentioned clad structure, it is necessary to carry out photolithography twice, once for aluminum or aluminum alloy and once for the second conductive layer. Is complicated.

Therefore, for the purpose of simplifying the process, a method in which aluminum or an aluminum alloy and a second conductive layer are continuously laminated and formed, and a wiring pattern is formed by one photolithography and collective etching of the laminated film. Is adopted. In this case, as the second conductive layer, molybdenum or a molybdenum alloy which is a high melting point metal material which can be etched at a time with aluminum or an aluminum alloy is used.

[0007] In particular, in Japanese Patent Application Laid-Open No. 4-20930,
A wiring structure employing a molybdenum alloy containing 0.5 to 10% by weight of chromium as the second conductive layer is described. The laminated film is wet-etched at once using a solution of phosphoric acid, nitric acid, and acetic acid.
It is processed to 0 °. In this case, the molybdenum - the chromium alloy is resistant to dry etching with a fluorine-based gas such as SF _6. For this reason, the Si
The second conductive layer does not disappear at the bottom of the contact hole even if the connection means such as the contact hole is processed by dry etching with SF ₆ gas on the N insulating film, and the second conductive layer and the pixel electrode are connected. Thereby, good contact characteristics can be obtained. Digest is an example of the cross-sectional shape of the wiring when molybdenum / aluminum laminated wiring is etched with a solution of a mixture of phosphoric acid and nitric acid for both the dip method and the shower method.
of Technical Papers of 1994 INTERNATIONAL WORKSHOP
ON ACTIVE-MATRIXLIQUID-CRYSTAL DISPLAYS, November
30-December 1, 1994, KOGAKUINUNIVERSITY, Shinju
ku, Tokyo, Japan, p188. According to this, it is reported that in the case of the dip method, the wiring cross section is subjected to forward taper processing, but in the case of the shower method, the molybdenum layer has a cross-sectional shape protruding like an eaves with respect to the aluminum layer. . In Japanese Patent Application Laid-Open No. 9-33066, the second
Is made of titanium, molybdenum, tantalum, tungsten, zirconium, or a composite material thereof. In the present invention, the light-shielding film and the wiring are simultaneously formed in the same process, but the second conductive layer has a role of suppressing the reflectance of the light-shielding film. No mention is made of a combination of elements or an alloy composition thereof when the second conductive layer is made of a composite material.

In JP-A-11-258633, the second conductive layer is made of chromium, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, niobium,
A method for manufacturing an array substrate for a display device, which is a metal selected from tantalum or an alloy thereof, is described. This prevents hillocks of the aluminum alloy film and further prevents corrosion of the aluminum alloy film during dry etching of the pixel electrode. No mention is made of the combination of elements when the second conductive layer is made of an alloy or the alloy composition.

[0009]

As a measure for increasing the productivity of an array substrate for a liquid crystal display device, the size of a mother glass substrate has been increased. For example, Flat Panel Display 2000, Nikkei BP, p56 (199
According to 9), the substrate size was 590 × 67 in 1998.
A production line of 0 mm ² , 600 × 720 mm ² , 650 × 830 mm ² is in operation.
mm ^2, 730 × 920mm ² of the production line is scheduled to run.

[0010] Each manufacturing apparatus is also adapted to increase the size of the mother glass substrate. In the case of a wet etching apparatus, it is almost impossible to perform uniform etching on a large-area substrate due to insufficient stirring of the liquid in the dipping method, and a shower method is used for wet etching with a large area and high uniformity. It is essential. However, as described above, when the laminated wiring of molybdenum and aluminum is collectively etched by a shower method using a solution in which phosphoric acid and nitric acid are mixed,
The molybdenum layer is processed into a wiring cross-sectional shape protruding like an eaves. The same wiring cross-sectional shape was reproduced in an experiment in which the inventors attempted batch etching of a laminated film of a molybdenum alloy and an aluminum alloy with a solution in which phosphoric acid, nitric acid, and acetic acid were mixed by a shower method. If an insulating film is formed above such a wiring shape, a problem of poor coverage occurs, which leads to a decrease in production yield.

Therefore, the present invention solves the problem that the cross section of a laminated wiring of a molybdenum alloy and an aluminum alloy is processed into a tapered shape by using a wet etching of a shower system to improve the coverage of an insulating film thereover. This is the first problem.

In order to solve the first problem, the second conductive layer is required to be resistant to dry etching with a fluorine-based gas such as SF ₆ or the like, and a contact hole or the like is formed in the SiN insulating film on the wiring. Even if the connection means is processed, the second conductive layer does not disappear at the bottom of the contact hole,
The second problem to be solved by the present invention is to make it compatible with the connection between the second conductive layer and the pixel electrode.

When a laminated wiring of an upper layer of a molybdenum alloy and a lower layer of an aluminum alloy is subjected to collective etching, the side surfaces of the lower layer are exposed to the aluminum alloy, so that hillocks may be generated from this portion. Therefore,
The third problem to be solved by the present invention is to suppress hillocks of the aluminum alloy.

Further, in solving the above problems, it is one of the problems to be solved by the present invention to ensure high production efficiency and a process margin as much as possible.

[0015]

Means for Solving the Problems The above-mentioned first problem and second problem are solved.
The first means for simultaneously solving the above problem is that the second conductive layer is made of SF ₆ equal to or more than a molybdenum-chromium alloy.
The use of a material having resistance to dry etching with a fluorine-based gas such as that described above and a wet etching rate with respect to a batch etching solution with an aluminum alloy that is sufficiently higher than that of a molybdenum-chromium alloy.

In order to discover such a material, the inventors prepared alloys in which molybdenum was added with various alloying elements of chromium, titanium, tantalum, zirconium, and hafnium at various concentrations, and the molybdenum alloys were SF ₆
The dry etching rate with a gas and the wet etching rate for a phosphoric acid-acetic acid-nitric acid solution were measured.
The results are shown in FIG. 20, where the horizontal axis represents the wet etching rate and the vertical axis represents the dry etching rate. For each alloy addition element, a diagram is obtained in which the wet etching rate and the dry etching rate decrease with the alloy addition concentration. The lower detection limit of the dry etching rate was 0.02 nm / s. The molybdenum-tantalum alloy is not suitable for the purpose of the present invention, because the wet etching rate is greatly reduced while the dry etching rate is not reduced as compared with the molybdenum-chromium alloy. The same applies to molybdenum-tungsten alloy and molybdenum-niobium alloy. In contrast, molybdenum
Zirconium and molybdenum-hafnium alloys are suitable for the purpose of the present invention because the dry etching rate is significantly reduced while the wet etching rate is not reduced as compared with the molybdenum-chromium alloy.

Although not described herein, the addition of vanadium has the effect of greatly reducing the dry etch rate.
In the case where the second conductive layer is applied to a scanning signal line, an etching selectivity with SiN of 7 or more is required as dry etching resistance of the second conductive layer. Since the dry etching rate of SiN with SF ₆ gas is 19.4 nm / s, the dry etching rate of the second conductive layer is 2.7.
If it is 8 nm / s or less, the required dry etching resistance is satisfied. The amount of zirconium required for this purpose is 2.
The content of hafnium is 6% by weight or more and the amount of hafnium added is 4.9% by weight or more. When applying the second conductive layer to a video signal line,
The dry etching resistance of the second conductive layer is required to have an etching selectivity to SiN of 14 or more. SiN SF
Dry etching rate with ₆ gases is 19.4nm / s
Therefore, if the dry etching rate of the second conductive layer is 1.39 nm / s or less, the required dry etching resistance is satisfied. The zirconium addition required for this purpose is 4.0% by weight or more, and the hafnium addition is 7.3% by weight.
That is all. In order to process the cross section of the wiring into a tapered shape by batch wet etching of the aluminum alloy and the second conductive layer, a wet etching rate at least equal to or higher than that of the aluminum alloy is required. The zirconium addition amount that satisfies this is 23% by weight or less, and the hafnium addition amount is 36% by weight or less.

Further, in order to secure a sufficient taper controllability margin using the shower system, a wet etching rate 2.4 times that of an aluminum alloy is required. The addition amount of zirconium which satisfies this is 14% by weight or less, and the addition amount of hafnium is 22% by weight or less. In addition,
The aluminum alloy was Al-9.8 wt% Nd, and the wet etching rate was 5.1 nm / s.
Note that the effects of molybdenum-zirconium and molybdenum-hafnium alloys as described above can be similarly obtained in the case of a molybdenum-zirconium-hafnium ternary alloy.

Further, depending on the wet etching conditions and the configuration of the laminated film, it may be easier to control the taper when the wet etching rate is appropriately slow. In this case, the wet etching rate can be controlled by adding an appropriate amount of chromium to molybdenum-zirconium or molybdenum-hafnium alloy. The molybdenum-titanium alloy has a slightly lower dry etching rate than the molybdenum-chromium alloy, despite the lower wet etching rate. While not as effective as molybdenum-zirconium and molybdenum-hafnium alloys, they are suitable for the purposes of the present invention. The amount of titanium added to be applied to the scanning signal line is 2.3% by weight or more, and the amount of titanium added to be applied to the video signal line is 3.4% by weight.
That is all. Further, the amount of titanium added to obtain a wet etching rate equal to or higher than that of an aluminum alloy is 6.
7 wt% or less, the amount of titanium added to ensure a sufficient taper controllability margin using a shower system is 4.0%.
% By weight or less. Further, the molybdenum-titanium alloy has an effect that a good electrical contact with the aluminum alloy can be ensured even when the film is formed on the aluminum alloy covered with the oxide film formed in the atmosphere. This is because titanium has the ability to deprive oxygen of aluminum oxide. That is, in the case of lamination of an aluminum alloy and a molybdenum-titanium alloy, continuous film formation without breaking a vacuum is not necessarily required, so that restrictions on production are reduced. In the case of a molybdenum-chromium alloy, it is impossible to achieve both dry etching resistance to be applied to a video signal line and a sufficient taper controllability margin using a shower method.

A second means for simultaneously solving the above first and second problems is to adjust the composition of an etching solution for simultaneously etching the aluminum alloy and the second conductive layer, thereby forming a wiring. It is a method of forming. That is, phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ) and acetic acid (C
In H ₃ COOH) and mixture containing water (H ₂ O), at least nitric acid (including HNO ₃₎ to 7 mol% 12 mol% or less, ammonium fluoride (NH ₄ F) and hydrogen fluoride (HF) Either one of the etchants has a composition containing a trace amount of about 0.01 to 0.1 mol%. By setting the nitric acid concentration as described above, the cross-sectional end of the resist pattern is turned up, so that the side etching rate of the second conductive layer in contact with the resist is increased, and the taper-shaped etching can be performed even in the shower method. . Further, by adding a small amount of ammonium fluoride or hydrogen fluoride, generation of etching residues on the surface of the aluminum alloy can be suppressed. By swinging the shower nozzle of the etching apparatus, the in-plane uniformity of the tapered shape is improved. In the case of shower etching using an etching solution of this composition, the wet etching rate of the molybdenum alloy is 3.8 n, which is slightly lower than that of the aluminum alloy.
Tapering can be performed even at m / s. That is, the upper limit of the amount of the alloy added to molybdenum in this case is 3.0% by weight for chromium, 26% by weight for zirconium, 41% by weight for hafnium, and 7.6% by weight for titanium. The above-mentioned third problem can be solved by forming the lower layer of the wiring from an aluminum alloy containing 0.2 at% or more, preferably 2 at% or more of neodymium. Further, in the case of a scanning signal line, the region where the second conductive layer is required for connection with the pixel electrode is only the terminal portion of the scanning signal line, and is unnecessary in the pixel portion. Therefore, by anodizing the aluminum alloy only in the pixel portion, coverage failure of the insulating film due to hillocks or the like can be sufficiently reduced. When the laminated film of the Mo-8 wt% Zr alloy and the Al-Nd alloy of the present invention is applied to the gate wiring, the upper Mo-8 wt% is used.
After the Zr film is electrochemically removed, an Al—Nd alloy is anodized, and an aluminum oxide film is selectively formed on the upper portion of the gate wiring, thereby greatly improving the reliability of the dielectric strength of the gate insulating film. . When an aluminum alloy wiring is applied to an image signal line, a contact with the semiconductor layer can be secured by providing a third conductive layer below the aluminum alloy layer. In this case, amorphous indium tin oxide (a-ITO) and indium zinc oxide (IZO), which can use a weak acid etchant, are used as the pixel electrodes so that the aluminum alloy is not damaged when the pixel electrodes are etched. It is desirable. If the aluminum alloy and the second conductive layer of the scanning signal line and the aluminum alloy and the second conductive layer of the image signal line are shared, the types of sputter targets required for producing an array substrate of the liquid crystal display device can be reduced. This is advantageous in production because the degree of freedom in the operation of the sputtering apparatus is improved. Further, by sharing the third conductive layer of the image signal line, the effect is further enhanced. On the other hand, the image signal line may be formed of a molybdenum alloy single layer. Since an aluminum alloy is not used, there is no need to consider wiring damage during pixel electrode etching, and a highly reliable polycrystalline indium tin oxide (poly-
ITO) can be employed. The molybdenum alloy used for this purpose is required to have an etching selectivity with SiN of 3.5 or more as dry etching resistance. The chromium addition amount necessary to satisfy this is 0.35 wt% or more, and the titanium addition amount is 1.3 wt. %, The zirconium addition is at least 1.4 wt%, and the hafnium addition is at least 2.6 wt%. Among these molybdenum alloys, a molybdenum-chromium alloy that can achieve both dry etching resistance and low resistivity is suitable.

[0021]

(Embodiment 1) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic sectional view of a main part for explaining an embodiment of a liquid crystal display device according to the present invention. This liquid crystal display device includes an active matrix substrate in which a thin film transistor TFT and the like are formed on the inner surface of a glass substrate 1, and a glass substrate 1.
A liquid crystal layer 1 made of a liquid crystal composition in a gap opposed to a color filter substrate having a color filter 14 and the like formed on the inner surface of the liquid crystal layer 1
8.

FIG. 2 is an embodiment of a liquid crystal display device according to the present invention. FIG. 3 is a schematic cross-sectional view of an essential part for explaining a laminated structure of gate wiring. FIG. 3 is an embodiment of the liquid crystal display device according to the present invention. FIG. 4 is a schematic cross-sectional view of a main part, illustrating an example of a stacked structure of source and drain wirings. FIG. 4 shows a structure in which a gate wiring is provided at a position distant from the thin film transistor TFT, and a wiring terminal is formed at an end thereof.

That is, as shown in FIG. 1, in the active matrix substrate, an aluminum-9.8 wt% neodymium alloy (Al-9.8 wt% Nd) is formed as an aluminum wiring 2 on the inner surface of a glass substrate 1. . Next, a molybdenum-8 wt% zirconium alloy (Mo-8 wt% Zr) is continuously formed as a molybdenum layer 3 at a film forming temperature of 120 ° C. by a sputtering method. After a resist pattern of the gate wiring is formed by photolithography, collective wet etching is performed by a shower etching method using an etching solution containing aqueous solution of phosphoric acid, nitric acid, acetic acid, and ammonium fluoride. With this etching solution, the etching rate of the Mo-8 wt% Zr alloy is about four times faster than the aluminum alloy. As a result, even if the substrate has a large area, the end face of the wiring can be formed into a forward tapered shape as shown in FIG. As a gate wiring, as shown in FIG. 3, a molybdenum-zirconium alloy (Mo-8 wt% Zr alloy) layer 2 ', an aluminum-neodymium alloy (Al-Nd alloy)
Layer 2, Molybdenum-8wt% zirconium alloy (Mo-
An 8 wt% Zr alloy) layer 3 may be continuously formed to form a three-layer structure. Although the laminated structure is more complicated than the Mo / Al two-layer structure, it has been experimentally confirmed that when a lower Mo layer is present, the forward tapered shape of the laminated structure is stably formed. . This is a phenomenon caused by a large difference between the etching states of Al and Mo. This is because the progress of etching of the upper Mo layer is stabilized by the presence of the lower Mo layer.

After the etching of the gate wiring, the resist is stripped off, and the gate insulating layer 4 of SiN is formed by plasma CVD.
A-Si layer 5 and n + a-Si layer 6 are continuously formed. Then, in order to process the island of the a-Si layer, a resist is applied in the same manner as in the processing of the gate wiring, and i is applied by dry etching.
Etching the a-Si layer 5 and the n + a-Si layer 6.

After the processing resist on the islands of the a-Si layer is stripped off, as shown in FIG. 3, the molybdenum-zirconium alloy (Mo-8) is used for source and drain wirings.
wt% Zr alloy) layer 7, aluminum-9.8 wt% neodymium alloy (Al-9.8 wt% Nd alloy) layer 8, molybdenum-8 wt% zirconium alloy (Mo-8 wt% Z)
An r alloy layer 9 is continuously formed to form a three-layer structure layer. Next, a resist for a source electrode and a drain electrode is formed by a photolithography process.

Then, in the same manner as the etching of the gate wiring, the above-mentioned multilayer structure layer is simultaneously etched by an etching solution comprising an aqueous solution to which phosphoric acid, nitric acid, acetic acid and ammonium fluoride are added. In this case, the etching rate of pure molybdenum (Mo) is aluminum (A).
Since the etching rate is much higher than 10 times the etching rate of 1), only the molybdenum layer is rapidly etched, and a good shape is not obtained. Therefore, zirconium (Zr), hafnium (Hf), titanium (T
i), tantalum (Ta) or the like is added to lower the etching rate of the alloy, and is added so as to be 1 to 4 times the etching rate of aluminum. Preferably, it is added so as to be doubled.

FIG. 5 is an explanatory diagram of the dependence of the wet etching rate of the metal wiring on the alloy addition amount. FIG. 5 also shows the wet etching rate of the aluminum-neodymium alloy.

That is, 2 wt% is added for chromium (Cr), and 5 to 20 for titanium (Ti) and tantalum (Ta).
By adding wt%, the etching rate of the molybdenum alloy can be set faster than that of aluminum (Al). Further, by adjusting the composition of the mixed acid, it becomes possible to process the end face shape of the wiring of the three-layered structure layer into a forward tapered shape.

Although the etching time is long in the continuous etching of the laminated structure layer, the adhesion between the molybdenum alloy and the resist can be greatly improved by adding titanium. In pure molybdenum, the surface oxide film easily dissolves in the developing solution, and as a result, minute cavities are formed at the interface between the resist and the laminated structure layer, and the etching solution penetrates there and the wiring becomes thin locally. Or break.

However, when the added titanium is oxidized to titanium oxide, contaminants on the surface are decomposed, and the hydrophilicity of the surface can be increased. As a result, local water spots can be prevented, and disconnection due to poor adhesion of the resist can be prevented. Similarly, the same effect was confirmed for zirconium (Zr), hafnium (Hf), and chromium (Cr) by stabilizing the oxide.

Then, the n + a-Si layer 6 is removed by dry etching using the source and drain wirings as a mask to form a channel portion.

Thereafter, the silicon nitride layer (SiN) as the passivation layer 10 is
To form a film.

In each terminal of the gate wiring and the drain wiring, a through hole is formed on each terminal. The through hole of the drain wiring is denoted by reference numeral 19 in FIG. 1, and the through hole of the gate wiring terminal is denoted by reference numeral 20 in FIG.

As shown in FIG. 4, when forming a gate wiring terminal, holes are formed in both the passivation layer 10 and the gate insulating layer 4. In this embodiment, a through-hole pattern is formed using the same photomask, and both layers are simultaneously processed by dry etching.

A layer having a high etching rate is formed on the uppermost portion of the passivation layer 10 and the uppermost portion is preferentially side-etched, so that the end surfaces of the passivation layer 10 and the gate insulating layer 4 have a forward tapered shape. Process into

Since the passivation layer 10 and the gate insulating layer 4 in the gate wiring terminal portion are thicker than the thin film transistor TFT portion shown in FIG. 1, the through hole 20 to be processed for the gate wiring terminal has a drain electrode or a source electrode. Deeper than the through hole 19. Therefore,
During the processing of the through-holes, the through-holes 19 of the drain and source wirings are processed first, and the lower electrode, that is, the electrode having the laminated structure of the aluminum alloy layer 8 and the molybdenum alloy layer 9 in FIG. You will be exposed to the atmosphere.

At this time, when the metal in the upper layer of the source electrode is pure molybdenum, the dry etching rate is high,
The surface of the aluminum layer below the pure molybdenum layer appears on the surface. FIG. 6 shows the dry etching rates when various elements were added to increase the dry etching resistance of the upper pure molybdenum layer. That is,
FIG. 6 is an explanatory diagram of the dependence of the dry etching rate of metal wiring on the amount of alloy addition. As shown in FIG. 6, all the elements studied have the effect of reducing the dry etching rate. This is presumably because the alloying increases the binding energy of each element. In the case of source and drain wirings, in order to prevent the uppermost Mo alloy film from being lost by dry etching, the selectivity with respect to the passivation film should be 14, and the dry etching rate should be 1.4 nm / s or less. is necessary. Among them, in particular, with tantalum (Ta) and tungsten (W), the dry etch rate cannot be reduced to 1.4 nm / s or less even if the added amount is increased. On the other hand, about 2.5 wt% for chromium (Cr)
%, 4 wt% for zirconium (Zr), 7.3 wt% for hafnium, and 7 wt% or more for titanium (Ti). That is, by stacking a molybdenum alloy to which the above elements are added on the aluminum layer, it is possible to prevent aluminum from appearing on the electrode surface of the through holes for the drain and source wiring terminals. After the formation of the through holes, an indium tin oxide (ITO) film serving as a pixel electrode is formed on the drain and source electrodes. In addition, in the gate and drain wiring terminals, good contact with the ITO film 11 formed thereon can be maintained well, and connection stability at the terminal portions of the wirings is ensured to improve product reliability. An apparatus can be provided. As the ITO film, a small amount of water is added during sputtering, and an amorphous ITO film is formed at room temperature. By employing an amorphous ITO film, 3% oxalic acid, which is a weak acid, can be used for the etching. By using a weak acid, ITO
When the film is etched, the selectivity of the laminated wiring formed below the passivation film with the Al film can be ensured. Instead of the weak acid, a mixed acid of hydrochloric acid, nitric acid, and water, which is an oxidizing etchant capable of forming an Al surface oxide film, may be used. As the amorphous transparent conductive film, amorphous indium zinc oxide (IZO) may be used instead of the amorphous ITO film. In this case, an argon + oxygen mixed gas is used as a sputtering gas, and a film is formed by a sputtering method at a film formation temperature in a range from room temperature to 200 ° C. Next, a configuration of a main part of an active matrix liquid crystal display device to which the present invention is applied will be described.

FIG. 7 is a schematic plan view of one pixel portion formed on an active matrix substrate of a liquid crystal display device to which the present invention is applied. 1 denotes an active matrix substrate, 2A denotes a gate wiring (electrode), 3A denotes a drain wiring, 3B denotes a drain electrode, 3C denotes a source electrode, 11A denotes a pixel electrode, 5 denotes a semiconductor layer, 19 denotes a contact hole, and TFT denotes a thin film transistor. Since the drain wiring 3A, the drain electrode 3B and the source electrode 3C have the same laminated structure, they are collectively shown as drain and source wirings (electrodes) in FIG. Further, since the drain wiring (electrode) 3A and the source wiring (electrode) 3B are interchanged during operation, they are described as drain or source wiring (electrode) in FIG. 1 for convenience of explanation.

The drain wiring 3A, the drain electrode 3B and the source electrode 3C have a laminated structure of the aluminum alloy layer 8 and the molybdenum alloy layers 7 and 9 in FIG.
The gate wiring (electrode) 2A has a laminated structure of the aluminum alloy layer 2 and the molybdenum alloy layer 3 in FIG.

Substrate 1 on which gate wiring (electrode) 2A is formed
A gate wiring (electrode) 2A and a silicon nitride (SiN) layer as a gate insulating layer 4 for interlayer insulation between the drain wiring 3A, the drain electrode 3B, and the source electrode 3C are formed over the entire surface of the semiconductor device (FIG. (Fig. 1).

Then, the gate electrode 2A and the drain wiring 3
A thin film transistor TFT is formed above the gate insulating layer 4 at one corner of the pixel region surrounded by A. In a region where the thin film transistor TFT is formed, amorphous silicon is formed on the surface of the gate insulating layer 4 located above the gate electrode 3B on the passivation layer 4 functioning as a gate insulating film so as to straddle the gate electrode 2A. A semiconductor layer 5 made of (a-Si) is formed.

The semiconductor layer 5 is formed below the formation region of the drain electrode 3B and the source electrode 3C. The reason why the drain electrode 3B and the source electrode 4 have a stacked structure of the semiconductor layer 5 is to prevent disconnection and to reduce the capacitance between the gate electrode 3A and the intersection.

A drain electrode 3B and a source electrode 3C are formed on the surface of the semiconductor layer 5 in the region where the thin film transistor TFT is formed. Are arranged facing each other.

The drain electrode 3 on the surface of the semiconductor layer 5
At the interface between B and the source electrode 3C, a contact layer in which the semiconductor layer 5 is doped with a high concentration impurity is formed, but is not shown. This high-concentration impurity layer is formed on the entire surface of the semiconductor layer 5 when the semiconductor layer 5 is formed, and the impurity layer exposed from each of the electrodes is etched using the drain electrode and the source electrode formed later as a mask. Formed by Then, the drain electrode 3B and the source electrode 3C are formed in the same step and by the same material.

Further, as shown in FIG.
C is formed so as to extend to the formation region of the pixel electrode 11A, and is configured to make contact with the pixel electrode 11A in this extending portion. In FIG. 1, this pixel electrode 11A is shown as ITO11.

A passivation layer 10 made of, for example, a silicon nitride film (SiN) is formed on the entire surface of the substrate 1 thus processed in order to avoid direct contact of the liquid crystal with the thin film transistor TFT (see FIG. 1). (Fig. 1).
In the passivation layer 10, a contact hole 19 exposing a part of the extension of the source electrode 3C is formed.

Then, in the pixel region on the upper surface of the passivation layer 10, a pixel electrode 11A made of a transparent conductive layer such as an ITO film is formed. This pixel electrode 11
A is electrically connected to the source electrode 3C through the contact hole 19.

In this case, a part of the pixel electrode 11A is formed so as to extend over another adjacent gate electrode 2A 'different from the gate electrode 2A for driving the thin film transistor TFT. An additional capacitor Cadd having a stacked body of the gate insulating layer 4 and the passivation layer 10 interposed between the adjacent gate electrode 2A 'and the dielectric film is formed.

As shown in FIG. 1, the active matrix substrate 1 on which the various films are formed as described above has the other substrate (color filter substrate) 1 with the liquid crystal layer 18 interposed therebetween.
It is bonded to 2. A plurality of color filters 14 partitioned by a black matrix 13 are provided on the liquid crystal layer LC side of the color filter substrate 12.
A common electrode 16 common to each pixel region is formed of, for example, ITO via a smooth layer 15 covering the black matrix 13 and the black matrix 13. Note that a protective film 17 is formed on the common electrode 16, and an interface between the protective film 17 and the liquid crystal layer 18.
An alignment film for regulating the alignment direction of the liquid crystal composition constituting the liquid crystal layer 18 is formed on the interface between the active matrix substrate 1 and the liquid crystal layer 18, but is not shown.

With the above-described structure, it is possible to obtain a liquid crystal display device in which various wirings (electrodes) are formed well, and connection stability at the terminals is ensured to improve product reliability. it can.

FIG. 8 is a schematic plan view illustrating a wiring structure near one pixel of an active matrix substrate constituting a liquid crystal display device to which the present invention is applied, wherein 1 is a substrate, 2A is a gate wiring, and 2A 'is an adjacent one. Gate wiring, 3A is a drain wiring, 3A 'is an adjacent drain wiring, 3B is a drain electrode,
3C is a source electrode, 11A is a pixel electrode, TFT is a thin film transistor, and Cadd is an additional capacitance element.

The central area except the periphery of the active matrix substrate 1 is a display area. As described above, in this display area, a liquid crystal layer is sealed in a bonding gap with the other substrate, a color filter substrate. ing.

In this display area, gate wirings 2A and 2A 'extending in the X direction in the figure and drain wirings 3A provided in the Y direction are formed. Further, a drain electrode 3B and a source electrode 3C extending in the Y direction while being insulated from the gate wirings 2A and 2A 'are formed.

The area surrounded by the gate wirings 2A and 2A 'and the drain wirings 3A and 3A' respectively constitutes one pixel area. That is, the display region is formed by an aggregate of a large number of pixel regions arranged in a matrix.

Each pixel region has a thin film transistor TF which is turned on by the supply of a scanning signal from the gate line 2A.
T and a pixel electrode 11A to which a video signal is supplied from the drain wiring 3A via the turned-on thin film transistor TFT are formed.

In addition to the thin film transistor TFT and the pixel electrode 11A, another adjacent scanning signal line different from the gate wiring 2A for driving the thin film transistor TFT is provided.
An additional capacitance element Cadd is formed between 2A 'and the pixel electrode 11A.

The additional capacitance element Cadd is provided for storing the video signal in the pixel electrode 5 for a long time even when the thin film transistor TFT is turned off.

In this type of liquid crystal display device, the above-described various wirings for selecting pixels are formed on the substrate 1 by using various film forming means and patterning means as described in the above embodiment. .

FIG. 9 is an exploded perspective view for explaining the whole structure of an active matrix type liquid crystal display device to which the present invention is applied. FIG. 1 illustrates a specific structure of a liquid crystal display device (hereinafter, referred to as an MDL in which a liquid crystal display panel, a circuit board, a backlight, and other components are integrated) according to the present invention.

SHD is a shield case (also called a metal frame) made of a metal plate, WD is a display window, INS1
To 3 are insulating sheets, PCB1 to 3 are circuit boards (PCB1
Is the drain side circuit board: the circuit board for driving the video signal wiring,
PCB2 is a gate-side circuit board: a circuit board for driving scanning signal wiring, PCB3 is an interface circuit board), JN1
3 is a joiner for electrically connecting the circuit boards PCB1 to 3, TCP1 and TCP2 are tape carrier packages,
PNL is a liquid crystal panel, GC is a rubber cushion, ILS is a light shielding spacer, PRS is a prism sheet, SPS is a diffusion sheet, GLB is a light guide plate, RFS is a reflection sheet, MCA
Is a lower case (mold frame) formed by integral molding, MO is an MCA opening, LP is a fluorescent tube, LPC
Denotes a lamp cable, GB denotes a rubber bush for supporting the fluorescent tube LP, BAT denotes a double-sided adhesive tape, BL denotes a backlight made of a fluorescent tube, a light guide plate, and the like. The MDL is assembled.

The liquid crystal display module MDL has two kinds of storage / holding members of a lower case MCA and a shield case SHD, and has insulating sheets INS1 to INS3 and circuit boards PCB1 to PCB1.
3. A metal shield case SHD in which the liquid crystal display panel PNL is stored and fixed, and a lower case MCA in which a backlight BL including a fluorescent tube LP, a light guide plate GLB, a prism sheet PRS and the like are stored are combined.

An integrated circuit chip for driving each pixel of the liquid crystal display panel PNL is mounted on the drain side circuit board PCB1, and an interface circuit board PCB3 receives video signals from an external host, and controls timing signals and the like. An integrated circuit chip that receives signals, a timing converter TCON that processes timing to generate a clock signal, and the like are mounted. The clock signal generated by the timing converter is connected to the interface circuit board PCB3 and the video signal line driving circuit board PCB
1 is supplied to an integrated circuit chip mounted on a circuit board PCB1 for driving a video signal line via a clock signal line CLL laid on the same.

The interface circuit board PCB3 and the video signal line driving circuit board PCB1 are multilayer wiring boards, and the clock signal line CLL is the interface circuit board PCB3 and the video signal line driving circuit board PC
It is formed as an inner wiring of B1.

The liquid crystal display panel PNL is formed by laminating a TFT substrate on which TFTs and various wirings / electrodes are formed, and a filter substrate on which a color filter is formed, and sealing a liquid crystal in a gap therebetween. , TFT-side circuit board PCB1 for driving TFT, gate-side circuit board PC
B2 and the interface circuit board PCB3 are connected by tape carrier packages TCP1 and TCP2, and the respective circuit boards are connected by joiners jN1, N2, J3.

According to the above-mentioned liquid crystal display device, it is possible to shorten the manufacturing process of various wirings and electrodes of the liquid crystal panel,
A highly reliable liquid crystal display device in which occurrence of disconnection or the like is reduced can be provided. Note that the present invention is not limited to the above-described thin film transistor type liquid crystal display device, but can be similarly applied to other types of liquid crystal display devices and other semiconductor element wiring or electrode patterning. (Embodiment 2) FIG. 10 is a schematic sectional view of a main part for explaining another embodiment of the liquid crystal display device according to the present invention. This liquid crystal display device is made of a liquid crystal composition in an opposing gap between an active matrix substrate having a thin film transistor TFT or the like formed on the inner surface of a glass substrate 1 and a color filter substrate having a color filter 14 formed on the inner surface of a glass substrate 12. The liquid crystal layer 18 is sandwiched therebetween. In the present invention, as in the first embodiment, the gate wiring is made of Mo-8 wt% Zr / Al-.
It is formed of 9.8 wt% Nd laminated wiring. Similarly, after etching the gate wiring, the resist is removed, and the gate insulating layer 4 and the ia-Si layer 5 of SiN are formed by plasma CVD.
And an n + a-Si layer 6 are continuously formed. And a-Si
In order to process the island of the layer, a resist is applied in the same manner as the processing of the gate wiring, and the ia-Si layer 5 is formed by dry etching.
And the n + a-Si layer 6 is etched.

After the processing resist on the islands of the a-Si layer is stripped off, as shown in FIG. 10, the Cr film 21 and the Cr-30 as Cr-Mo alloy are used for source and drain wirings.
A two-layer structure layer is formed by continuously forming a wt% Mo film 22. Next, a resist for a source electrode and a drain electrode is formed by a photolithography process. Then, wet etching is performed by a shower etching method using an etching solution composed of ceric ammonium nitrate, nitric acid and water. Perchloric acid may be added as a substitute for nitric acid. Using this etching solution, the Cr-3
When the 0 wt% Mo / Cr laminated wiring is etched,
Due to the difference in corrosion potential between the −30 wt% Mo film and the Cr film, the etching rate of the upper Cr—30 wt% Mo film becomes faster than that of the Cr film. It becomes possible to control the shape to the shape.

Next, using the source and drain wirings as a mask, the n + a-Si layer 6 is removed by dry etching to form a channel portion. After that, CV
A silicon nitride layer (SiN) as the passivation layer 10 is formed at 230 ° C. using the D method.

For each terminal of the gate wiring and the drain wiring, a through hole is formed on each terminal. FIG.
As shown in (1), when forming a gate wiring terminal, holes are formed in both the passivation layer 10 and the gate insulating layer 4. In this embodiment, a through-hole pattern is formed using the same photomask, and both layers are simultaneously processed by dry etching.

By forming a layer having a high etching rate on the uppermost part of the passivation layer 10 and preferentially performing side etching on the uppermost part, the end surfaces of the passivation layer 10 and the gate insulating layer 4 are formed into a forward tapered shape. Process into At this time, the Cr-
The 30 wt% Mo / Cr laminated wiring has a large selectivity of 100 or more with respect to SiN in dry etching using SF ₆ gas. Therefore, as shown in FIG. 4, when processing the through-hole 20 of the two-layer film of the passivation film / gate SiN film of the gate terminal, the Cr-3 under the through-hole 19 of the source terminal shown in FIG.
The 0 wt% Mo / Cr laminated film does not decrease. On the other hand, when the dry etching resistance is sufficiently high as in the case of the Cr alloy and the specific resistance can be suppressed low, Mo
As alloys, Mo-Ti, Mo-Zr, Mo-Hf, M
A single phase of o-Cr, Mo-W, and Mo-V can also be applied as wiring. In this case, the etching may be performed by using a wet etching solution composed of phosphoric acid, nitric acid, acetic acid, and water as in the first embodiment. After the formation of this through hole, ITO is used as a pixel electrode and as a gate terminal, source and drain electrode terminal protection film.
(Indium tin oxide) is formed by a film sputtering method. At this time, the deposition temperature was 230 ° C., and a mixed gas of argon and oxygen was used as a sputtering gas, and a polycrystalline ITO film (po
(ly-ITO film). This film is made of amorphous IT
Unlike the O film, it is difficult to perform wet etching with a weak acid, and a strong acid such as aqua regia or hydrobromic acid (HBr) having a high hydrochloric acid concentration is used. In particular, using HBr, 40 ° C
, The amount of side etching from the resist is small, and etching can be performed with high dimensional accuracy. Since a strong acid is used, it is difficult to use an Al film for the source and drain wirings sandwiching the passivation film. When the Al wiring is applied to the source and drain wirings as in the first embodiment, a passivation film made of an organic film may be added to FIG. 10 in order to improve the resistance of the passivation film to the ITO etchant. By using the poly-ITO film, it is possible to maintain good contact with the metal film layer underneath, and to improve the reliability of the product by securing the connection stability at the terminal of the wiring and improving the product reliability. Can be provided. For example, the IT in the through hole 19 shown in FIG.
The contact resistance of the O / Cr-30 wt% Mo film is 2000
It can be set as low as Ωμm ² . Cr-50wt% Mo
By increasing the amount of Mo and the amount of Mo added, the contact resistance can be set to a further lower value of 800 Ωμm ² . further,
Poly-ITO / in the through hole 20 shown in FIG.
The contact resistance of the Mo-8 wt% Zr film is 400 μm ²
And lower. In addition, by using a poly-ITO film, the contact resistance with the bump of a driver IC using an anisotropic conductive film is low, and the contact resistance value does not change with time as compared with an amorphous ITO film. Can be greatly improved. Since such a low contact resistance value between the ITO / metal wiring and between the anisotropic conductive film / ITO can be realized, the mounting of the IC can be improved more easily and more reliably than before. FIGS. 11 and 12 show an example in which a data signal is transferred between a gate and a drain driver IC chip, thereby simplifying a method of connecting a flexible printed circuit (FPC) and improving connection reliability. FIG. 11 is a cross-sectional view of a case where the semiconductor device is mounted on the glass substrate 1 by a chip-on-glass (COG) method via an anisotropic conductive film (ACF) 23. In order to realize a data transfer method between ICs, first, an Al wiring is used for a bus line so as to realize a low resistance. Furthermore, in order to realize a low contact resistance with the driver IC, M
o-8 wt% Zr, a poly-ITO film is used as a connection film under the solder ball of the IC chip. By selecting such a wiring and a terminal film material, the sheet resistance value of the bus line is 0.3Ω / □, ITO / Mo−8 wt% Zr.
The contact resistance with the film was reduced to 400 Ωμm ² ,
The contact resistance between the TO film and the anisotropic conductive particles is low and stable. By realizing such low wiring resistance and contact resistance, the driver ICs 24 are connected to each other by a bus line 25 formed of a thin film wiring formed on a TFT substrate, so that power and signals conventionally supplied to each driver IC from the FPC can be obtained. Can be sequentially transferred to the next-stage driver IC via this bus line. FIG. 12 shows a layout example of bus lines, FPCs, and driver ICs when the data transfer method is applied to both the gate side and the drain side. In FIG. 12, an FPC 26 for a gate driver is used.
Are supplied to the gate driver IC 28 through the gate power bus line and the scanning signal bus line 27.
While transferring the data between IC chips, the next IC
Write a signal to the chip. Since the load is large on the signal line side, the drive power supply voltage is supplied from the power supply FPC 29 via the power bus line 30. The data signal is
Data signal FPC 31 to data transfer bus line 32
The driver is sequentially driven while being transferred between the drain driver ICs 33 via the. By employing this method, the FPC on the gate side is eliminated and the FPC width on the drain side is minimized, so that the reliability of connection can be greatly improved and the frame of the display can be narrowed. Further, by reducing the FPC, the manufacturing cost can be reduced. (Embodiment 3) FIGS. 13 and 14 show examples in which the present invention is applied to an in-plane switching type (IPS) liquid crystal mode. FIG. 13 is a sectional view of the liquid crystal cell of FIG. 14, and FIG. 14 is a plan view. In FIG. 14, the gate wiring 2A, the counter electrode wiring 2B, and the counter electrode 2C are formed by Mo.
-8 wt% Zr / Al-9.8 wt% Nd laminated wiring is formed simultaneously. After forming the semiconductor layer, Cr-30w is used as the source electrode 3C, the drain wiring 3A, and the drain electrode 3B.
A t% Mo / Cr laminated wiring is used. Other than Cr, a Mo alloy film having dry etch resistance may be used. After forming a SiN film as a passivation layer 10 by a CVD method, a through hole 19 is formed on the source electrode by a dry etching method. A transparent comb-tooth electrode 11 is formed thereon as a pixel electrode with a poly-ITO film. The processing is performed by wet etching using hydrobromic acid (HBr). This is TF
The T substrate is completed. A black matrix layer 13, a color filter layer 14, and a surface flattening film 15 are formed on a glass substrate 12, and a color filter substrate is manufactured.
This is superimposed on the TFT substrate, and a liquid crystal 18 for IPS is used.
Inject. In this embodiment, by using the Mo / Al laminated wiring, the wiring resistance of the counter electrode formed at the same time as the gate electrode is as small as 0.3 Ω / □ in sheet resistance. A large-area IPS-type liquid crystal display device having an angle of 160 ° can be realized. In this embodiment, the source and drain wirings are Cr-30 wt% Mo.
/ Cr laminated wiring or Mo with dry etch resistance
Although the alloy single-layer wiring was used, the Mo-8w
A three-layer laminated wiring of t% Zr / Al-Nd alloy / Mo-8wt% Zr may be used. In this case, amorphous indium tin oxide (ITO) is used as the transparent pixel electrode.
By using a film or an indium zinc oxide (IZO) film and performing wet etching with aqua regia having a high concentration of weak acid or nitric acid, etching resistance to source and drain wirings can be secured. Alternatively, similar results can be obtained by dry etching using HBr gas.
As shown in FIG. 14, when the counter electrode 2B exists in the same layer as the gate wiring 2A, the number of intersections with the drain wiring 3A is two.
As a result, the probability of short circuit between the gate and the drain or between the gate and the counter electrode increases due to the defect of the gate insulating film 4 in FIG. In this case, in FIG. 13, after the Mo alloy film on the surface of the gate wiring and the counter electrode is electrochemically removed, the surface of the Al alloy is anodized, and an aluminum oxide film is selectively formed on the wiring. As a result, the gate insulating film becomes two layers of the plasma SiN film and the aluminum oxide film, and the above-mentioned interlayer short-circuit probability can be greatly reduced. (Example 4) As a gate wiring material, Mo-7wt% Z
An r-0.4% Cr / Al-9.8 wt% Nd laminated film was used. As shown in FIG. 20, chromium, as an additive element to molybdenum, has the effect of lowering the wet etching rate and the dry etching rate, like zirconium or hafnium. In the present invention, Zr and Hf, which have a relatively modest effect on the wet etching rate and easily control the laminated wiring, are mainly used as the additional elements, but chromium may be used. In particular, since chromium has a large effect even in a trace amount, for example, 0.4 wt.
%. As an effect of adding chromium, there is an advantage that the production efficiency of the sputtering target can be greatly improved in addition to the above-mentioned controllability of the etch rate. Since the melting point is lower than other elements, sinterability of the molybdenum alloy by hot isostatic pressing (HIP) is improved. As a result, the sintering density in the sputtering target is improved. Since the number of micro holes is reduced, abnormal discharge during sputtering and generation of splash caused by the existence of holes can be significantly reduced. In addition, the Mo of the laminated wiring
When removing the alloy portion by electrolytic etching or the like, it is preferable to add an appropriate amount of chromium which is easily electrolytically etched. Also in this case, since the addition has a large effect on the etching characteristics,
It is preferable to add 1 wt% or less and about 0.4 wt%. Embodiment 5 As an additive element for controlling etching characteristics, titanium has an intermediate effect between zirconium, hafnium and chromium. Therefore, Mo-5% Ti-0.4wt% Cr / Al-9.8w is used as the gate wiring.
t% Nd or Mo-6% Ti / Al-9.8wt%
Nd has a similar effect. Further, the oxide on the surface of molybdenum which is unstable in the air or an aqueous solution is replaced with titanium oxide (T
By stabilizing with iO ₂ ), resist adhesion can be improved. As a result, it is possible to prevent the penetration of the etching solution and the disconnection failure caused by the local insufficient adhesion between the resist and molybdenum. (Embodiment 6) FIG. 15 shows that the lower layer is made of Al alloy and the upper layer is made of M
The cross-sectional shape of the wiring when a laminated wiring made of an o-alloy is formed by wet etching of a shower system is shown.

First, an Al alloy 2 and M
The o-alloy 3 is continuously formed. In this embodiment, the Al alloy 240 containing 9.8 wt% Nd is used as the Al alloy 2.
and a Mo alloy 20 nm containing 1.6 wt% Cr as the Mo alloy 3 were formed by a sputtering method. Thereafter, a resist pattern is formed by photolithography, and wet etching is performed by a shower etching apparatus. In this embodiment, the etchant is phosphoric acid (H ₃ PO ₄ ) and nitric acid (HN) having a nitric acid concentration of 12 mol%.
O ₃ ), acetic acid (CH ₃ COOH) and water (H ₂ O). FIG. 15A shows a case where ammonium fluoride or hydrogen fluoride is not added to the etchant, and FIG. 15B shows a wiring cross-sectional shape when 0.01 mol% of ammonium fluoride is added to the etchant.

When ammonium fluoride or hydrogen fluoride was not added to the etchant, a beard-like product 7 was observed on the side surface of the lower Al alloy 2. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was insufficient. On the other hand, ammonium fluoride is used as an etchant.
When added in an amount of 0.1 mol%, ammonium fluoride is added in an amount of 0.1 mol%.
Similar to the case of adding mol%, the cross-sectional shape of the wiring is approximately 2
It was processed into a forward tapered shape of 5 ° to 30 °. Similarly, in the case of an etchant to which 0.01 mol% or 0.1 mol% of hydrogen fluoride is added as an alternative to ammonium fluoride,
The cross-sectional shape of the wiring was processed into a forward tapered shape of about 25 ° to 30 °. The coverage of the SiN film deposited by chemical vapor deposition on these wiring patterns was sufficient.

FIG. 16 shows that the lower layer is made of Al alloy and the upper layer is made of M
The cross-sectional shape of the wiring when a laminated wiring made of an o-alloy is formed by wet etching of a shower system is shown.

First, an Al alloy 2 and M
The o-alloy 3 is continuously formed. In this embodiment, the Al alloy 240 containing 9.8 wt% Nd is used as the Al alloy 2.
and a Mo alloy 20 nm containing 1.6 wt% Cr as the Mo alloy 3 were formed by a sputtering method. Thereafter, a resist pattern is formed by photolithography, and wet etching is performed by a shower etching apparatus. In this embodiment, the etchant is phosphoric acid (H ₃ P) containing 0.1 mol% of ammonium fluoride.
O ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and water (H ₂ O).

FIG. 16A shows the case where the concentration of nitric acid in the etchant is 5.0 mol%, and the cross section of the wiring is the upper Mo layer.
The alloy 3 had a shape protruding like an eaves. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was insufficient. FIG. 16B shows the case where the nitric acid concentration of the etchant is 7.0 mol%, and the cross-sectional shape of the wiring is approximately 4 mol%.
It was processed into a forward taper of 5 ° to 49 °. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was sufficient. FIG. 16C shows the case where the nitric acid concentration of the etchant is 9.5 mol%, and the cross-sectional shape of the wiring is approximately 35%.
It processed into the forward taper shape of ° -40 °. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was sufficient. FIG. 16D shows that the nitric acid concentration of the etchant is 1
In this case, the cross-sectional shape of the wiring is approximately 25%.
The workpiece was processed into a forward taper of 30 ° to 30 °. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was sufficient. FIG. 16E shows that the nitric acid concentration of the etchant is 1;
This is the case of 4.5 mol%. In this case, the upper Mo alloy is largely retreated by etching. Insect-like defects were observed in some wiring patterns.

FIG. 17 shows that the lower layer is made of Al alloy and the upper layer is made of M
The cross-sectional shape of the wiring when a laminated wiring made of an o-alloy is formed by wet etching of a shower system is shown. First,
An Al alloy 2 and a Mo alloy 3 are continuously formed on a glass substrate 1. In the present embodiment, 9.8 wt.
% Of Nd containing 240 nm, and Mo alloy 3 containing Cr, Hf, Zr or Ti in various C
A film having a thickness of 20 nm to which an r content was added was formed by a sputtering method. Thereafter, a resist pattern was formed by photolithography, and wet etching was performed by a shower etching apparatus. In this embodiment, as in Embodiment 1, as the etchant 6, the concentration of nitric acid is 12 mol%, and phosphoric acid (H) containing 0.1 mol% of ammonium fluoride is added.
₃ PO ₄₎ and employing nitric acid (mixture containing HNO ₃₎ and acetic acid (CH ₃ COOH) and water (H ₂ O). FIG. 17A shows the case where the Mo alloy 3 is pure Mo containing no Cr, Hf, Zr or Ti. In this case, the upper Mo alloy is largely retreated by etching. Insect-like defects were observed in some wiring patterns. FIG. 17B shows a case where the Cr content of the Mo alloy 3 is 0.4 wt%, and the cross-sectional shape of the wiring is processed into a forward tapered shape of approximately 20 ° to 25 °. Similarly, when the Hf content of the Mo alloy 3 was 12 wt%, the Zr content was 8 wt%, and the Ti content was 2 wt%, the cross-sectional shape of the wiring was similarly processed into a forward tapered shape of approximately 20 ° to 25 °. . The coverage of the SiN film deposited by chemical vapor deposition on these wiring patterns was sufficient. FIG. 17C shows a case where the Cr content of the Mo alloy 3 is 1.5 wt%, and the cross-sectional shape of the wiring is processed into a forward tapered shape of approximately 25 ° to 30 °. Hf content of Mo alloy 3 is 30wt
%, The Zr content is 20 wt%, and the Ti content is 6 wt%, the cross-sectional shape of the wiring is also approximately 25 °.
It was processed into a forward tapered shape of ３０30 °. The coverage of the SiN film deposited by chemical vapor deposition on these wiring patterns was sufficient. FIG. 17D shows a case where the Cr content of the Mo alloy 3 is 3.0 wt%, and the cross-sectional shape of the wiring is approximately 35%.
It processed into the forward taper shape of ° -40 °. H of Mo alloy 3
f content is 41 wt% and Zr content is 26 wt%
% And Ti content of 7.6 wt%, the wiring was similarly processed into a forward tapered shape of approximately 35 ° to 40 °. Si deposited by chemical vapor deposition on these wiring patterns
The coverage of the N film was sufficient. (E) of FIG.
In this case, the Cr content of the o-alloy 3 was 4.0 wt%, and the cross section of the wiring had a shape in which the upper Mo alloy 3 protruded like an eaves. Mo alloy 3 has an Hf content of 48 wt%, a Zr content of 32 wt%, and a Ti content of 9 wt%
Similarly, in the case of the above, the Mo alloy 3 of the upper layer had a shape protruding like an eave. The coverage of the SiN film deposited by chemical vapor deposition on these wiring patterns was insufficient.

FIG. 18 shows that the lower layer is made of Al alloy and the upper layer is made of M alloy.
The cross-sectional shape of the wiring when a laminated wiring made of an o-alloy is formed by wet etching of a shower system is shown.

First, an Al alloy 2 and M
The o-alloy 3 was formed continuously. In this embodiment, the Al alloy 2 is 240 nm having various Nd contents, and the Mo alloy 3 is a Mo alloy 20 containing 1.5 wt% of Cr.
nm was formed by a sputtering method. Thereafter, a resist pattern was formed by photolithography, and wet etching was performed by a shower etching apparatus. In this embodiment, the concentration of nitric acid is 12 mol% as an etchant.
Phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COO) containing 0.1 mol% of ammonium fluoride.
A mixture containing H) and water (H ₂ O) was employed. After the wet etching, the wiring pattern was heat-treated at 300 ° C. in a vacuum.

FIG. 18A shows the case where the Nd content of the Al alloy 2 is 9.8 wt%, and the cross-sectional shape of the wiring is approximately 2%.
It was processed into a forward tapered shape of 5 ° to 30 °. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was sufficient. FIG. 18B shows a case where the Nd content of the Al alloy 2 is 0.49 wt%, and a protruding product which seems to be a hillock is formed on the side surface of the Al alloy layer of the wiring. The coverage of the SiN film deposited by chemical vapor deposition on this wiring pattern was insufficient. The Nd content of the Al alloy 2 is 0.1.
In the case of 98 wt%, similarly to FIG. 18A, the cross-sectional shape of the wiring was processed into a forward tapered shape of approximately 25 ° to 30 °. However, when the temperature of the heat treatment in vacuum after the wet etching is set to 350 ° C., as in FIG.
A protruding product considered to be a hillock was formed on the side surface of the alloy layer. (Embodiment 7) FIG. 19 is a schematic view of a wet etching method using shower etching. While horizontally transporting the glass substrate by roller transportation, the etching liquid is supplied in a shower shape from above. In the figure, the substrate advances in a direction perpendicular to the plane of the paper. The etching nozzle irradiates the etching liquid radially from each point source. At this time, in order to improve the uniformity of the etching, by disposing the nozzles such that the respective etching showers partially overlap, uniform etching can be performed without supply unevenness. But,
Mo-8 wt% Zr / Al- which is the wiring material of the present invention
In the etching of the 9.8 wt% Nd multilayer wiring, there is a problem that the etching rate changes due to a slight variation in the shower flow distribution. In particular, the Al film is characterized in that the higher the flow rate, the lower the etch rate. As a result, as shown in FIG. 19, in a region where the shower flow rate is large immediately below the nozzle, the etch rate is low, and as a result, the side etch amount is low. The opposite phenomenon occurs in the nozzle overlap region, and as a result, variation in the side etch amount occurs due to the nozzle distribution. As a result, the in-plane distribution of the dimensional accuracy of the wiring deteriorates, and the image quality of the liquid crystal display varies. In the present invention, Mo alloy / Al
In the etching of the laminated wiring of the alloy, the etching nozzle is swung in a direction perpendicular to the horizontal transfer direction of the substrate. The optimal swing angle depends on the spread angle from the nozzle, but is preferably 40 ° to 100 °. By oscillating the nozzle, the shower flow rate was averaged over time, and as a result, the side etch amount, that is, the variation in wiring dimensions could be significantly reduced. Depending on the composition of the etching solution, the etching of the Mo film may progress even by rinsing with water after the etching. In this case, it is necessary to make the water displacement rate during rinsing uniform in the substrate plane, and it was also confirmed that the shower nozzle swinging treatment was effective in that case.

[0079]

As described above, the gate wiring (electrode), the source and drain wiring (electrode) are mainly composed of molybdenum, and at least one of chromium, titanium, tantalum, and niobium in which molybdenum is dissolved. , An aluminum alloy layer and an alloy layer containing as an additive element make it easy to reduce the resistance of the wiring to increase the area of the screen, and to simplify the photo-etching process of the wiring and electrodes. As a result, a highly reliable liquid crystal display device which is low in cost and free from display defects can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a main part for explaining an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a schematic cross-sectional view of a main part, illustrating a two-layer laminated structure of an embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is a schematic cross-sectional view of an essential part for explaining an example of a three-layer laminated structure of an embodiment of the liquid crystal display device according to the present invention.

FIG. 4 is a schematic cross-sectional view of an essential part for explaining an example of a structure of a wiring terminal at an end of a gate wiring in an embodiment of the liquid crystal display device according to the present invention.

FIG. 5 is an explanatory diagram of the dependence of the wet etching rate of metal wiring on the amount of alloy addition.

FIG. 6 is an explanatory diagram of the dependence of the dry etching rate of metal wiring on the amount of alloy addition.

FIG. 7 is a schematic plan view of one pixel portion formed on an active matrix substrate of a liquid crystal display device to which the present invention is applied.

FIG. 8 is a schematic plan view illustrating a wiring structure near one pixel of an active matrix substrate that constitutes a liquid crystal display device to which the present invention is applied.

FIG. 9 is an exploded perspective view illustrating an overall configuration of an active matrix liquid crystal display device to which the present invention is applied.

FIG. 10 is a schematic cross-sectional view of a main part illustrating one embodiment of a liquid crystal display device according to the present invention.

FIG. 11 is a schematic cross-sectional view of a driver IC mounting portion of one embodiment of the liquid crystal display device of the present invention.

FIG. 12 is a plan view of a driver IC mounting portion of one embodiment of the liquid crystal display device of the present invention.

FIG. 13 is a schematic sectional view of a main part for explaining an embodiment of a liquid crystal display device according to the present invention.

FIG. 14 is a plan view of a pixel portion of a liquid crystal display device illustrating one embodiment of a liquid crystal display device according to the present invention.

FIG. 15 is an embodiment showing a cross-sectional shape of a wiring according to the present invention.

FIG. 16 is an embodiment showing a cross-sectional shape of a wiring according to the present invention.

FIG. 17 is an embodiment showing a cross-sectional shape of a wiring according to the present invention.

FIG. 18 is an example showing a cross-sectional shape of a wiring according to the present invention.

FIG. 19 is an embodiment of an etching method in the method for manufacturing a liquid crystal display device of the present invention.

FIG. 20 shows the dependence of the wet etch rate and the dry etch rate of the present invention on the amount of alloying elements added.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Active matrix substrate, 2 ... Aluminum alloy layer, 2A ... Gate bus line, 2B ... Counter electrode wiring, 2
C: counter comb electrode, 3: molybdenum alloy layer, 3A: drain wiring, 3B: drain electrode, 3C: source electrode, 4
... gate insulating layer, 5 ... semiconductor layer (ia-Si layer), 6
... contact layer (n + a-Si layer), 7, 9 ... molybdenum alloy layer, 8 ... aluminum alloy layer, 10 ... passivation layer, 11 ... transparent conductive layer (ITO), 11A ... pixel electrode, 12 ... color filter substrate, 18 ... Liquid crystal layer, 1
9, 20: through hole, 21: Cr film, 22: Cr-
Mo alloy film, 23 anisotropic conductive film, 24 driver chip, 25 bus line, 26 F for gate line
PC, 27: Power bus line and scanning signal bus line, 28: Gate driver IC, 29: Power supply F
PC, 30: power bus line, 31: F for data signal
PC, 32: data transfer bus line, 33: drain driver for drain, 34: etching shower nozzle,
35 ... Etching liquid shower.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 301 G02F 1/136 500 5F043 21/306 H01L 21/306 F 5F110 21/3205 21/88 F 29/786 R 29/78 612C 616U 616V 617T 617U (72) Katsu Tamura 1-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Kenichi Onizawa Hitachi City, Ibaraki Prefecture 7-1-1, Omika-cho Hitachi Research Laboratories Hitachi Research Laboratory, Ltd. (72) Inventor Masanori Terakado 3300 Hayano, Mobara-shi, Chiba In-house Display Group, Hitachi, Ltd. 7-1-1, Machi-cho, Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Ochiai Takahiro 3300 Hayano, Mobara-shi, Chiba Prefecture, Hitachi, Ltd.Display Group (72) Inventor Masaru Takahata 3300, Hayano, Mobara-shi, Chiba Prefecture, Japan Display Group, Hitachi, Ltd. (72) Inventor Hideaki Yamamoto 3300 Hayano, Mobara-shi, Chiba F-term in Hitachi Display Group (reference) 2H090 LA01 LA15 2H091 GA02 GA03 LA12 2H092 GA17 GA25 GA29 HA04 HA06 JA26 JA34 JA46 JB22 JB31 JB51 JB57 JB69 KA05 KB24 MA05 MA13 MA18 MA19 MA24 NA28 NA29 PA08 4M104 AA10 BB02 BB36 BB38 BB39 CC05 DD08 DD12 DD17 DD64 FF08 FF13 GG20 HH13 5F033 HH10 HH17 HH38 JJ01 Q10 MM10 KK10 KK10 KK10 QQ20 QQ35 QQ39 RR06 SS15 VV06 VV15 WW04 XX02 XX10 XX33 5F043 AA22 AA27 BB18 DD13 DD15 FF03 5F110 AA03 AA16 BB01 CC07 DD02 EE06 EE14 EE15 EE23 EE37 EE44 FF03 FF2 4 FF30 GG02 GG15 GG35 GG45 HK06 HK09 HK16 HK22 HK35 HL07 HM03 HM19 NN02 NN24 NN35 NN72 QQ05 QQ09

Claims (28)

[Claims] 1. A liquid crystal display device comprising a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein a plurality of scanning signal lines formed on one of the pair of substrates, Any one of the plurality of video signal lines intersecting in a matrix includes a stacked structure including a first conductive layer and a second conductive layer, wherein the first conductive layer contains Al as a main component and the second conductive layer The layer is mainly composed of Mo containing Zr.
A liquid crystal display device wherein the content of r is not less than 2.6% by weight and not more than 23% by weight. 2. A liquid crystal display device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates, wherein a plurality of scanning signal lines formed on one of the pair of substrates; Any one of the plurality of video signal lines intersecting in a matrix includes a stacked structure including a first conductive layer and a second conductive layer, wherein the first conductive layer contains Al as a main component and the second conductive layer The layer is mainly composed of Mo containing Zr.
A liquid crystal display device, wherein the content of r is not less than 4.0% by weight and not more than 14% by weight. 3. The first conductive layer according to claim 1, wherein the second conductive layer is mainly composed of Mo containing Zr and Hf.
3. The liquid crystal display device according to 1. 4. The liquid crystal display device according to claim 1, wherein the scanning signal line has a laminated structure including a first conductive layer and a second conductive layer. 5. The liquid crystal display device according to claim 1, wherein at least one pair of pixel electrodes formed on one of the pair of substrates is provided in a plurality of pixels formed in a region surrounded by the plurality of scanning signal lines and the video signal lines. And a counter electrode, the pixel electrode is supplied with a video signal from the video signal line via a thin film transistor driven based on the supply of a scanning signal from the scanning signal line, and the counter electrode is The reference voltage is supplied via a counter voltage signal line formed over a plurality of pixels, and the stacked structure including the first conductive layer and the second conductive layer has a stacked structure including the counter voltage signal line or the 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a counter electrode. 6. The liquid crystal display device according to claim 1, wherein the first conductive layer containing Al as a main component is anodized. 7. A liquid crystal display device having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein a plurality of scanning signal lines formed on one of the pair of substrates, One of the plurality of video signal lines crossing in a matrix has a three-layer structure including a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer is mainly composed of Al. Wherein the second conductive layer is mainly composed of Mo containing Zr, the third conductive layer is mainly composed of Mo, and the second conductive layer is mainly composed of Mo.
A liquid crystal display device wherein the content of r is not less than 4.0% by weight and not more than 14% by weight. 8. The liquid crystal display device according to claim 7, wherein said second conductive layer is mainly composed of Mo containing Zr and Hf. 9. The liquid crystal display device according to claim 7, wherein the scanning signal line has a laminated structure including a first conductive layer and a second conductive layer. 10. The liquid crystal display device according to claim 1, wherein at least one pair of pixel electrodes formed on one of the pair of substrates is provided in a plurality of pixels formed in a region surrounded by the plurality of scanning signal lines and the video signal lines. And a counter electrode, the pixel electrode is supplied with a video signal from the video signal line via a thin film transistor driven based on the supply of a scanning signal from the scanning signal line, and the counter electrode is A reference voltage is supplied via a counter voltage signal line formed over a plurality of pixels, and a three-layer structure including the first conductive layer, the second conductive layer, and the third conductive layer is provided. The liquid crystal display device according to claim 7, wherein the liquid crystal display device is the counter voltage signal line or the counter electrode. 11. A liquid crystal layer sandwiched between a pair of substrates, a plurality of scanning signal lines formed on one of the pair of substrates, a plurality of video signal lines intersecting the scanning signal lines in a matrix, A thin film transistor driven based on the supply of a scanning signal from the scanning signal line; a pixel electrode to which a video signal from the video signal line is supplied via the thin film transistor; In a liquid crystal display device including a counter electrode to which a reference voltage is supplied via a voltage signal line, one of the scanning signal line, the video signal line, the counter voltage signal line, and the counter electrode includes a first conductive layer and a second conductive layer. The first conductive layer includes Al as a main component, and the second conductive layer includes Cr and 2.6% to 23% by weight of Zr.
A liquid crystal display device comprising o as a main component. 12. The liquid crystal display device according to claim 11, wherein said scanning signal line and said counter voltage signal line have a laminated structure including a first conductive layer and a second conductive layer. . 13. The semiconductor device according to claim 1, wherein the second conductive layer is formed on the first conductive layer, and the cross section of the first conductive layer is formed in a trapezoid having a forward tapered shape. Item 12. The liquid crystal display device according to any one of Items 1, 7, and 11. 14. The scanning signal line is disposed on the same layer as a counter voltage signal line and a counter electrode, and the video signal line is disposed on a layer above the scanning signal line via a first insulating film. Is disposed above the video signal line via a second insulating film, the pixel electrode is disposed on the second insulating film, and the pixel electrode is connected via connection means provided on the second insulating film. The liquid crystal display device according to claim 5, wherein the liquid crystal display device is connected to a layer mainly containing Mo containing Zr. 15. The liquid crystal display device according to claim 14, wherein said pixel electrode is made of one of ITO and IZO. 16. The device according to claim 1, wherein said pixel electrode is made of polycrystalline indium tin oxide (ITO), and said video signal line is a laminate of a Cr—Mo alloy film and a Cr film.
5. The liquid crystal display device according to 4. 17. The liquid crystal display device according to claim 14, wherein the pixel electrode is IZO, and the video signal line is a Mo alloy / Al alloy / Mo alloy laminate. 18. A gate wiring, a common wiring,
Common electrode, gate insulating layer, semiconductor layer, contact layer,
An active matrix substrate on which source and drain wiring, a passivation layer, and a pixel electrode are formed; a color filter substrate on which a color filter layer, a smooth layer, a common electrode, and an insulating protective layer are formed on an insulating substrate; A liquid crystal layer made of a liquid crystal composition is sandwiched between opposing gaps of the filter substrate.
A liquid crystal display device, wherein source and drain wirings are formed by a laminated wiring of an alloy layer of Ti containing Mo as a main component and an Al alloy layer. 19. A gate wiring, a common wiring,
Common electrode, gate insulating layer, semiconductor layer, contact layer,
An active matrix substrate on which source and drain wiring, a passivation layer, and a pixel electrode are formed; a color filter substrate on which a color filter layer, a smooth layer, a common electrode, and an insulating protective layer are formed on an insulating substrate; A liquid crystal layer made of a liquid crystal composition is sandwiched between opposing gaps of the filter substrate. The gate wiring is made of two layers of a titanium alloy and an aluminum alloy. A liquid crystal display device having a layer structure. 20. A gate wiring, a common wiring,
Common electrode, gate insulating layer, semiconductor layer, contact layer,
An active matrix substrate on which source and drain wiring, a passivation layer, and a pixel electrode are formed; a color filter substrate on which a color filter layer, a smooth layer, a common electrode, and an insulating protective layer are formed on an insulating substrate; A liquid crystal layer made of a liquid crystal composition is sandwiched between opposing gaps of the filter substrate, and the source and drain wirings contain 0.35% by weight or more of Cr or 1.
3% by weight or more of Ti or 1.4% by weight or more of Z
A liquid crystal display device having a single-layer structure of r or an alloy containing Mo as a main component containing 2.6% by weight or more of Hf. 21. A step of forming a metal thin film on a glass substrate, a step of forming a resist pattern on the metal thin film by photolithography, and using an etchant of phosphoric acid (H ₃
PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and water (H ₂ O), containing 7 mol% to 12 mol% of nitric acid (HNO ₃ ) and ammonium fluoride (NH
₄ F) and a method of manufacturing a liquid crystal display device comprising the steps of carrying out wet etching at least either the composition from about 0.01 comprising about 0.1 mole%, of hydrogen fluoride (HF). 22. The method according to claim 20, wherein the metal thin film comprises: Al or an Al alloy;
22. The method for manufacturing a liquid crystal display device according to claim 21, wherein the method is configured by continuously forming a Mo alloy. 23. The aluminum alloy according to claim 1, wherein said aluminum alloy has at least 0.98 watts.
23. The method of manufacturing a liquid crystal display device according to claim 22, wherein the aluminum alloy contains neodymium in an amount of t% or more, preferably 9.8% by weight or more. 24. The Mo alloy according to claim 1, wherein said Mo alloy is not less than 0.84% by weight.
0 wt% or less chromium or 4.9 wt% or more and 41 wt% or less hafnium or 2.6 wt% or more and 26 wt%
The following zirconium or 2.3 wt% or more and 7.6 wt%
23. The method for manufacturing a liquid crystal display device according to claim 22, which is a molybdenum alloy containing the following titanium. 25. The method according to claim 25, wherein the Al alloy is at least 0.2 at.
% Or more, preferably 2 at% or more, of an aluminum alloy containing neodymium, and the Mo alloy contains 0.84 to 3.0% by weight of chromium or 4.9 to 41% by weight of chromium.
3. A molybdenum alloy containing not more than 2.6% by weight of hafnium, not less than 2.6% by weight and not more than 26% by weight of zirconium, or not less than 2.3% by weight and not more than 7.6% by weight of titanium.
2. A method for manufacturing a liquid crystal display device. 26. The method according to claim 22, wherein the Mo alloy layer and the Al alloy layer are formed by simultaneous etching with the same etching solution. 27. The gate line is disposed on the same layer as a common line and a common electrode, the drain line is disposed on a gate insulating film provided on the gate line, and the pixel electrode is disposed on the drain line. The pixel electrode is disposed on a passivation layer provided as an upper layer, and the pixel electrode is connected to an alloy layer containing Mo as a main component through a contact hole provided in the passivation layer. Dry etching for processing, and an etching selectivity of the passivation layer to a molybdenum alloy containing at least one of chromium, titanium, zirconium, hafnium, and vanadium as an additive element of the source and drain wirings is set to 7 or more. A method for manufacturing a liquid crystal display device characterized by the above-mentioned. 28. An etching solution is supplied onto a substrate having a metal thin film formed on a transparent insulating substrate in a shower form from a plurality of etching nozzles disposed above the substrate while horizontally transporting the substrate in the air. In the method of manufacturing a liquid crystal display device, wherein the metal thin film is etched, the metal thin film is a laminated wiring of Mo or a Mo alloy and Al or an alloy thereof, and the etching nozzle is arranged in a direction perpendicular to a horizontal transport direction of the substrate. A method for manufacturing a liquid crystal display device, characterized in that the liquid crystal display device swings.