JP2001308224A - Package for chip component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip component package that solves problems of degraded electrical characteristics of reflection and propagation, which are caused by the impedance mismatch because of a structural difference between a lead terminal and a package circuit when the chip component package and an external circuit board are electrically connected. SOLUTION: The chip component package with a cavity to accommodate the chip component has a dielectric part 11 with a conductor pattern 11a, which the chip component is electrically connected to, and the dielectric part 12 with an externally extended conduction part 12a that is laminated on the upper surface of the dielectric part 11a and connected to the conductor pattern 11a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for chip components, and more particularly to a package for chip components which can be electrically connected to an external circuit without deteriorating transmission characteristics of high frequency signals and the like. -With respect to di.

[0002]

2. Description of the Related Art Conventionally, a package on which a high-frequency integrated circuit is mounted, for example, has a high-frequency integrated circuit mounted on a dielectric substrate, and a high-frequency integrated circuit in the package and a conductor pattern of an external circuit board. A high-frequency signal line for connecting to a circuit is provided on or on the surface of a dielectric substrate, and a package is mounted on a surface of a predetermined external circuit board to input and output signals. In such a high-frequency package, it is required to form a package structure and a signal line capable of inputting and outputting a high-frequency signal to and from an external circuit board without deteriorating high-frequency signal characteristics.

FIGS. 8A and 8B are schematic views showing the main parts of a conventional package for such a chip component, wherein FIG. 8A is a perspective view, and FIG. 8B is a sectional view taken along the line BB in FIG. Is shown. Mounting holes 73a are provided on both side surfaces of the frame 73,
The dielectric portion 71 is disposed in the mounting hole 73a such that one end thereof is pulled out from the side surface of the frame 73 to the outside in a direction perpendicular to the side surface. The dielectric portion 72 is stacked and arranged in the mounting hole 73a on the upper surface of the dielectric portion 71. A plurality of conductor patterns 71a for electrically connecting the inside and outside of the frame are formed on the surface of the dielectric portion 71,
The conductor pattern 71a is configured to be electrically connected to a joint of the conductor pattern 76a formed on the external printed circuit board 76 via an external lead terminal 75.

[0004] In the package for a chip component configured as described above, an external lead terminal 75 and an external printed circuit board 76 are provided.
Between the upper conductor pattern 76a and the external lead terminal 75
Since the line structure of the conductor greatly differs between the conductor pattern 71a and the package, the mismatch of the characteristic impedance becomes large, and the conductor pattern on the external lead terminal 75 and the external printed board 76 becomes large. The signal reflection due to the characteristic impedance mismatch at the junction with the external lead terminal 75a and the junction with the external lead terminal 75 and the conductor pattern 71a of the package is increased.

[0005]

In the package for chip components shown in FIG. 8, the external lead terminals 75 are used when electrically connecting to the external printed circuit board 76, as described above. Therefore, the line structure of the conductor is significantly different between the external lead terminal 75 and the conductor pattern 76a on the external printed circuit board 76 and between the external lead terminal 75 and the conductor pattern 71a of the package. In addition, the mismatch of the characteristic impedance is likely to be large, so that the external lead terminals 75 and the conductor pattern on the external printed circuit board 76 are not easily formed.
Signal reflection due to characteristic impedance mismatch at the junction with the lead 76a and the junction between the external lead terminal 75 and the conductor pattern 71a of the package is likely to increase, and the signal transmission characteristics However, there was a problem that the steel was deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has an object to increase the bonding strength between a package and an external circuit board.
A package for chip parts which is capable of reducing the mismatch of the characteristic impedance of the part to be electrically joined and reducing the signal reflection, and particularly has excellent transmission characteristics in a high frequency range.
The purpose is to provide

[0007]

In order to achieve the above object, a package for chip parts according to the present invention is provided with a package for a chip part having a cavity for accommodating chip parts. Wherein a conductor pattern to which the chip component is electrically connected is formed.
And a second dielectric portion having a conductive portion laminated on the upper surface of the first dielectric portion and connected to the conductor pattern and drawn to the outside. Features.

[0008] According to the chip component package (1), the first dielectric portion on which the conductor pattern to which the chip component is electrically connected is formed, and the upper surface of the dielectric portion. And a second dielectric portion having a conductive portion connected to the conductor pattern and drawn out to the outside. Therefore, the conductive portion of the second dielectric portion and the conductor of the external circuit are provided. And a conductive pattern between the conductor pattern of the first dielectric part and the conductive part of the second dielectric part, and a conductive part of the second dielectric part. Electrical connection can be made without significantly changing the line structure of the conductor between the conductive portion and the conductor pattern of the external circuit. Therefore, it is possible to reduce the mismatch of the characteristic impedance at the connection portion and reduce the reflection loss.

Further, a package for a chip component according to the present invention is provided.
The chip (2) is the chip component package (1), wherein the conductive portion is a terminal plate, a metal foil, or a conductor pattern.
It is characterized by being formed of any one of the following.
According to the package for chip components (2) described above, according to the shape of the package and the bonding method with the external circuit board,
Any of a terminal plate, a metal foil, and a conductor pattern may be selected as the form of the conductive portion of the second dielectric portion, and the form is adapted to various types of packages and the form of the external circuit board. Can be.

[0010] A package for chip parts according to the present invention.
The die (3) is characterized in that, in the chip component package (1) or (2), a metal part is laminated on the second dielectric part. According to the chip component package (3), the second dielectric portion includes:
Since the metal portion is laminated, the second dielectric portion can be reinforced, and the shielding effect and the heat radiation characteristics can be enhanced.

Further, a package for chip parts according to the present invention is provided.
The package (4) is a package (1) to
(3) In any one of the constitutions (3), an external connection pad portion for connecting to the outside is formed on the second dielectric portion. Package for chip components described above
According to the device (4), since the external connection pad for connecting to the outside is formed in the second dielectric portion, the connection with the external circuit pattern is facilitated and the connection is made easily. Strength can be increased.

Further, a package for a chip component according to the present invention is provided.
The chip (5) is the package for chip parts (1) to
(4) In any one of (4) and (4), the chip component is an integrated circuit for high-frequency driving. According to the chip component package (5), since the chip component is a high-frequency driving integrated circuit, the characteristic impedance of the connection portion with the outside, which is particularly problematic in a high-frequency range, is not matched. The problem that the transmission characteristics become large and the transmission characteristics are easily deteriorated can be solved, and a package for chip parts having excellent transmission characteristics can be obtained.

Further, a package for chip parts according to the present invention is provided.
The package (6) is a package (1) to
(5) In any one of the constitutions (5), the second dielectric portion is surface-connected to an external substrate. According to the chip component package (6) described above,
Since the second dielectric portion is surface-connected to the external substrate, it can be easily mounted on the external substrate and cost can be reduced.

Further, a package for a chip component according to the present invention is provided.
The package (7) is a package (1) to
(5) In any one of the constitutions (5), the second dielectric portion is inserted and connected to an external substrate. According to the chip component package (7) described above,
Since the second dielectric part is inserted and connected to the external substrate, the conventional insertion connection using lead terminals can be replaced by the first part of the package without changing this form. (2) The conductive portion of the dielectric portion can be inserted and connected to the external substrate, thereby reducing the characteristic impedance mismatch at the electrical connection portion, reducing the reflection loss, and connecting strength with the external circuit substrate. Can be increased.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a package for a chip component according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram schematically showing a main part of a package for chip components according to an embodiment (1), (a) is a perspective view,
(B) is a sectional view taken along line BB in (a).

The dielectric portion 11 is made of ceramic or the like, and is installed inside a frame 15 made of metal or the like. On the upper surface of the dielectric portion 11, a conductor pattern 11a is provided.
And one end thereof is connected by wire bonding to a chip component (not shown), which is an integrated circuit for high-frequency driving mounted in a cavity inside the frame 15, and the other end is laminated on the upper surface of the dielectric portion 11. It is electrically connected to the conductive part 12a of the dielectric part 12 to be arranged. Dielectric part 12
Are stacked on the upper surface of the dielectric portion 11 with one end thereof pulled out from the side surface of the frame 15 to the outside in a direction perpendicular to the side surface. On the joint surface with the dielectric part 11,
A conductive portion 12a made of a conductor pattern that is conductive with the conductor pattern 11a is formed, and the conductor pattern of the external circuit board 16 is formed.
Is electrically connected to the connection 16a. The metal plate portion 13 laminated on the upper surface of the dielectric portion 12 supplements the mechanical strength of the dielectric portion 12 and at the same time imparts a shield effect against noise and further enhances the heat radiation characteristics of the package. Plays a role. A metal seal portion 14 joined above the metal plate portion 13 and the frame body 15 has a lid (not shown) made of metal or the like for hermetically sealing the inside of the package above the metal seal portion 14. It is designed to be joined and sealed with glass, resin, brazing material or the like.

The dielectric portion 11 and the dielectric portion 12
Is formed using an inorganic material such as a glass ceramic, a resin material, a resin-ceramic composite material, or the like, in addition to a ceramic material such as alumina or mullite. The dimensions such as the length should be set according to the signal characteristics and characteristic impedance of the chip component used. The conductor pattern 11a and the conductive portion 12a are formed using a metal material such as copper, silver, gold, tungsten, molybdenum, and the like, and the thickness and width of the conductor pattern 11a and the conductive portion 12a are determined by the signal characteristics and characteristics of the chip component used. It should be set according to the impedance and the like. Examples of the constituent material of the metal plate portion 13 include, for example, a copper-tungsten alloy, a copper-molybdenum alloy, an iron-nickel-cobalt alloy, an iron-nickel alloy, and the like. It is appropriately set in consideration of the heat radiation characteristics of the chip component used, the strength of the dielectric portion 12, the consistency of the thermal expansion coefficient, and the like.

According to the chip component package 10 described above, the conductor pattern 1 to which the chip components are electrically connected.
A dielectric portion 11 having a dielectric portion 1a formed thereon and a dielectric portion 12 having a conductive portion 12a, which is laminated on the upper surface of the dielectric portion 11 and is connected to the conductor pattern 11a and drawn out, are provided. Therefore, by electrically connecting the conductive portion 12a of the dielectric portion 12 and the conductive pattern 16a of the external circuit board 16, the conductive pattern 11a of the dielectric portion 11 and the conductive portion 12a of the dielectric portion 12 are electrically connected. , And between the conductive portion 12a of the dielectric portion 12 and the conductor pattern 16a of the external circuit board 16 without significantly changing the line structure of the conductor. Therefore, it is possible to reduce the mismatch of the characteristic impedance at the electrical connection portion and reduce the reflection loss.

In the package 10 for a chip component according to the first embodiment, the conductive portion 12a is formed of a conductor pattern, but the conductive portion 12a is limited to a conductor pattern. Instead, the conductive portion 12a of the dielectric portion 12 may be made of a terminal plate or a metal foil having an appropriate line length or line width in accordance with the shape of the package and the bonding method with the external circuit board. -An appropriate conductive portion can be selected according to the type and shape of the die, and the mismatch in characteristic impedance at the electrical connection portion can be reduced to easily reduce the reflection loss.

Further, since the chip component is a high-frequency driving integrated circuit, the problem that the characteristic impedance mismatch at the connection portion with the outside, which is particularly problematic in the high-frequency range, becomes large, and the transmission characteristics are easily degraded is solved. And a package 10 for chip parts having excellent transmission characteristics.
The conductive portion 12a of the dielectric portion 12 and the external circuit board 16
Since the upper conductor pattern 16a is surface-connected, the mounting of the chip component package 10 on the external circuit board 16 becomes easy, so that the bonding strength can be increased and the cost can be reduced. .

FIG. 2 is a schematic view showing a package for chip components according to the embodiment (2), wherein (a) is a plan view,
(B) is a front view, (C) is a side view. FIG.
FIG. 4 is a schematic diagram showing a state in which the package for chip components according to Embodiment (2) is mounted on an external circuit board;
(A) is a plan view, (b) is a cross-sectional view taken along the line BB in (a).

The connecting member 26 is formed by connecting the package to a heat sink 32.
(FIG. 3 (b)) for fixing to an external member such as a copper-tungsten alloy having excellent heat transfer characteristics, and bolts (not shown) inserted near both ends. Mounting hole 26a is provided. A frame 25 made of metal or the like is joined onto the connection member 26 by a method such as brazing, and the frame 25 has a housing portion 25b for installing the dielectric portions 21 and 22. A cylindrical body 27 made of metal or the like is joined to one side surface of the frame 25, and an optical fiber or the like is inserted into the cylindrical body 27. A substantially central portion of the inner area of the frame 25 is provided with a space 25 for mounting chip components (not shown) such as photoelectric conversion elements.
a. A dielectric portion 21 is installed in the housing portion 25b of the frame 25, and a chip component mounted inside the package and a circuit board 31 outside the package (FIG. 3) are provided on the surface of the dielectric portion 21. And a conductor pattern 21a for electrical connection between the conductor pattern 21a. This conductor pattern
The transmission line 21a can have a transmission line structure such as a microstrip line, a strip line, or a grounded coplanar. By adjusting the transmission line structure pattern, the conductor pattern 21a as a signal line can be formed. The characteristic impedance can be adjusted. One end of the conductor pattern 21a is provided with a pad portion 2 for electrically connecting the conductor pattern 21a to a chip component (not shown).
1b.

On the upper surface of the dielectric portion 21, the dielectric portion 22 is stacked and arranged with one end thereof being drawn out from the side surface of the frame 25 in the direction perpendicular to the side surface. A conductive portion 22a that is electrically connected to the conductor pattern 21a is formed on a joint surface of the dielectric portion 22 with the dielectric portion 21.
The conductive portion 28 electrically connects the chip components inside the package and the circuit board 31 outside the package with the component 21a and the conductive portion 22a. Further, a bonding pad portion 22b for bonding to the external circuit board 31 is formed at one end of the conductive portion 22a which is drawn out. The conductive portion 22a can have a transmission line structure such as a microstrip line, a strip line, or a grounded coplanar. By adjusting the transmission line structure pattern, the conductive portion 22a as a signal line can be formed. The characteristic impedance can be adjusted.

The metal plate portion 23 laminated on the upper surface of the dielectric portion 22 is made of, for example, a copper-tungsten alloy or the like, and supplements the mechanical strength of the dielectric portion 22 and at the same time has a shielding effect on noise. And further serves to enhance the heat dissipation characteristics of the package. A metal seal portion 24 is joined above the frame 25 and the metal plate portion 23, and a lid (not shown) made of metal or the like for hermetically sealing the inside of the package is provided above the metal seal portion 24. ) Are joined by soldering, brazing, or the like.

When the chip component package 20 constructed as described above is used, in FIG. 3, signals are transmitted from the conductor pattern 31a of the external substrate 31 to the conductive portion 22a from the pad portion 22b at the end of the conductive portion 28. , A conductor pattern 21a, and a pad part 21b at the end of the conductor pattern 21a are inputted from a bonding wire to a chip component (not shown), while the bonding wire and the conductor pattern 21a are inputted from the chip component. The signal is output from the pad portion 22b at the end of the conductive portion 28 to the conductor pattern 31a of the external substrate 31 via the pad portion 21b at the end portion, the conductor pattern 21a, and the conductive portion 22a.

As is clear from the above description, according to the package 20 for the chip component according to the embodiment (2), the dielectric member in which the conductor pattern 21a to which the chip component is electrically connected is formed. And a dielectric portion 22 provided on the upper surface of the dielectric portion 21 and having a conductive portion 22a connected to the conductor pattern 21a and drawn to the outside. Conductive part 22a and external circuit board 3
The first conductor pattern 31a and the second conductor pattern 31a can be electrically connected to each other.
And the conductive portion 22a of the dielectric portion 22
a and the conductor pattern between the conductor pattern 31a of the external circuit board 31 can be electrically connected without greatly changing the line structure of the conductor. Therefore, it is possible to reduce the mismatch of the characteristic impedance at the electrical connection portion and reduce the reflection loss.

Further, since the connecting member 26 is joined to the frame 25, the frame 25 can be reinforced and the amount of heat generated by the chip component package 20 can be efficiently reduced via the joining member 26. 32 can be dissipated, and the heat dissipation characteristics can be further improved. Further, since the external connection pad portion 22b for connecting to the external circuit board 31 is formed at one end of the conductive portion 22a of the dielectric portion 22, the external circuit board 31
Can be easily joined to the conductor pattern 31a, and the joining strength can be increased.

The package 20 for a chip component according to the embodiment (2) shown in FIGS. 2 and 3 shows an example in which there are 14 external signal terminals. The number of terminals in the package is not limited to 14 at all. In the package 20 for a chip component according to the embodiment (2), the dielectric portions 21 and 2
2 has been described as having one layer each. However, in another embodiment, these dielectric portions 21 and 22 may have a multilayer structure.

In the package 20 for a chip component according to the above embodiment (2), the case where the dielectric portion 22 is drawn out perpendicular to the side surface of the package has been described. In the embodiment, the dielectric portion 22 may be pulled out in the direction of the lower surface in parallel with the side surface of the package. With such a configuration, one end of the dielectric portion 22 is formed on the external circuit board 31 through the transparent portion. It is also possible to electrically connect the conductive portion 22a to the wiring pattern on the external circuit board side by inserting it into the hole. According to such a configuration, since the dielectric portion 22 is inserted and connected to the external circuit board 31, the conventional structure using lead terminals for insertion connection can be used without changing this form. The conductive portion 22a of the dielectric portion 22 of the package can be inserted and connected to the external circuit board 31, thereby reducing the characteristic impedance mismatch at the electrical connection portion, reducing the reflection loss, and reducing the external loss. The connection strength with the circuit board can be increased.

In the package for chip components according to the embodiment (2), an optical fiber is used as the chip component.
Has been described, but the package for chip components according to the present invention is not limited to this, and the chip components to be mounted may be other than IC chips. Any type of chip parts can be used as long as it can process electric signals. In addition to the above-mentioned types, the present invention can be applied to QFP type packages. The present invention can be applied to any type of package that has been connected to an external circuit board by using.

[0031]

EXAMPLES AND COMPARATIVE EXAMPLES The results of analyzing the high-frequency signal passing characteristics and reflection characteristics of the packages using the chip component packages according to the examples and the comparative examples will be described below. FIG. 4A is a partial plan view showing a connection portion between a package and an external circuit board in a package having a conventional structure according to Comparative Example 1, and FIG. B
It is a line sectional view. FIG. 5A is a partial plan view showing a connection portion between the package and an external circuit board in the package having the structure according to the first embodiment of the present invention, and FIG.
FIG. 3 is a sectional view taken along line BB in FIG.

In Comparative Example 1 shown in FIG.
A signal line layer 41a is formed on the surface of the frame 1 with a frame body 44 formed of a dielectric portion 42 and a metal seal portion 43 interposed therebetween, and a ground layer 45 is formed around the signal line layer 41a via a gap g.
Are formed. Also, on the back surface of the dielectric substrate 41,
A ground layer 45 is formed. This signal line layer 41a
The conductor pattern 50a on the external circuit board 50 side is electrically connected to the conductor pattern 50a via a lead terminal 46 by soldering or the like.
In addition, a ground layer 50b is formed on the external circuit board 50.

The specifications of each member in the comparative example are shown below. Constituent material of dielectric substrate 41: alumina (ε _r 9.7) Thickness T ₁ : 0.4 mm Constituent material of dielectric substrate 42: alumina (ε _r 9.7) Thickness T ₂ : 0.4 mm Metallic sheath Material of complete part 43: Complete conductor Thickness T ₃ : 0.4 mm Material of signal line layer 41a: Perfect conductor Width W ₁ : 1.2 mm Width W ₂ : 0.6 mm Length l ₃ : 1.5 mm Length l ₄ : 1.5 mm length l ₅ : 1.5 mm width g _{1 of} gap g: 0.3 mm material of lead terminal 46: perfect conductor width W ₃ : 0.5 mm length l ₆ : 2.0 mm Thickness T ₅ : 0.15 mm Material of ground layer 45: perfect conductor Material of ground layer 50 b: perfect conductor Material of conductor pattern 50 a: perfect conductor Width W ₄ : 1.5 mm Length l ₁ : 1. 5mm constituent material of the external circuit board 50: FR4 (ε _r 4.7) thickness T _9: In the structure of Embodiment 1 shown in .3mm Figure 5, the signal line 61a on the surface of the dielectric substrate 61 is formed, a ground layer 65 is formed around the signal line 61a through the gap g. On the upper surface of the dielectric substrate 61, a dielectric portion 62 is laminated in a state of being drawn out of the dielectric substrate 61, and a signal line layer 62a is formed on the joint surface thereof. Is electrically connected to the signal line layer 61a by soldering or the like. The signal line layers 61a, 6 at this junction
The line width of 2a is set to be narrower than the line width of other portions. The ground layer 65 is formed on the back surface of the dielectric substrate 61. The signal line layer 62a is electrically connected to the conductor pattern 50a on the external circuit board 50 side. The external circuit board 50 has a ground layer 50.
b is formed.

The specification of each member in the embodiment will be described below. Constituent material of dielectric substrate 61: Alumina (ε _r 9.7) Thickness T ₁₁ : 0.4 mm Constituent material of dielectric substrate 62: Alumina (ε _r 9.7) Thickness T ₁₂ : 0.4 mm Metal plate 63 of the material: perfect conductor thickness T _13: the material of 0.4mm signal line 61a: complete conductor width W _11: 1.2 mm width W _12: 0.6 mm length l _14: 3.0 mm length l _15: 1.5 mm Constituent material of the signal line layer 62a: perfect conductor Width W ₁₃ : 1.2 mm Length l ₁₂ : 0.5 mm Length l ₁₃ : 0.5 mm Length l ₁₄ : 3.0 mm Width g _{2 of} gap g : 0.3 mm Width g _{3 of} gap g: 0.65 mm Constituent material of ground layer 65: perfect conductor FIG. 6 shows high-frequency transmission characteristics (S21) in Comparative Example 1 and Example 1 described above. FIG. 7 shows the reflection characteristics (S11). The pass characteristics (S21) shown in FIG. 6 indicate that the closer to zero the value is, the smaller the loss is and the better the pass characteristics are.
In a frequency band exceeding 0 GHz, the pass characteristics are significantly reduced. On the other hand, in the case of the embodiment, 5.0 GH
In the frequency band up to z, excellent pass characteristics are shown with almost no decrease in pass characteristics. Further, in the reflection characteristics (S11) shown in FIG. 7, the value according to the example is considerably smaller than that of the comparative example, indicating excellent reflection characteristics.

As is clear from the above results, in the embodiment according to the present invention, it is possible to reduce the mismatch of the characteristic impedance at the junction, and to improve the transmission characteristic and the reflection characteristic. Was.

[Brief description of the drawings]

FIG. 1A is a partial perspective view schematically showing an embodiment (1) of a package for chip components according to the present invention,
(B) is a sectional view taken along line BB in (a).

FIG. 2 is a package for a chip component according to the embodiment (2).
FIGS. 3A and 3B are schematic views showing the same, wherein FIG. 3A is a plan view, FIG. 3B is a front view, and FIG.

FIG. 3 is a package for a chip component according to the embodiment (2).
FIGS. 3A and 3B are schematic diagrams showing a state when the device is mounted on an external circuit board, wherein FIG. 3A is a plan view, and FIG.
It is a line sectional view.

4A and 4B are schematic views showing a structure simulating a package for a chip component according to a comparative example, in which FIG. 4A is a partial plan view, and FIG.
FIG. 3 is a sectional view taken along line BB in FIG.

5A and 5B are schematic views showing a structure simulating a package for a chip component according to an embodiment, wherein FIG. 5A is a partial plan view and FIG.
FIG. 3 is a sectional view taken along line BB in FIG.

FIG. 6 is a graph showing pass characteristics (S21) in models according to a comparative example and an example.

FIG. 7 is a graph showing reflection characteristics (S11) in models according to a comparative example and an example.

FIG. 8A is a partial perspective view schematically showing a main part of a conventional package for chip components, and FIG.
FIG. 3 is a sectional view taken along line BB in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Package for chip components 11 Dielectric part 11a Conductive pattern 12 Dielectric part 12a Conductive part 13 Metal plate part 14 Seal part 15 Frame

Claims (7)

[Claims] 1. A chip component package having a cavity for accommodating a chip component, comprising: a first dielectric portion having a conductor pattern to which the chip component is electrically connected; A second dielectric portion having a conductive portion laminated on the upper surface of the first dielectric portion and connected to the conductor pattern and drawn to the outside. Package. 2. The chip component package according to claim 1, wherein said conductive portion is formed of any one of a terminal plate, a metal foil, and a conductor pattern. 3. The chip component package according to claim 1, wherein a metal portion is laminated on said second dielectric portion. 4. The device according to claim 1, wherein an external connection pad portion for connecting to the outside is formed in the conductive portion of the second dielectric portion. Package for chip parts. 5. The package for a chip component according to claim 1, wherein said chip component is a high frequency driving integrated circuit. 6. The package for a chip component according to claim 1, wherein said second dielectric portion is surface-connected to an external substrate. 7. The chip component package according to claim 1, wherein said second dielectric portion is inserted and connected to an external substrate.