JP2001306321A - Processor - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A conventional processor for performing predication has a problem that it is impossible to achieve both an improvement in execution efficiency and an improvement in program efficiency particularly in implementing multidirectional branching. SOLUTION: The processor of the present invention is a processor that performs predication under at least a first condition and predication under a second condition based on a single operation designation. The two conditions are not mutually exclusive. Further, the processor of the present invention is a processor that performs at least predication under the first condition, predication under the second condition, and predication under the third condition based on a single operation designation, First condition, second condition and third condition
It is characterized in that none of the two conditions are the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor using predication, and in particular, to a VLIW (Ver.
The present invention relates to a technique of predication suitable for a processor of a Long Instruction Word (y) type.

[0002]

2. Description of the Related Art With the development of electronic technology in recent years, high-performance processors have become widespread and used in all fields.
Such a processor achieves high performance by parallel processing of instructions. An architecture called VLIW is also one form of instruction parallel processing. A processor employing the VLIW architecture (hereinafter referred to as a “VLIW processor”) includes a plurality of arithmetic units inside and a slot provided for one instruction. Performs the operations specified in multiple fields simultaneously, in parallel. Such a VL
The machine instruction program of the IW processor is generated after parallel processing at the operation level in a program described in a high-level language is detected and scheduled by a compiler. The machine instruction program is also called an execution code.

[0003] A technique called predication is a technique in which a branch instruction is replaced with a conditional execution instruction so that a branch instruction is not apparent from a machine instruction program and the number of operations executed in parallel is increased.
Often used in combination with an IW processor. A conditional execution instruction is an instruction that executes a specified function if the condition is true and does not execute the function if the condition is false. The condition is held in a register called a predication register.

A VLIW processor in the prior art using predication is known, for example, as described in Nikkei BP, Nikkei Electronics, November 29, 1999, pp. 138-153.

FIG. 7 is a list as an example of a machine instruction program of the above-mentioned conventional processor, and both (a) and (b) of FIG. 7 realize the flowchart shown in FIG. However, the processor here assumes that the number of slots in one instruction is always three. FIG.
Determines whether the variable Y is positive, 0, or negative. If it is positive, subtracts the variable P from the variable X and assigns it to the variable X. If it is 0, assigns the variable X to the variable Y. It is a flowchart of a processing example of a three-way branch in which a variable P is added to a variable X and substituted for the variable X if negative. Where the variable
It is assumed that X is assigned to the register R1, the variable Y is assigned to the register R2, the variable P is assigned to the register R3, and the register R0 is a zero register (a register whose contents are always 0). Although FIG. 3 shows only the three-way branch and the process immediately after the branch, it is assumed that some process precedes and succeeds before and after the three-way branch.

FIG. 7 (a) realizes three-way branching by two-stage comparison. The third slot of instruction 1 is a comparison operation that sets the predication register p0 to 1 if true and the predication register p1 to 1 if false for the condition that register R2 is greater than zero. The first slot of the instruction 2 is a subtraction operation for storing the subtraction result of the register R3 from the register R1 into the register R1 only when the predication register p0 is 1, and the second slot is used when the predication register p1 is 1. Is a comparison operation that sets the predication register p2 to 1 if true for the condition that the register R2 is equal to 0, and sets the predication register p3 to 1 if false. The first slot of the instruction 3 is a transfer operation for transferring the register R1 to the register R2 only when the predication register p2 is 1,
The slot stores the addition result of register R1 and register R3 in register R1 only when predication register p3 is 1.
Is an addition operation to be stored. Slots other than those described above are operations based on the processing before and after the processing in FIG. 3 and which can be executed in parallel with each of the above operations in the same instruction (no operation if there is no significant operation). Yes, here we call it OP. Predication is not performed in the OP operation. Conventional processors execute these instruction sequences one instruction at a time in one cycle. The first comparison operation is performed in the first cycle, and if it is true, the subtraction operation is performed in the second cycle. If false, a compare operation is performed in the second cycle; if it is true, a transfer operation is performed in the third cycle; if false, an add operation is performed in the third cycle. If the first compare operation is true, the third cycle does nothing. Since the operation of the OP operation is not the main focus, the description is omitted.

FIG. 7 (b) shows a three-way branch realized by performing three comparisons simultaneously. The first slot of instruction 1 is a comparison operation that sets the predication register p0 to 1 if true and the predication register p1 to 1 if false for the condition that register R2 is greater than 0, and the second slot is Is a comparison operation that sets the predication register p2 to 1 if true for the condition that the register R2 is equal to 0, and sets the predication register p3 to 1 if false, and the third slot is that the register R2 is smaller than 0. Is true, the predication register p4 is set to 1 if true, and the predication register p5 is set to 1 if false. The first slot of the instruction 2 is a subtraction operation for storing the subtraction result of the register R3 from the register R1 into the register R1 only when the predication register p0 is 1, and the second slot is used when the predication register p2 is 1. Is a transfer operation that transfers the register R1 to the register R2 only when the predication register p4 is 1.
This is an addition operation for storing the addition result of R1 and the register R3 in the register R1. Conventional processors perform three comparison operations in parallel in a first cycle and a second
In the cycle, a subtraction operation is performed if the first comparison operation is true, a transfer operation is performed if the second comparison operation is true, and an addition operation is performed if the third comparison operation is true.

[0008]

However, in the above-mentioned prior art, there is a problem that it is impossible to achieve both an improvement in execution efficiency and an improvement in program efficiency. What is execution efficiency?
The term “program efficiency” refers to a measure of how long a specific process can be realized, and the term “program efficiency” refers to a measure of the size of a program that can realize a specific process.

In the machine instruction program shown in FIG. 7A, the three-way branch and the processing immediately after the branch shown in the flowchart of FIG. 3 can be achieved in five slots, and although the program efficiency is high, the execution requires three cycles. Is low. On the other hand, in the machine instruction program shown in FIG. 7B, the same processing can be executed in two cycles and the execution efficiency is high, but the required processing requires six slots, so the program efficiency is low.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a processor which achieves both improvement in execution efficiency and improvement in program efficiency. Note that the above-mentioned number of slots does not include the OP operation based on the processing other than the processing in the three-way branch and the processing immediately after the branch because it is not the main focus of the comparison.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

In order to solve the above-mentioned problems, a first processor of the present invention comprises a predication under at least a first condition and a predication under a second condition based on a single operation designation. A processor for performing predication, wherein the first condition and the second condition are not mutually exclusive.

[0013] The second processor of the present invention may further include a predication under at least the first condition, a predication under the second condition, and a third predicate based on a single operation designation.
A processor that performs predication under the following condition, wherein none of the first condition, the second condition, and the third condition are the same condition.

The third processor of the present invention performs predication under the first condition, predication under the second condition, and predication under the third condition based on a single operation designation. A processor, wherein a total set is formed by three unions of the first condition, the second condition, and the third condition.

In the third processor, the operation specification relates to a comparison operation between a first operand and a second operand, and the first condition is that the first operand is the second operand.
Even if the second condition is a condition that the first operand and the second operand are equal, and the third condition is a condition that the first operand is smaller than the second operand, Good.

In the third processor, the operation designation is related to an arithmetic operation, the first condition is a condition that the operation result is positive, and the second condition is a condition that the operation result is zero. The third condition may be a condition that the operation result is negative.

In each of the first to third processors, the operation designation relates to an arithmetic operation, and a condition that an arithmetic result overflows may be included in the condition of the predication.

A fourth processor according to the present invention, based on a single arithmetic operation specification, performs predication under the first condition, predication under the second condition, predication under the third condition, and the fourth A processor that performs predication under the condition (1) and predication under the condition (5), wherein the first condition is a condition that the operation result overflows in the positive direction, and the second condition is a condition that the operation result overflows. Is a positive condition that does not overflow, the third condition is a condition that the operation result is zero, the fourth condition is a condition that the operation result is negative that does not overflow, and the fifth condition is Is a condition that the operation result overflows in the negative direction.

In the first processor, both the first condition and the second condition may be explicitly specified in an instruction.

Here, the designation of the first condition and the second condition
May be performed by extending the area on the instruction for specifying the normal operation.

A fifth processor according to the present invention is a processor that performs predication under at least one condition based on a single operation specification, and includes a region on an instruction for specifying an operand accompanying the operation specification. It is characterized in that it shares an area on an instruction for designating a storage location of a result of the success or failure of the condition accompanying the prediction.

In the fifth processor, the operation specification includes an instruction area for specifying three operands of a first source operand, a second source operand, and a destination operand. And a region on the instruction for specifying the storage location of the result of the success or failure of the condition accompanying the predication may be shared.

In the fifth processor, the operation specification may include an instruction area for specifying three operands of a first source operand, a second source operand, and a destination operand. And a region on the instruction for specifying the storage location of the result of the success or failure of the condition accompanying the predication may be shared.

In the fifth processor and the processor according to each of the above-described embodiments, the area on the shared instruction is an area for specifying an operand or an area for specifying a storage destination of a condition success / failure result accompanying predication. May be determined based on whether or not the operation specified by the operation specification is a comparison operation.

Here, when the operation specified by the operation specification is a comparison operation, the area on the instruction related to the sharing may be an area for specifying a storage destination of a condition success / failure result accompanying the predication. Good.

In the first processor, the storage destination of the condition success / failure result accompanying the predication under the first condition and the storage destination of the condition success / failure result accompanying the predication under the second condition are both included in the instruction. It may be specified explicitly.

In each of the above processors, the processor may be a long instruction processor that specifies a plurality of operations in one instruction.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1. 1. Instruction Configuration FIG. 1 is an instruction configuration diagram of the processor according to the embodiment of the present invention. FIG. 7A shows an instruction format, in which one instruction is composed of three slots each having 21 bits.
An unused word field (indicated by ud in the figure) consists of a total of 64 bits of instruction word. Each slot can basically specify an operation equally. Each 21-bit slot has a 4-bit opcode (op field), a 4-bit destination operand (dst field), a 4-bit first source operand (sra field), and a 4-bit second source operand or predication destination. It consists of a nation operand (srb / pd field), a 1-bit control field (c field), and a 4-bit evaluation predication operand (qp field).
Are assigned. The c field is a field for switching whether the srb / pd field is the second source operand or the predication destination operand, and is 3 when no predication destination operand is specified.
Operand type operation can be realized. When a predication destination operand is specified, a two-operand format is used in which the dst field is shared as a second source operand as needed.

Each field has the following functions. The op field is from 0000 MOV (transfer operation) to 1111 N
Sixteen types are assigned to OP (no operation). Note that the CMPL (conditional comparison operation) can be exceptionally specified only for the first slot. The dst and sra fields select one of registers R0 through R15. Here, the register R0 is a zero register (a register whose content is always 0). The srb / pd field functions as specifying the second source operand when the c field is 0, and registers R1 to R1.
Select one of the five. When the c field is 1, it functions as the designation of the predication destination operand, and selects and designates one of the predication registers p0 to p14 as the destination for storing the truth of the satisfaction of the condition after the operation. (If the c field is 1, 1111 of the srb / pd field is invalid). In the qp field, in the case of 0000 to 1110, one of the predication registers p0 to p14 is selected and designated as a predication register for evaluating whether the condition is satisfied before the operation. If the qp field is 1111, it is always treated as true (condition fulfilled) and no predication is performed.

Next, conditions reflected in the predication register and how to reflect the conditions will be described. FIG.
As shown in the bit string of the op field in (b), c
If the field is 1, the truth of two or more conditions is reflected in the predication register. ADD, SUB, MUL, D
For the IV operation, the truth of the condition that the operation result is positive is stored in the predication register specified by the srb / pd field, and the truth of the condition that the operation result is 0 is stored in srb / pd.
In the predication register next to the predication register specified by the pd field, the truth of the condition that the operation result is negative is added to the predication register next to the predication register specified by the srb / pd field. Store them in registers. For ADDV and SUBV operations, the true / false condition of the operation result overflowing in the positive direction is stored in the predication register specified by the srb / pd field, and the true / false condition of the positive condition that the operation result does not overflow is stored in the srb / pd field. In the predication register next to the predication register specified by, the truth of the condition that the operation result is 0 is stored in the predication register next to the predication register specified by the srb / pd field. The true / false condition of the condition that the operation result does not overflow is stored in the predication register of the third next number to the predication register specified by the srb / pd field. Fourth next to the predication register specified in the srb / pd field Respectively stored in the predication register number. For AND, OR, and XOR operations, the true / false of the condition that the operation result is 0 is stored in the predication register specified by the srb / pd field.
Is stored in the predication register next to the predication register specified by the srb / pd field. For the CMP operation, sr determines whether the operand specified in the sra field is greater than the operand specified in the dst field.
In the predication register specified by the b / pd field, the truth of the condition that the operand specified by the dst field is equal to the operand specified by the sra field is set.
dst is added to the predication register next to the predication register specified by the srb / pd field.
Determines whether the condition that the operand specified by the sra field is smaller than the operand specified by the field is 2 in the predication register specified by the srb / pd field.
The next number is stored in the predication register.

The CMPL operation is exceptionally the first and second
The operation is specified using the two slots, and an arbitrary plurality of conditions can be specified. However, the operation code can specify only the first slot. The first condition to be compared is specified in the dst2 field of the second slot, and the second condition is specified in the sra2 field of the second slot. As shown in FIG. 1B, 0000 is eq (equal) to 1001 (unsigned). You can specify 10 types up to a small equal. Here, since the magnitude relation differs depending on whether the numerical value is regarded as signed or unsigned, here two types of signed relation and unsigned are prepared for the four conditions of magnitude relation.
The truth of the first condition is stored in the predication register specified by the srb / pd1 field of the first slot, and the truth of the second condition is written next to the predication register specified by the srb / pd1 field of the first slot. In the predication register.

The other operations when the c field is 1 and all the operations when the c field is 0 are not reflected in the predication register. Note that the value stored in the predication register is 1 when all operations are true.
If false, set to 0. The numbers of the predication registers refer to numbers from 0 to 14 corresponding to the predication registers p0 to p14, respectively.
The number following 14 is wrapped round to 0.

In the NOP operation, the op field is 1111
The other fields can be anything. 2. Configuration of Processor FIG. 2 is a schematic configuration diagram of a processor according to the embodiment.

This processor includes an instruction fetch stage (hereinafter, IF stage), a decoding and register reading stage (hereinafter, DEC stage), and an execution stage (hereinafter, EX stage).
(Stage) in a three-stage pipeline structure.

In FIG. 2, 1 is a ROM for storing a machine instruction program, and 2, 3 and 4 store the contents of a first slot, a second slot and a third slot of a machine instruction (hereinafter abbreviated as an instruction). I1 latch, I2 latch and I3 respectively
Latches 5, 5 and 6 are first instructions for decoding the contents of the first, second and third slots of the instructions held in I1 latch 2, I2 latch 3 and I3 latch 4, respectively, and controlling the respective sections of the processor. Decryptor, second command decoder, and third
An instruction decoder, 8 is a register file for storing operands, 9 and 10 and 11 are a part of the contents of I1 latch 2, I2 latch 3 and I3 latch 4, respectively, and a register file 8
And a D1 selector for selecting one from two inputs of the
2 selector and D3 selector, and 12, 13 and 14 are D1 selector 9, D2 selector 10, and D3 selector 1, respectively.
D11 latch, D12 latch and D1
3 latches, 15, 16 and 17 are D21 latches, D22 latches and D23 latches for storing the output of the register file 8, and 18 is an arithmetic logic operation or load / store operation using the contents of the D11 latches 12 and 15. A first operation unit for performing operations, 19 is a D12 latch 13
And a second operation unit 20 for performing all operations such as arithmetic logic operation and load / store using the contents of the D22 latch 16, and a second operation unit 20 including arithmetic logic operation and load / store using the contents of the D13 latch 14 and the D23 latch 17. The first operation unit 18 is a third operation unit that performs the operation of
The outputs of the second operating unit 19 and the second operating unit 20 are both connected to the register file 8 and an external memory (not shown). 21, 22, and 23 receive the operation results of the first operation unit 18, the second operation unit 19, and the third operation unit 20, respectively, and change the true / false state of establishment of some of the predication conditions shown in FIG. 1. The first state generation unit, the second state generation unit, and the third state generation unit to be generated, 24 are the first state generation unit 21
, Second state generating unit 22 and third state generating unit 2
3 is stored in a predication register, and a predication register having a predication register therein for evaluating the contents of the predication register and determining whether to execute each operation from the first slot to the third slot. Unit. The registers R0 to R15 are included in the register file 8, and particularly, 0 is always read from the register R0. The operation is not guaranteed if a value is written to register R0.
3. Example of Operation of Processor Hereinafter, the operation of the processor having the above configuration when the machine instruction programs of FIGS. 4 to 6 are stored in the ROM 1 will be described.

(1) First Machine Instruction Program FIG. 4 is a list of a first example of a machine instruction program, which implements the flowchart for the three-way branch and the processing immediately after the branch shown in FIG. Instruction 1 first
The slot and the second slot are operations based on a process (not shown) preceding or succeeding the process of FIG. 3 and can be executed in parallel with an operation of a third slot described later (when there is no significant operation, No operation)
Here, it is described as OP. Predication is not performed in the OP operation. In the third slot, the predication register p0 is set to 1 if the condition that the register R2 is greater than 0 is set, and if the condition is true for the condition that the register R2 is equal to 0, the predication register p1 is set to 1; If the condition that R2 is smaller than 0 is true, this is a comparison operation that sets 1 to the predication register p2. The first slot of the instruction 2 is a subtraction operation for storing the subtraction result of the register R3 from the register R1 into the register R1 only when the predication register p0 is 1, and the second slot is used when the predication register p1 is 1. Register R1 only
Is transferred to the register R2. In the third slot, the addition result of the register R1 and the register R3 is registered only when the predication register p2 is 1.
This is an addition operation to be stored in R1. FIG. 4 shows the machine instruction program as a mnemonic, which is stored in the ROM 1 in binary. For example, in the third slot of the instruction 1, the op field is 1010 (CMP), and the dst field is
0010 (R2), sra field is 0000 (R0), srb / pd field is 0000 (p0), c field is 1, qp field is 1
111 (always true), the first slot of instruction 2 has an op field of 0010 (SUB), a dst field of 0001 (R1), s
The ra field is 0011 (R3), and the srb / pd field is 0001 (R
1), the c field is 0, and the qp field is 0000 (p0).

Next, the operation of the processor when the machine instruction program of FIG. 4 is stored in the ROM 1 will be described in the order of timing called a machine cycle. Since the operation of the OP operation is not the main focus, detailed description will be omitted. (Timing 1) IF stage: Instruction 1 Instruction 1 is read from ROM1, and the first to third slots of instruction 1 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 2) DEC stage: Instruction 1 The first slot of instruction 1 stored in I1 latch 2 is the first
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the operation is an operation (corresponding to an OP operation). Some registers are read from the register file 8 as needed based on the decoding. At the same time, I2
The second slot of the instruction 1 stored in the latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is also found that the operation is some sort of operation (corresponding to an OP operation). Some registers are read from the register file 8 as needed based on the decoding. At the same time, the third slot of the instruction 1 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of decryption
It turns out to be a CMP operation. Based on this decoding, registers R2 and R0 are read from register file 8, and the read values are stored in D13 latch 14 and D23 latch 17, respectively. IF stage: instruction 2 Instruction 2 is read from ROM1, and the first to third slots of instruction 2 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 3) EX stage: Instruction 1 Based on the result decoded by the first instruction decoder 5, the first operation unit 18 and the first state generation unit 21 perform desired operations. At the same time, the second operation unit 19 and the second state generation unit 22 perform desired operations based on the result decoded by the second command decoder 6. At the same time, D13
The operation of comparing the value of the register R2 stored in the latch 14 with the value 0 of the register R0 stored in the D23 latch 17 is performed in the third operation unit 20, and the third state generation unit 23 performs the operation of comparing the value of the register R2. If the value is larger than the value of the register R0, 1 is written to the predication register p0 of the predication unit 24, otherwise 0 is written. If the value of the register R2 is equal to the value of the register R0, 1 is written to the predication register p1. Otherwise, write 0, and if the value of the register R2 is smaller than the value of the register R0, write 1 to the predication register p2, otherwise write 0. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the SUB operation is based on the evaluation of the predication register p0. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D11 latch 12 and the D21 latch 15, respectively. At the same time, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is determined that the operation is the MOV operation based on the evaluation of the predication register p1. Based on the decoding, the register R1 is read from the register file 8, and the read value is stored in the D22 latch 16. At the same time, the third slot of the instruction 2 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the ADD operation is based on the evaluation of the predication register p2. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D13 latch 14 and the D23 latch 17, respectively. (Timing 4) • EX stage: Instruction 2 Based on the fact that the result decoded by the first instruction decoder 5 is a SUB operation based on the evaluation of the predication register p0, the value of the register R1 stored in the D11 latch 12 is calculated. A subtraction operation for reducing the value of the register R3 stored in the D21 latch 15 is performed in the first operation unit 18, and the operation result is stored in the register R1 of the register file 8. Since the c field is 0 and the pd field is invalid, the first state generation unit 21 does nothing. At the same time, the second
Based on the fact that the result decoded by the instruction decoder 6 is a MOV operation based on the evaluation of the predication register p1,
The transfer operation of the value of the register R1 stored in the D22 latch 16 is performed by the second operation unit 19, and the operation result is stored in the register R2 of the register file 8. Since the c field is 0 and the pd field is invalid, the second state generation unit 22 does nothing. At the same time, the third
Based on the fact that the result decoded by the instruction decoder 7 is an ADD operation based on the evaluation of the predication register p2,
The value 1 of the register R1 stored in the D13 latch 14 and D2
An addition operation is performed by the third operation unit 20 with the value of the register R3 stored in the 3-latch 17, and the operation result is stored in the register R4 of the register file 8. Since the c field is 0 and the pd field is invalid, the third state generation unit 23 does nothing.

As described above, the three-way branch and the processing immediately after the branch shown in the flow chart of FIG. 3 which conventionally require three cycles of five slots or two cycles of six slots can be executed in two cycles of four slots in the processor of this embodiment. It is possible to achieve both execution efficiency and program efficiency. Note that the above-mentioned number of slots does not include the OP operation based on the processing other than the processing in the three-way branch and the processing immediately after the branch because it is not the main focus of the comparison.

(2) Second Machine Instruction Program FIG. 5 is a list of a second example of the machine instruction program. The third slot of instruction 1 consists of registers R1 and R2
Is stored in the register R1. If the addition result is true for the condition that the addition result overflows in the positive direction, the predication register p0 is set to 1 and the true value is set for the condition that the addition result is positive without overflow. If so, set the predication register p1 to 1; if true for the condition that the addition result is 0, set 1 to the predication register p2; if true for the negative condition that the addition result does not overflow, then predication. This is an overflow detection addition operation in which the register p3 is set to 1 and the predication register p4 is set to 1 if true for the condition that the addition result overflows in the negative direction. The first slot of the instruction 2 is a subtraction operation for storing the subtraction result of the register R3 from the register R1 into the register R1 only when the predication register p0 is 1, and the second slot is used when the predication register p1 is 1. Is a transfer operation for transferring the register R1 to the register R2 only in the third slot.
This is an addition operation in which the addition result of the register R1 and the register R3 is stored in the register R1 only when the predication register p2 is 1. The first slot of instruction 3 is a register only when the predication register p3 is 1.
A division operation in which the result of dividing R1 by the register R3 is stored in the register R1, and the second slot is a multiplication in which the result of multiplication of the register R1 and the register R3 is stored in the register R1 only when the predication register p4 is 1. Operation. The first slot and the second slot of the instruction 1 and the third slot of the instruction 3 are each an operation which can be executed in parallel with each of the above operations in the same instruction (the operation becomes no if there is no significant operation). Yes, here we call it OP.
Predication is not performed in the OP operation. FIG. 5 shows the machine instruction program as a mnemonic, which is stored in the ROM 1 in binary. For example, in the third slot of instruction 1, the op field is 0101
(ADDV), dst field is 0001 (R1), sra field is 0010 (R2), srb / pd field is 0000 (p0), c field is 1, qp field is 1111 (always true). For one slot, the op field is 0100 (DIV), dst
The field is 0001 (R1), the sra field is 0011 (R3), s
The rb / pd field is 0001 (R1), the c field is 0, and the qp field is 0000 (p0).

Next, the operation of the processor when the machine instruction program of FIG. 5 is stored in the ROM 1 will be described in the order of timing called a machine cycle. (Timing 1) IF stage: Instruction 1 Instruction 1 is read from ROM1, and the first to third slots of instruction 1 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 2) DEC stage: Instruction 1 The first slot of instruction 1 stored in I1 latch 2 is the first
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the operation is an operation (corresponding to an OP operation). Some registers are read from the register file 8 as necessary based on the decoding. At the same time, I
The second slot of the instruction 1 stored in the second latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is also found that the operation is some sort of operation (corresponding to an OP operation). Some registers are read from the register file 8 as necessary based on the decoding. At the same time, the third slot of the instruction 1 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the operation is an ADDV operation. Based on this decoding, registers R1 and R2 are read from register file 8, and the read values are stored in D13 latches 14 and D23, respectively.
It is stored in the latch 17. IF stage: instruction 2 Instruction 2 is read from ROM1, and the first to third slots of instruction 2 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 3) EX stage: Instruction 1 Based on the result decoded by the first instruction decoder 5, the first operation unit 18 and the first state generation unit 21 perform desired operations. At the same time, based on the result decoded by the second command decoder 6, the second operation unit 19 and the second state generation unit 22 perform desired operations. At the same time, D1
The operation of adding the value of the register R1 stored in the third latch 14 and the value of the register R1 stored in the D23 latch 17 is performed in the third operation unit 20, and the addition result is stored in the register R1 of the register file 8. Is done. The third state generation unit 23 writes 1 to the predication register p0 of the predication unit 24 if the addition result overflows in the positive direction, and 0 otherwise.
If the addition result is positive without overflow, write 1 to the predication register p1, otherwise write 0, and if the addition result becomes 0, write the predication register p1.
Write 1 to p2, otherwise write 0. If the addition result does not overflow, write 1 to the predication register p3 if it becomes negative, otherwise write 0, and if the addition result overflows in the negative direction, write the predication register. Write 1 to p4, otherwise write 0. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the SUB operation is based on the evaluation of the predication register p0. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D11 latch 12 and the D21 latch 15, respectively. At the same time, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is determined that the operation is the MOV operation based on the evaluation of the predication register p1. Based on the decoding, the register R1 is read from the register file 8, and the read value is stored in the D22 latch 16. At the same time, the third slot of the instruction 2 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the ADD operation is based on the evaluation of the predication register p2. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D13 latch 14 and the D23 latch 17, respectively. IF stage: instruction 3 Instruction 3 is read from ROM1, and the first to third slots of instruction 2 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 4) • EX stage: Instruction 2 Based on the fact that the result decoded by the first instruction decoder 5 is a SUB operation based on the evaluation of the predication register p0, the value of the register R1 stored in the D11 latch 12 is calculated. A subtraction operation for reducing the value of the register R3 stored in the D21 latch 15 is performed in the first operation unit 18, and the operation result is stored in the register R1 of the register file 8. Since the c field is 0 and the pd field is invalid, the first state generation unit 21 does nothing. At the same time, the second
Based on the fact that the result decoded by the instruction decoder 6 is a MOV operation based on the evaluation of the predication register p1,
The transfer operation of the value of the register R1 stored in the D22 latch 16 is performed by the second operation unit 19, and the operation result is stored in the register R2 of the register file 8. Since the c field is 0 and the pd field is invalid, the second state generation unit 22 does nothing. At the same time, the third
Based on the fact that the result decoded by the instruction decoder 7 is an ADD operation based on the evaluation of the predication register p2,
The value 1 of the register R1 stored in the D13 latch 14 and D2
An addition operation is performed by the third operation unit 20 with the value of the register R3 stored in the 3-latch 17, and the operation result is stored in the register R4 of the register file 8. Since the c field is 0 and the pd field is invalid, the third state generation unit 23 does nothing. DEC stage: Instruction 3 The first slot of instruction 3 stored in I1 latch 2 is the first
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the operation is the DIV operation based on the evaluation of the predication register p3. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D11 latch 12 and the D21 latch 15, respectively. At the same time, the second slot of the instruction 3 stored in the I2 latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is determined that the MUL operation is based on the evaluation of the predication register p4. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D12 latch 13 and the D22 latch 1.
6 is stored. At the same time, the third slot of the instruction 3 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the operation is an operation (corresponding to an OP operation). Some registers are read from the register file 8 as needed based on the decoding. (Timing 5) EX stage: Instruction 3 Based on the fact that the result decoded by the first instruction decoder 5 is a DIV operation based on the evaluation of the predication register p3, the value of the register R1 stored in the D11 latch 12 is D
The first operation unit 18 performs a division operation of dividing by the value of the register R3 stored in the latch 21 and the operation result is stored in the register R1 of the register file 8. Since the c field is 0 and the pd field is invalid, the first state generation unit 21 does nothing. At the same time, the second
Based on the fact that the result decoded by the instruction decoder 6 is a MUL operation based on the evaluation of the predication register p4,
The value 1 of the register R1 stored in the D12 latch 13 and D2
The multiplication operation is performed by the second operation unit 19 with the value of the register R3 stored in the second latch 16 and the operation result is stored in the register R1 of the register file 8. Since the c field is 0 and the pd field is invalid, the second state generation unit 22 does nothing. At the same time, the third operation unit 20 and the third state generation unit 23 perform desired operations based on the result decoded by the third command decoder 7.

As described above, the processor of the present embodiment can execute the five-way branch and the processing immediately after the branch in three cycles of six slots, thereby achieving both execution efficiency and program efficiency. Note that the above-mentioned number of slots does not include the OP operation based on the processing other than the processing in the five-way branch and the processing immediately after the branch because it is not the main focus.

In the machine instruction program shown in FIG.
The operation is used to perform predication for all five conditions including the presence or absence of overflow. However, some of the five conditions may be used, and if the three conditions of positive / negative and zero including no overflow are sufficient, the ADD operation ( If the op field uses 0001), only three predication registers are required, and the usage efficiency of the predication registers is high.

(3) Third Machine Instruction Program FIG. 6 is a list of a third example of the machine instruction program. The first slot and the second slot of instruction 1 form one compare operation, and set the predication register p0 to 1 if true for one specified condition, that is, the condition that register R2 is greater than zero; This is a condition specifying comparison operation in which the predication register p1 is set to 1 if true for another specified condition, that is, the condition that the register R2 is equal to 0. The first slot of the instruction 2 is a subtraction operation for storing the subtraction result of the register R3 from the register R1 into the register R1 only when the predication register p0 is 1, and the second slot is
This is a transfer operation for transferring the register R1 to the register R2 only when the predication register p1 is 1. The third slot of instruction 1 and the third slot of instruction 2 are
Any operation that can be executed in parallel with each of the above operations in the same instruction (no operation if there is no significant operation)
Here, it is described as OP. Predication is not performed in the OP operation. FIG. 5 shows the machine instruction program as a mnemonic, which is stored in the ROM 1 in binary. For example, in the first slot and the second slot of the instruction 1, the op1 field is 1011 (CMPL), dst1
The field is 0010 (R2), the sra1 field is 0000 (R0),
srb / pd1 field is 0000 (p0), c1 field is 1, q
p1 field is 1111 (always true), dst2 field is 0010
The (gt) and sra2 fields are 0000 (eq), and the op2 field, srb / pd2 field, c2 field, and qp2 field can be anything.

Next, the operation of the processor when the machine instruction program of FIG. 6 is stored in the ROM 1 will be described in the order of timing called a machine cycle. (Timing 1) IF stage: Instruction 1 Instruction 1 is read from ROM1, and the first to third slots of instruction 1 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 2) DEC stage: Instruction 1 The first slot of instruction 1 stored in I1 latch 2 is the first
It is decoded by the instruction decoder 5. CMPL as decrypted result
It turns out to be an operation. Based on the decoding, registers R2 and R0 are read from register file 8, and the read values are stored in D11 latch 12 and D21 latch 15, respectively.
And stored in Further, based on this decoding, the decoding information (designating two conditions to be compared) in the second instruction decoder 6 is used together with the decoding information in the first instruction decoder 5, and thereafter the second slot is operated in the same manner as the no operation. Nothing is read from the register file 8 in particular. At the same time, the third slot of the instruction 1 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the operation is an operation (corresponding to an OP operation). Some registers are read from the register file 8 as needed based on the decoding. IF stage: instruction 2 Instruction 2 is read from ROM1, and the first to third slots of instruction 2 are stored in I1 latch 2 to I3 latch 4, respectively. (Timing 3) • EX stage: Instruction 1 The value of register R2 stored in D11 latch 12 and D21
An operation of comparing the value of the register R0 stored in the latch 15 with the value 0 is performed in the first operation unit 18, and the first state generating unit 21 performs the operation of comparing the value of the register R2 based on the information from the second instruction decoder 6. Is larger than the value of the register R0, 1 is written to the predication register p0 of the predication unit 24; otherwise, 0 is written. Based on the information from the second instruction decoder 6, the value of the register R2 is changed to the value of the register R0. Prediction register if equal
Write 1 to p1, otherwise write 0. At the same time, the third
The third operation unit 20 and the third state generation unit 23 perform a desired operation based on the result decoded by the command decoder 7. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the SUB operation is based on the evaluation of the predication register p0. Based on the decoding, the registers R1 and R3 are read from the register file 8, and the read values are stored in the D11 latch 12 and the D21 latch 15, respectively. At the same time, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 6. As a result of the decryption, it is determined that the operation is the MOV operation based on the evaluation of the predication register p1. Based on the decoding, the register R1 is read from the register file 8, and the read value is stored in the D22 latch 16. At the same time, the third slot of the instruction 2 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the operation is an operation (corresponding to an OP operation). Some registers are read from the register file 8 as needed based on the decoding. (Timing 4) • EX stage: Instruction 2 Based on the fact that the result decoded by the first instruction decoder 5 is a SUB operation based on the evaluation of the predication register p0, the value of the register R1 stored in the D11 latch 12 is calculated. A subtraction operation for reducing the value of the register R3 stored in the D21 latch 15 is performed in the first operation unit 18, and the operation result is stored in the register R1 of the register file 8. Since the c field is 0 and the pd field is invalid, the first state generation unit 21 does nothing. At the same time, the second
Based on the fact that the result decoded by the instruction decoder 6 is a MOV operation based on the evaluation of the predication register p1,
The transfer operation of the value of the register R1 stored in the D22 latch 16 is performed by the second operation unit 19, and the operation result is stored in the register R2 of the register file 8. Since the c field is 0 and the pd field is invalid, the second state generation unit 22 does nothing. At the same time, the third
The third operation unit 20 and the third state generation unit 23 perform a desired operation based on the result decoded by the command decoder 7.

As described above, in the processor of the present embodiment, any two conditions can be specified. Therefore, even if the two conditions are not exclusive conditions, the predication register necessary for performing predication based on those two conditions is not necessary. Only two are required, and the usage efficiency of the predication register is good.

As described above, with respect to the processor according to the present invention,
Although the description has been given based on the above embodiment, it goes without saying that the present invention is not limited to this embodiment. (1) In the above embodiment, the CMPL operation is limited to the first slot, and the two comparison conditions are specified using the dst field and the sra field of the second slot, but the op field and the srb / pd Three or more conditions may be specified using other unused fields such as fields, two comparison conditions may be specified in the third slot, or both slots may be used. Alternatively, more conditions may be designated, or the CMPL operation may be limited to the second slot and the comparison condition may be designated to the third slot. (2) In the above embodiment, the operation in which the predication condition can be arbitrarily specified is limited to the comparison operation. However, the instruction set is extended so that the predication condition can be arbitrarily specified in other arithmetic and logic operations. May be. (3) In the above embodiment, srb / p
Although the d field is switched between the second source operand and the predication destination operand, the d field may be switched according to the contents of the operation code (op field) without providing the c field. For example, taking advantage of the characteristic that the comparison operation does not need to be in the 3-operand format, the srb / pd field is used as a predication destination operand when the operation code is a comparison operation, and the second source operand is used when the operation is other than the above. A preferred embodiment for use as a device is conceivable.
In this way, one bit of the c field can be used for another function. For example, if the op field is extended by one bit, 16 more operations can be specified, which is very useful. (4) In the above embodiment, the instruction format shares the second source operand field and the predication destination operand field. However, the instruction format shares the destination operand field and the predication destination operand field. Is also good. In particular, since the comparison operation does not involve a destination operand, it is a preferred embodiment to use a field that is normally the destination operand as the predication destination operand field only for the comparison operation. (5) In the above embodiment, the srb / pd field is used to specify a predication register to be one predication destination operand, and for the second and subsequent predication registers used simultaneously, the specified predication register is used. Although the registers having the register numbers in ascending order are sequentially used starting from, the descending order may be used, or all the predication registers to be used may be explicitly specified by an instruction. By specifying explicitly, unnecessary use of predication registers can be avoided by, for example, duplicating dummy predication registers for unnecessary predication, and the predication register usage efficiency is improved. I do. (6) In the above embodiment, three instruction decoders and three operation units are provided to achieve three-parallel execution. However, two of these may be provided and two-parallel execution may be performed. Four of them may be provided and executed in parallel, or more may be provided. (7) The processor of the above embodiment employs the VLIW architecture, but may adopt a superscalar architecture. (8) The processor according to the above embodiment includes an instruction fetch,
Although a three-stage pipeline of decryption and execution is described, the number of stages of the pipeline may be any, and the pipeline need not be adopted.

[0047]

As is apparent from the above description, the processor according to the present invention can perform the predication relating to the multi-directional branch based on a single operation, so that both the execution efficiency and the program efficiency are compatible. Is particularly useful in the development of multimedia-related products, and greatly contributes to the advancement and development of the multimedia-related industry.

[Brief description of the drawings]

FIG. 1 is an instruction configuration diagram of a processor according to an embodiment.

FIG. 2 is a schematic configuration diagram of a processor according to the embodiment;

FIG. 3 is a flowchart of a processing example of a three-way branch;

FIG. 4 is a diagram showing a list of a first example of a machine instruction program of the processor according to the embodiment;

FIG. 5 is a view showing a list of a second example of the machine instruction program of the processor according to the embodiment;

FIG. 6 is a diagram showing a list of a third example of the machine instruction program of the processor according to the embodiment;

FIG. 7 is a diagram showing a list of examples of a machine instruction program of a processor according to the related art.

[Explanation of symbols]

 1 ROM 2 I1 latch 3 I2 latch 4 I3 latch 5 First instruction decoder 6 Second instruction decoder 7 Third instruction decoder 8 Register file 9 D1 selector 10 D2 selector 11 D3 selector 12 D11 latch 13 D12 latch 14 D13 latch Reference Signs List 15 D21 latch 16 D22 latch 17 D23 latch 18 First operation unit 19 Second operation unit 20 Third operation unit 21 First state generation unit 22 Second state generation unit 23 Third state generation unit 24 Predication unit

Claims (16)

[Claims] 1. A processor for performing at least predication under a first condition and predication under a second condition based on a single operation designation, wherein
And the second condition is not mutually exclusive. 2. A processor that performs at least predication under a first condition, predication under a second condition, and predication under a third condition based on a single operation designation, wherein Condition 1 and the second
2. The processor according to claim 1, wherein none of the second condition and the third condition are the same condition. 3. A processor for performing predication under a first condition, predication under a second condition, and predication under a third condition based on a single operation designation, wherein A total set is formed by three unions of the above condition, the second condition, and the third condition. 4. The operation specification relates to a comparison operation between a first operand and a second operand, wherein the first condition is a condition that the first operand is larger than the second operand, and the second condition is Is the first operand and the second
4. The processor of claim 3, wherein the condition is that the operands are equal, and the third condition is that the first operand is smaller than the second operand. 5. The operation specification is for an operation, the first condition is a condition that the operation result is positive, the second condition is a condition that the operation result is zero, and the third condition is a condition that the operation result is zero. 4. The processor according to claim 3, wherein the condition is that the operation result is negative. 6. The predication condition according to claim 1, wherein the operation designation relates to an arithmetic operation, and includes a condition that an arithmetic result overflows.
The processor according to any one of claims 1 to 3. 7. A predication under a first condition, a predication under a second condition, a predication under a third condition, and a predication under a fourth condition based on a single operation specification. A processor that performs predication under a fifth condition, wherein the first condition is a condition that the operation result overflows in a positive direction, and the second condition is a condition that the operation result is positive without overflow. The third condition is a condition that the operation result is zero, the fourth condition is a condition that the operation result is negative without overflow, and
The fifth condition is that the operation result overflows in the negative direction. 8. The processor according to claim 1, wherein both the first condition and the second condition are explicitly specified in an instruction. 9. The processor according to claim 8, wherein the designation of the first condition and the designation of the second condition are performed by expanding an area on an instruction for a normal operation designation. . 10. A processor that performs predication under at least one condition based on a single operation specification, wherein an area on an instruction for specifying an operand associated with the operation specification and whether the condition associated with the predication is satisfied A processor which shares an instruction area for designating a result storage destination. 11. The operation specification includes an instruction area for specifying three operands of a first source operand, a second source operand, and a destination operand, and includes an instruction area for specifying the second source operand. 11. The processor according to claim 10, wherein the area of the instruction is shared with an area on an instruction for specifying a storage destination of a result of success or failure of the condition accompanying the predication. 12. The operation specification includes an instruction area for specifying three operands of a first source operand, a second source operand, and a destination operand, and an instruction area for specifying the destination operand. 11. The processor according to claim 10, wherein an area and an area on an instruction for designating a storage destination of a result of the success or failure of the condition accompanying the predication are shared. 13. Whether the area on the instruction related to sharing is an area for specifying an operand or an area for specifying a storage destination of a condition success / failure result accompanying predication is determined.
11. The method according to claim 10, wherein the determination is made based on whether or not the operation specified by the operation specification is a comparison operation.
A processor according to any one of claims 1 to 12. 14. When the operation specified by the operation specification is a comparison operation, an area on the instruction related to the sharing is set as an area for specifying a storage destination of a condition success / failure result accompanying predication. 14. The processor according to claim 13, wherein: 15. A storage location of the result of the success or failure of the condition accompanying the predication under the first condition and a storage location of the result of the success or failure of the condition accompanying the predication under the second condition are both explicitly specified in an instruction. The processor of claim 1, wherein 16. The processor according to claim 1, wherein the processor is a long-word instruction format processor that specifies a plurality of operations in one instruction.