JP2001359057A - Data receiving device - Google Patents

Abstract

(57) [Problem] To provide a function of receiving composite serial data and reproducing a two-channel digital video signal without using an expensive signal processing device, and at the same time, complicating the circuit configuration and reducing power consumption. It can be fulfilled under the condition that the increase can be avoided. Kind Code: A1 A bit separation section for obtaining first and second reproduced serial data based on composite serial data from a receiving section, and first and second reproduced serial data and a first selection control signal are supplied. A 2: 1 multiplexer unit 22 for transmitting one of the first and second reproduced serial data in response to the first selection control signal; a first and a second reproduced serial data; and a second selection control. And a second signal
2: 1 multiplexer section 23 for transmitting the other of the first and second reproduced serial data in response to the selection control signal of
And detecting identification code data for one of the first and second reproduced digital video signals based on the first and second reproduced serial data, and outputting the first and second selection control signals as a result of the detection. And an identification code detection / control signal transmission unit 24 that transmits the signal as a signal corresponding to the identification code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The invention described in the claims of the present application is directed to parallel / digital conversion of two digital video signals having identification code data inserted in at least one of them.
Serial conversion (P / S conversion) is performed, and the first and second serial data obtained thereby are subjected to bit multiplexing / combining processing to receive composite serial data, and two serial data based on the composite serial data are received. And a digital video signal reproducing the digital video signal in a state independent of each other.

[0002]

2. Description of the Related Art In the field of transmission of digital data containing information data representing various kinds of signal information such as image information, the digital data is converted into serial data, an electric signal based on the serial data is obtained, and the signal is coaxial. A system for transmitting data through a transmission line formed using a cable or twisted pair line,
Alternatively, digital data is converted into serial data, and the serial data is converted into an optical signal, and the optical
A system for transmitting data through a transmission line formed using fibers has been put to practical use.

[0003] On the other hand, in the field of video signals, digitization of video signals has been attempted from the viewpoint of diversifying transmitted information and improving the quality of reproduced images in connection with the transmission. High-definition television (HDTV) systems and the like that handle digitized video signals have been proposed. Under the HDTV system, HDT systems have been proposed.
V digital video signals (HD signals) are handled. Also, standardized digital video signals for digital transmission of video signals have been proposed.
2: 2 component digital video signal (D1 signal). 4fsc composite digital video signal (D2
Signals) are known.

These HD signals, D1 signals, D2 signals, etc.
Represents, for example, a luminance signal component in a video signal.
A Y data sequence formed of 10-bit word string data,
10-bit word representing a color difference signal component in an image signal
P that is the data string data_B/ P _REach place with data series
Fixed part or 10-bit word string data
Y data series and P that is 10-bit word string data
_B/ P_RWord multiplexing is performed on the data sequence and
A predetermined part of the word multiplex data sequence
Reference code data (SAV: Start of Active Video and
And EAV: Endof Active Video)
It is assumed to be. SAV and EAV are word-synchronous data
Data role.

For example, a data sequence constituting an HD signal follows a data format as shown in FIG.

The data format of the HD signal shown in FIG. 8 includes a luminance signal data sequence (Y data sequence) representing a luminance signal component in a video signal as shown in FIG. each consists from the color difference signal data sequence representing the color difference signal components (P _B / P _R data sequence) in the video signal, the word data forming the respective Y data sequence and P _B / P _R data sequence as shown Has a 10-bit configuration. That is, each of the Y data sequence and P _B / P _R data sequence takes the form of 10-bit word sequence data. And, in FIG. 8A, Y
A line blanking period in a line period in the data sequence and a portion corresponding to a part of a video data period before and after the line blanking period are shown, and FIG. 8B shows P _B /
P portion corresponding portions of the _R line blanking period and the image data period in the preceding and succeeding the data series in the line period is shown.

In the Y data series, immediately before the portion corresponding to the video data period, four words (3FF (Y), 000 (Y), 000) each having a 10-bit configuration.
(Y), XYZ (Y); 3FF and 000 are fixed value information displayed in hexadecimal, XYZ is variable value information displayed in hexadecimal, and identifies a field, an identification of a field blanking period, and , Timing identification code data (SAV, EAV). (Y) is Y
Represents a word in the data series. ) Timing reference code data (SAV: Start of Ac)
tive Video), and immediately after the portion corresponding to the video data period, each has a 10-bit configuration.
Word (3FF (Y), 000 (Y), 000 (Y),
XYZ (Y)) is provided. Timing reference code data (EAV: End of Active Video) is provided. Similarly, even in the P _B / P _R data series, immediately before the portion corresponding to the video data period, four words each having a 10-bit configuration (3FF (C), 000 (C), 000).
(C), XYZ (C) ; (C) represents that the word in P _B / P _R data sequence. ), And immediately after the portion corresponding to the video data period, 4 words (3FF) each having a 10-bit configuration.
(C), 000 (C), 000 (C), XYZ (C))
Is arranged. Of course, E in the Y data series
Each of the AV and SAV, disposed in a portion corresponding to the line blanking period in the Y data sequence, also, P _B
/ P husband _R data EAV in series and SAV s is, P _B
/ Disposed in P _R data sequence portion corresponding to the line blanking period in.

[0008] For example, the data series constituting the D1 signal takes the form of 10-bit word string data and follows the data format as shown in FIG. 9 for example.

FIG. 9 shows a line blanking period in the line period of the D1 signal and a portion corresponding to a part of the video data period before and after the line blanking period. In such portion, just before the portion where the Y data sequence and the C _B / C _R data series corresponding to the video data period which is arranged in the word multiplex processing is performed, four words, each of which is a 10-bit configuration SAV, which is timing reference code data composed of (3FF, 00,000,000, XYZ), is provided, and immediately after the portion corresponding to the video data period, 4 words (3FF, 00) each having a 10-bit configuration are provided.
0,000, XYZ). 3FF and 000 are fixed value information displayed in hexadecimal, XYZ is variable value information displayed in hexadecimal, and indicates field identification, field blanking period identification, and SAV and EAV identification.

[0010] forms of such Y data sequence and P _B / P _R data sequence or C _B / C _R data series or,, Y data sequence and the P _B / P _R data sequence or C _B
In the case of a digital video signal in the form of a word multiplexed data sequence formed by performing word multiplexing processing on a / C _R data sequence, not only a single digital video signal but also a plurality of, for example, , Two (2
(Channel) digital video signal can be multiplexed and transmitted so that it can be reliably reproduced on the receiving side, so that the digital video signal can be used efficiently and the range of use of the digital video signal can be expanded. Will be done. And efficient use of digital video signals,
Alternatively, expansion of the use range of digital video signals, etc.
For example, it will result in further development of technology in the field of commercial or consumer electronics. Therefore, from such a viewpoint, with a means that can be prepared relatively easily,
There is a need for a method of multiplexing and transmitting two-channel digital video signals so that they can be reliably reproduced on the receiving side.

Therefore, the applicant of the present application has previously filed Japanese Patent Application No.
No. 0-141846, a digital video signal such as a two-channel HD signal is inserted with identification code data in at least one of them, and then subjected to P / S conversion for each of the two. Serial data, and a bit multiplexing / synthesis process is performed on the obtained two serial data to form composite serial data.
A data transmission method for transmitting the composite serial data to transmit the data and a data transmission device for implementing the method have been proposed.

In the data transmission method or the data transmission device proposed above, the two-channel digital video signal is divided into at least one of the P / S signals with the identification code data inserted therein. The conversion is performed, and furthermore, the two serial data obtained are subjected to bit multiplexing / combining processing to form composite serial data, and the composite serial data is transmitted for transmission. Therefore, the transmitted composite serial data includes a part where the identification code data inserted into at least one of the original two-channel digital video signals is converted into serial data.

Therefore, on the receiving side receiving the transmitted composite serial data, the composite serial data received as including the part where the identification code data is converted into the serial data is subjected to bit separation processing and serial /
The identification code data can be detected in any of the two-channel digital video signals obtained by performing the parallel conversion (S / P conversion) processing. The digital video signal of the channel can be properly reproduced and derived.

That is, for example, with respect to a digital video signal such as an HD signal or a D1 signal, for example, the two channels are multiplexed so that the two channels can be reliably reproduced on the receiving side by means that can be prepared relatively easily. Can be transmitted.

[0015]

On the receiving side receiving the composite serial data transmitted in this way, the composite serial data is subjected to bit separation processing, S / P conversion processing, and the like to obtain a plurality of, for example, two channels. In reproducing a digital video signal, in a bit separation unit that performs a bit separation process of decomposing composite serial data into two serial data, a portion where identification code data of the two serial data is converted into serial data It is necessary to perform reset timing control on the bit separation unit in order to always obtain at the predetermined output terminal. Otherwise, S is assigned to each of the two serial data obtained from the bit separation unit.
A bus switch to which a two-channel digital video signal obtained by performing the / P conversion process is supplied, and the one into which the identification code data of the two-channel digital video signal is inserted is always output to a predetermined output terminal. In order to be derived, for example, it is necessary to perform switching control of a bus switch according to the presence or absence of identification code data in a digital video signal obtained from one of the S / P converters.

However, as described above, when performing the reset timing control for the bit separation unit, the reset pulse signal supplied to the bit separation unit is
The control is performed with the timing of one clock cycle for the composite serial data. Specifically, for example, the phase of the reset pulse signal supplied to the bit separation unit is set to be equal to one cycle of the clock signal whose frequency is 2.97 GHz. It needs to be changed. Such phase control for the reset pulse signal is an extremely high-speed signal processing, and a signal processing device capable of performing such high-speed signal processing is generally extremely expensive. Therefore, there is a problem that the circuit components including the bit separation unit and its surroundings are expensive.

As described above, a bus switch is provided for supplying a two-channel digital video signal obtained by performing S / P conversion processing on each of two serial data obtained from the bit separation unit. In performing the switching control, the provision of the bus switch significantly complicates the circuit configuration of the digital video signal processing portion, and further causes a problem of increasing power consumption.

In view of the above, according to the invention described in the claims of the present application, P / S conversion is performed on each of the two-channel digital video signals in which identification code data is inserted into at least one of them, and Are formed by performing a bit multiplexing / combining process on the two serial data obtained by
Receiving the composite serial data sent to be transmitted,
The composite serial data undergoes bit separation processing and S / P conversion processing to reproduce a 2-channel digital video signal, eliminating the need for expensive signal processing devices capable of high-speed signal processing. In addition, a data receiving apparatus is provided that can achieve the required functions while avoiding the complexity of the circuit configuration of the digital video signal processing portion and the increase in power consumption.

[0019]

According to a first aspect of the present invention, there is provided a data receiving apparatus in which identification code data is inserted in at least one of the first and second aspects. A P / S converter for each of the digital video signals, and a receiving unit for receiving composite serial data formed by subjecting the first and second serial data obtained by bit multiplexing / combining, to reception; A bit separation unit that performs a bit separation process on the composite serial data received by the unit to obtain first and second reproduced serial data; a first and a second reproduced serial data obtained from the bit separation unit; And a first 2: 1 transmitting one of the first and second reproduced serial data in response to the first selection control signal.
A multiplexer unit, first and second reproduced serial data obtained from a bit separation unit, and a second selection control signal are supplied, and the first and second reproduced serial data of the first and second reproduced serial data are supplied according to the second selection control signal. Second 2: sending the other out:
A first S / P for obtaining a first reproduced digital video signal by performing S / P conversion on reproduced serial data transmitted from a 1 multiplexer unit and a first 2: 1 multiplexer unit;
A conversion unit, a second S / P conversion unit that performs S / P conversion on the reproduced serial data sent from the second 2: 1 multiplexer unit to obtain a second reproduced digital video signal, For the first reproduced digital video signal obtained from the S / P converter or the second reproduced digital video signal obtained from the second S / P converter, the presence or absence of inserted identification code data is detected. An identification code detection / control signal transmission unit for transmitting the first and second selection control signals as a signal corresponding to the detection result.

Each of the first and second 2: 1 multiplexer units basically has at least a pair of input terminals, one output terminal, and one control terminal, and is supplied to the control terminal. According to the state of the control signal, it functions to derive one of the two input data supplied to the pair of input terminals to the output terminal. Therefore, depending on the control signal supplied to the control terminal, output data in which two input data supplied to a pair of input terminals are multiplexed in a time division manner at the output terminal is obtained.

In the data receiving apparatus according to any one of the first to sixth aspects of the present invention as described above, the composite serial data received by the receiving unit is First and second reproduced serial data obtained by performing the bit separation process by the bit separation unit are supplied to the first and second 2: 1 multiplexer units, respectively. One of the first and second reproduced serial data is transmitted from the first 2: 1 multiplexer unit in response to the first selection control signal, and the second 2: 1 multiplexer unit outputs , And the other of the first and second reproduced serial data is transmitted in response to the second selection control signal. Further, one of the first and second reproduced serial data derived from the first 2: 1 multiplexer section undergoes S / P conversion by the first S / P conversion section, and the first reproduced digital A video signal, and a first signal derived from a second 2: 1 multiplexer unit.
And the other of the second reproduced serial data is the second S
After undergoing S / P conversion by the / P conversion unit, it is converted into a second reproduced digital video signal. Then, the identification code detection / control signal transmission unit detects the presence or absence of identification code data inserted in the first or second reproduced digital video signal, and outputs the first and second selection control signals as a result. Is transmitted as a signal corresponding to.

With this configuration, the first and second 2: 1 multiplexer units are configured to receive the first and second selection control signals, and obtain the first and second selection control signals from the first S / P conversion unit.
Is set to a state in which the reproduced digital video signal of (1) is accompanied by identification code data, or a state in which the second reproduced digital video signal obtained from the second S / P converter is accompanied by identification code data. As a result, the first and second reproduced digital video signals are obtained by properly reproducing the original digital video signals of two channels multiplexed and transmitted in the form of composite serial data received by the receiver. In addition, the bit separation unit that performs bit separation processing on the composite serial data received by the receiving unit operates in a so-called free-run state without performing reset timing control, so that high-speed signal processing is possible. This eliminates the need for expensive signal processing devices, and eliminates the need to provide a bus switch to which two-channel digital video signals are supplied.

Therefore, the data receiving apparatus according to any one of claims 1 to 6 in the claims of the present application provides a data receiving apparatus having at least one of two channels in which identification code data is inserted, for example, , HD signal,
Each of the digital video signals, such as the D1 signal, has a P /
The S serial conversion is performed, and the resulting two serial data are subjected to bit multiplexing / combining processing to form and receive the composite serial data transmitted to be transmitted. A function of reproducing a 2-channel digital video signal by performing a P / P conversion process or the like does not require the use of an expensive signal processing device capable of high-speed signal processing. This can be achieved while avoiding a complicated configuration and an increase in power consumption.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 5 shows the transmission of composite serial data received by an example of the data receiving apparatus according to any one of the first to sixth aspects of the present invention. 1 shows an example of a data transmission device.

In the example of the data transmission apparatus shown in FIG. 5, two-channel digital video signals DHD1 and DHD2 are used, and one of the two digital video signals DHD1 is used as a channel identification code (CH identification code).
The digital video signal DHD2 on the other side is supplied to the P / S converter 12 while being supplied to the insertion unit 11. 2-channel digital video signal DHD
1 and DHD2 Each of the, for example, the as shown in A and B in FIG. 8, each of 10-bit word sequence data Y data sequence and P _B / P _R data sequence to form the HD signal, SAV and It is assumed that the EAV forms 20-bit word string data formed by superimposing words in a synchronized state. Each of the digital video signals DHD1 and DHD2 is parallel data whose word transmission rate is, for example, 74.25 MBps.

The CH identification code insertion unit 11 has a horizontal synchronization pulse signal SH for the digital video signal DHD1.
Is also supplied. In the CH identification code insertion section 11, the digital video signal DHD1 is supplied to the data selection / extraction section 13. The data selection / extraction section 13 supplies the word transmission rate of 74.25 Mbps from the CH identification code data transmission section 14. CH identification code data DCI
Is also supplied. The CH identification code data DCI is configured by connecting a plurality of 10-bit word data having a preset code.

In the CH identification code insertion section 11, the horizontal synchronizing pulse signal SH is supplied to the control signal forming section 15. The control signal forming unit 15 forms a control signal CWS and a control signal CDS synchronized with the horizontal synchronizing pulse signal SH, and sends the control signal CWS to the CH identification code data transmitting unit 1.
4 and a control signal CDS to the data selection / extraction unit 13.

Accordingly, the CH identification code data transmitting section 14 transmits the CH identification code data DCI in response to the control signal CWS, and supplies it to the data selection / extraction section 13. When the control signal CDS is supplied to the data selection / extraction section 13, the CH identification code data DC from the CH identification code data transmission section 14 is correspondingly supplied.
I and one of a 10-bit word-structured Y data sequence and a 10-bit word-structured P _B / P _R data sequence constituting the digital video signal DHD1, for example, a 10-bit word-structured P _B / P _R data sequence , And at other times, the digital video signal DHD1 is directly extracted, and data is selectively extracted. Thereby, the data selection / extraction section 13 outputs the digital video signal DH
Against D1, 10-bit word structure of the Y data sequence and the 10-bit word structure of the P _B / P _R 10-bit word configuration of the line blanking during line period portion in the Y data sequence of the data sequence constituting the same In the period portion, a process of inserting the CH identification code data DCI from the CH identification code data transmission unit 14 is performed according to the control signal CDS.

The digital video signal DHD1 in the data selection / extraction section 13 includes the CH identification code data DCI
As shown in FIG. 6, in a specific example of the processing for inserting a line ID, the CH identification code data DCI is converted into a Y data sequence constituting the digital video signal DHD1 by a line blanking during a line period portion thereof. It is inserted so as to be arranged immediately before the SAV, which is timing reference code data, as a series of the auxiliary data timing reference code data ANC following the EAV, which is the timing reference code data, and the horizontal synchronization data group DHS, which are arranged in the period portion. , Auxiliary data timing reference code data ANC
Is formed as a part of the auxiliary data including. Therefore, the CH identification code data DCI is inserted as auxiliary data in the line blanking period portion of the line period portion of the digital video signal DHD1.

The timing at which the CH identification code data DCI is inserted as a part of the auxiliary data into the Y data sequence forming the digital video signal DHD1 is set by the control signal CWS and the control signal CDS. As a result, from the data selection and extraction unit 13,
CH during line blanking period during line period
A digital video signal D including a Y data sequence in which identification code data DCI is inserted as auxiliary data
HD1 is derived as 20-bit word string data DZ1 (20) having a word transmission rate of 74.25 MBps.

At this time, the CH identification code data transmitting section 1
The word transmission rate sent from 4 is 74.25 MB.
One specific example of the CH identification code data DCI to be set to ps is the same 10-bit word data 010h (h represents hexadecimal notation, and the same applies hereinafter).
Have a 32-word configuration formed by a series of 32 words.

The Y constituting the digital video signal DHD1 into which such CH identification code data DCI is inserted.
10-bit word string data DY1 formed by the data series
In (10), the part where the CH identification code data DCI is inserted is as shown in FIG. In FIG. 7, DD10 represents 10-bit word data forming a horizontal synchronization data group DHS or SAV which is timing reference code data. Auxiliary data timing reference code data ANC which forms auxiliary data together with CH identification code data DCI formed of 32 consecutive 10-bit word data 010h includes six 10-bit word data 000h, 3FCh, 3FCh, and TT.
T, MMM and LLL are successively formed. TT
T is a data identification word, MMM and LLL
Is a word representing either the line number or the number of data words. Arrow t represents the elapsed time.

A word transmission rate of 74.25 MBps, which is formed in the data selection and extraction unit 13,
The 20-bit word string data DZ1 (20) including the H identification code data DCI is transmitted from the CH identification code insertion unit 11 and supplied to the P / S conversion unit 16.

The P / S converter 16 performs a P / S conversion on the 20-bit word string data DZ1 (20) to convert parallel data into serial data, based on the 20-bit word string data DZ1 (20). Obtains serial data DS1 having a bit transmission rate of 74.25 × 20 = 1.485 Gbps, and obtains the serial data DS1.
Is supplied to the bit multiplexing unit 17.

On the other hand, in the P / S converter 12 to which the digital video signal DHD2 is supplied, the digital video signal DHD2 forming the 20-bit word string data is converted into a P / S signal.
After performing the conversion, based on the digital video signal DHD2,
The bit transmission rate is 74.25 × 20 = 1.485 Gb
The serial data DS2 having the value of ps is obtained, and the serial data DS2 is supplied to the bit multiplexing unit 17. In the bit multiplexing unit 17, the frequency is 1.485 × 2 = 2.97 GHz
Is also supplied.

In the bit multiplexing section 17, one bit is sent from each of the serial data DS1 from the P / S conversion section 16 and the serial data DS2 from the P / S conversion section 12 in accordance with the clock pulse signal CA. The operation of taking out the data alternately is performed, and the serial data DS1 and the serial data DS2
Is subjected to a bit multiplexing / combining process to obtain a composite serial data DS having a bit transmission rate of 2.97 Gbps.
Form M. Thus, the composite serial data DSM obtained from the bit multiplexing unit 17 is supplied to the transmission unit 18.

The transmitting section 18 is a composite serial data DSM
For example, in order to transmit through a data transmission line formed using a coaxial cable or an optical fiber, an electric signal suitable for a data transmission line formed using a coaxial cable, or an optical fiber is used. The signal is converted into a transmission signal SM which is an optical signal suitable for the data transmission path formed and transmitted. Thus, transmission of the composite serial data DSM is performed.

In the example of the data transmission apparatus shown in FIG. 5 as described above, the transmitting unit 18 converts the composite serial data DSM having a bit transmission rate of 2.97 Gbps into
The transmission signal SM is converted into a transmission signal SM suitable for a data transmission path formed by using a coaxial cable or an optical fiber. Therefore, such a transmission unit 18 can be configured by effectively utilizing a commercially available integrated circuit (IC) element, which is not specially developed. Accordingly, with the digital video signal is an HD signal in the form of a Y data sequence and P _B / P _R data sequence, a means that can adjust relatively easily,
The plurality can be multiplexed and transmitted so as to be surely reproduced on the receiving side.

FIG. 1 shows an example of a data receiving apparatus according to any one of the first to sixth aspects of the present invention. One example of the data receiving apparatus is to receive the transmission signal SM representing the composite serial data DSM transmitted by the transmitting unit 18 in the data transmitting apparatus shown in FIG.

In the example of the data receiving apparatus shown in FIG. 1, for example, an electric signal suitable for a data transmission path formed by using a coaxial cable or an optical fiber formed by using an optical fiber is used. A receiving unit 2 for receiving a transmission signal SM which is an optical signal suitable for a data transmission path;
0 is provided.

Since the receiving section 20 receives the transmission signal SM representing the composite serial data DSM transmitted by the transmission section 18 in the data transmitting apparatus shown in FIG. 5, the composite serial data DSM is substantially transmitted. Will receive it. Then, the receiving unit 2 that has received the transmission signal SM
0 is a composite serial data DS having a bit transmission rate of 2.97 Gbps based on the received transmission signal SM.
M is reproduced and supplied to the bit separation unit 21.

The receiving unit 20 detects the clock of the reproduced composite serial data DSM, reproduces a clock pulse signal CA having a frequency of 2.97 GHz from the composite serial data DSM, and outputs the clock pulse signal CA. Is supplied to the bit separation unit 21.

The bit separation section 21 is constituted by, for example, a 1: 2 demultiplexer. The 1: 2 demultiplexer basically has at least one input terminal, a pair of output terminals, and one clock terminal. When input serial data is supplied to the input terminal, the 1: 2 demultiplexer receives the input serial data. In accordance with the clock pulse signal supplied to the clock terminal after the bit synchronization, the input serial data is distributed to a pair of output terminals for each bit, whereby each bit is transmitted to a pair of output terminals. It has a function of deriving each of two output serial data whose rate is 1/2 of the bit transmission rate of the input serial data.

The bit separation unit 21 sequentially extracts one bit from the composite serial data DSM received by the reception unit 20 using a clock pulse signal CA having a frequency of 2.97 GHz, and One of
An operation of forming every other bit group is performed, and a bit separation process is performed on the composite serial data DSM. As a result, in the bit separation unit 21, every other bit of the composite serial data DSM is sequentially formed, and the bit transmission rate is 2.97 / 2 = 1.485 Gb.
ps, and every other bit of the composite serial data DSM are sequentially connected, and the bit transmission rate is 2.97 / 2 = 1.485.
Gbps, and the serial data DS1 is obtained at one of a pair of output terminals of the bit separation unit 21 and the serial data DS2 is obtained at the other, or a pair of outputs of the bit separation unit 21. In this state, serial data DS2 is obtained at one end and serial data DS1 is obtained at the other end.

The serial data DS1 and DS
No. 2 means that any one of them has a portion in which the CH identification code data DCI inserted on the transmitting side for transmitting the composite serial data DSM as the transmission signal SM is converted into serial data. here,
The serial data DS1 is the CH identification code data DCI
Is accompanied by a portion that has been converted into serial data.

Then, the serial data DS1 or DS2 obtained at one of the pair of output terminals in the bit separation section 21 is converted into a pair of 2: 1 multiplexer sections 22 and 23.
And the serial data DS2 obtained at the other of the pair of output terminals of the bit separation unit 21.
Alternatively, DS1 is a pair of 2: 1 multiplexer units 22
And 23 respectively. The 2: 1 multiplexer unit 22 is also supplied with the selection control signal SSA from the identification code detection / control signal transmission unit 24, and the 2: 1 multiplexer unit 23 is supplied with the identification code detection / control signal transmission unit 2
4 is also supplied.

Each of the 2: 1 multiplexer sections 22 and 23 basically has at least one pair of input terminals (a) and (b) and one output terminal (Q) as shown in FIG. And one control terminal (s), and two input data Da supplied to a pair of input terminals (a) and (b) according to the state of the control signal SS supplied to the control terminal (s). And Db at the output terminal (Q) as output data DQ. Therefore, depending on the control signal SS supplied to the control terminal (s), the two input data Da and Db supplied to the pair of input terminals (a) and (b) are time-divisionally input to the output terminal (Q). Is obtained as output data DQ multiplexed.

In such a case, the control signal SS selectively takes, for example, a high level H and a low level L, whereby the control signal SS changes to a high level H as shown in FIG. When the control signal SS takes the low level L, the output data DQ supplied to the input terminal (a) is obtained as the output data DQ.
As Q, input data Db supplied to the input terminal (b) is obtained.

In the 2: 1 multiplexer section 22,
Depending on the state of the selection control signal SSA, the bit separation unit 21
, One of the serial data DS1 and DS2 is selectively derived. For example, when the serial data DS1 is selectively derived, the state is maintained by the selection control signal SSA, and when the serial data DS2 is selectively derived. By the selection control signal SSA, the state where the serial data DS2 is selectively derived is switched to the state where the serial data DS1 is selectively derived. On the other hand, in the 2: 1 multiplexer section 23, the other of the serial data DS1 and DS2 from the bit separation section 21 is selectively derived according to the state of the selection control signal SSB. For example, the serial data DS2 is selected. When the serial data DS1 is derived, the state is maintained by the selection control signal SSB. When the serial data DS1 is selectively derived, the serial data DS2 is changed from the state in which the serial data DS1 is selectively derived by the selection control signal SSB.
Is switched to a state in which is derived.

The serial data DS1 (or serial data DS2) whose bit transmission rate obtained from the 2: 1 multiplexer section 22 is 1.485 Gbps is represented by S
/ P conversion section 25, and the bit transmission rate obtained from the 2: 1 multiplexer section 23 together with 1.
The serial data DS2 (or serial data DS1) at 485 Gbps is supplied to the S / P converter 26.

The S / P converter 25 converts the serial data DS1 (or the serial data DS2) into an S / P
The conversion is performed to convert the serial data DS1 (or serial data DS2) into 20-bit word string data. As a result, the S / P conversion unit 25 outputs a signal based on the serial data DS1 (or the serial data DS2).
Word transmission rate of 1,485 / 20 = 74.25 MB
A reproduced digital video signal DHD1 '(or a reproduced digital video signal DHD2') forming 20-bit word string data of ps is obtained. Then, the reproduced digital video signal DHD1 ′ forming the 20-bit word string data obtained based on the serial data DS1 is represented by C
H identification code data DCI is formed.

Similarly, in the S / P converter 26, the serial data DS2 (or serial data DS1)
Is subjected to S / P conversion to convert serial data DS2 (or serial data DS1) into 20-bit word string data. As a result, the S / P converter 26 sets the word transmission rate based on the serial data DS2 (or the serial data DS1) to 1,485 / 20 = 74.
A reproduced digital video signal DHD2 '(or a reproduced digital video signal DHD1') forming 20-bit word string data of 25 MBps is obtained.

The reproduced digital video signal DHD1 '(or the reproduced digital video signal DHD2') obtained from the S / P converter 25 is supplied to the identification code detection / control signal transmitting unit 24. Identification code detection / control signal transmission unit 2
In 4, with respect to the reproduced digital video signal DHD 1 ′ (or the reproduced digital video signal DHD 2 ′) from the S / P converter 25, the CH identification code data DCI inserted therein is detected. In such detection, the S / P converter 25 outputs the reproduced digital video signal DH
D1 'is obtained and supplied to the identification code detection / control signal transmitting section 24, whereupon the CH identification code data DC
I is detected, and the reproduced digital video signal DHD2 'is obtained from the S / P conversion unit 25 and supplied to the identification code detection / control signal transmission unit 24, where the CH identification code data DCI is detected. Will not be.

The identification code detection / control signal transmission unit 2
4 is supplied to the 2: 1 multiplexer section 22 by the selection control signal SS.
A, and supplies the selection control signal SSB to the 2: 1 multiplexer section 23.
High level H is applied to one of the SA and the selection control signal SSB.
And let the other take a low level L.

Then, the identification code detection / control signal transmission section 24 outputs the reproduced digital video signal DHD1 '(or the reproduced digital video signal DHD) from the S / P conversion section 25.
When the CH identification code data DCI is detected as a result of the detection of the CH identification code data DCI for 2 ′),
That is, the reproduced digital video signal D is output from the S / P converter 25.
When HD1 'is obtained, the selection control signal SSA supplied to the 2: 1 multiplexer section 22 maintains the level at that time, for example, the high level H or the low level L, and the 2: 1 multiplexer Part 23
Is also supplied to the selection control signal SSB at that level:
For example, the low level L or the high level H is maintained. Thereby, the 2: 1 multiplexer unit 22
The state in which the serial data DS1 is derived is maintained, and the state in which the serial data DS2 is derived is maintained in the 2: 1 multiplexer unit 23. As a result, S / P
The state where the reproduced digital video signal DHD1 ′ is obtained from the conversion unit 25 and the reproduced digital video signal DHD2 ′ is obtained from the S / P conversion unit 26 is maintained.

The identification code detection / control signal transmission unit 2
4 is the reproduced digital video signal DHD1 '(or the reproduced digital video signal DHD) from the S / P converter 25.
As a result of the detection of the CH identification code data DCI for 2 ′), when the CH identification code data DCI is not detected, that is, when the reproduced digital video signal DHD2 ′ is obtained from the S / P converter 25, 2: 1 The selection control signal SSA supplied to the multiplexer unit 22 is changed at that time, for example, a high level H or a low level L, and takes a low level L or a high level H, for example. The current level of the selection control signal SSB supplied to the section 23, for example, the low level L or the high level H is changed, and for example, the high level H or the low level L is taken.
As a result, the serial data DS1 is changed from the state in which the serial data DS2 is derived to the 2: 1 multiplexer unit 22.
Is switched to a state in which the serial data DS1 is derived, and the state in which the serial data DS1 is derived is maintained.
The multiplexer section 23 switches from a state in which the serial data DS1 is derived to a state in which the serial data DS2 is derived, and maintains the state in which the serial data DS2 is derived.

By performing such a control operation by the identification code detection / control signal transmission section 24, the reproduced digital video signal DHD1 'is obtained from the S / P conversion section 25 and the reproduced digital video signal DHD1' is transmitted from the S / P conversion section 26. The state in which the video signal DHD2 'is obtained is a stable state, and S /
As soon as the reproduction digital video signal DHD2 'is obtained from the P conversion unit 25 and the reproduction digital video signal DHD1' is obtained from the S / P conversion unit 26, the reproduction digital video signal is output from the S / P conversion unit 25. The state is switched to a state in which the signal DHD1 'is obtained and the reproduced digital video signal DHD2' is obtained from the S / P converter 26.

In the identification code detection / control signal transmitting section 24 in the example of the receiving apparatus shown in FIG. 1, the control operation as described above is performed by using a built-in microcomputer, for example. The operation is performed by the formed operation control unit in accordance with the flowchart shown in FIG.

In the control operation according to the flowchart shown in FIG.
The count value Cv of the counter is reset to 0, and in the following step 32, the CH identification code data of the reproduced digital video signal DHD1 ′ (or the reproduced digital video signal DHD2 ′) from the S / P conversion unit 25 is detected, and CH It is determined whether or not the identification code data DCI has been detected. As a result, when the CH identification code data DCI is detected, it is determined in step 33 whether or not the count value Cv of the counter is 0.

If the result of determination in step 33 is that the count value Cv of the counter is 0, the flow returns to step 32, and
If the count value Cv of the counter is not 0, step 3
In step 4, the count value Cv of the counter is reduced by 1, and the process returns to step 32.

Also, as a result of the determination in step 32, CH
If the identification code data DCI is not detected, the count value Cv of the counter is increased by 1 in step 35, and the count value Cv of the counter is incremented in step 36.
It is determined whether or not v has reached a predetermined set value N. As a result, if the count value Cv of the counter has not reached the set value N, the process returns to step 32 and the count value C
If v has reached the set value N, in step 37, the level of the selection control signal SSA is changed from the high level H to the low level L, or from the low level L to the high level H, and the selection control signal SSB is changed. Is changed from the low level L to the high level H or from the high level H to the low level L, and then the process returns to the step 31.

In the above description, identification code detection and
The control signal transmission unit 24 is assumed to perform CH identification code data detection on the reproduced digital video signal DHD1 ′ (or reproduced digital video signal DHD2 ′) from the S / P conversion unit 25. The control signal transmitting unit 24 may be configured to detect the CH identification code data of the reproduced digital video signal DHD2 ′ (or the reproduced digital video signal DHD1 ′) from the S / P conversion unit 26. However, in such a case, when the CH identification code data is not detected as a result of the CH identification code data detection, the identification code detection / control signal transmitting unit 24 sets the level of each of the selection control signals SSA and SSB at that time. And the CH identification code data DCI
Is detected, the respective levels of the selection control signals SSA and SSB are changed.

Further, in the above description, the bit separation unit 2
1, the serial data DS1 and the serial data DS2 are converted from the CH identification code data DC.
Since I is accompanied by a portion converted to serial data, the S / P converter 25 (or the S / P converter 26)
The digital video signal DHD1 'forming the 20-bit word string data obtained from the bit separation unit 21 is formed with the CH identification code data DCI. To the CH identification code data D
If the CI includes a portion converted to serial data, the S / P converter 26 (or the S / P converter 25)
The reproduced digital video signal DHD2 'forming the 20-bit word string data obtained from the above is formed with the CH identification code data DCI.

In the example of the data receiving apparatus shown in FIG. 1 as described above, the bit separation section 21 that performs bit separation processing on the composite serial data DSM obtained from the reception section 20 performs reset timing control. Without
It operates in a so-called free-run state. Therefore, the bit separation unit 21 can be configured without using expensive signal processing devices capable of high-speed signal processing. In addition, there is no need to provide a bus switch to which the two-channel reproduced digital video signals DHD1 ′ and DHD2 ′ are supplied. Therefore, in the example of the data receiving device shown in FIG.
The use of expensive signal processing devices capable of high-speed signal processing is unnecessary, and the reproduced digital video signal D
It is possible to avoid the complexity of the circuit configuration of the part for processing HD1 'and DHD2' and increase in power consumption.

[0065]

As is apparent from the above description, in the data receiving apparatus according to any one of the first to sixth aspects of the present invention, the first and second data receiving apparatuses are provided. 2: 1: 1 multiplexer unit, in response to the first and second selection control signals, the first reproduced digital video signal obtained from the first S / P conversion unit is accompanied by identification code data Or the second S / P
A state is set in which the second reproduced digital video signal obtained from the conversion unit accompanies identification code data. As a result, the first and second reproduced digital video signals are obtained by properly reproducing the original digital video signals of two channels multiplexed and transmitted in the form of composite serial data received by the receiver. In addition, the bit separation unit that performs bit separation processing on the composite serial data received by the receiving unit operates in a so-called free-run state without performing reset timing control, so that high-speed signal processing is possible. This eliminates the need for expensive signal processing devices, and eliminates the need to provide a bus switch to which two-channel digital video signals are supplied.

Therefore, according to the data receiving apparatus according to any one of the first to sixth aspects of the present invention, the two-channel data having the identification code data inserted into at least one of the two channels is provided. , For example, HD
A digital video signal, which is a signal, a D1 signal, etc., is subjected to P / S conversion, and the resulting two serial data are subjected to bit multiplexing and synthesis processing to form
Receiving the composite serial data sent to be transmitted,
The function of performing bit separation processing, S / P conversion processing, and the like on the composite serial data to reproduce a two-channel digital video signal eliminates the need for expensive signal processing devices capable of high-speed signal processing. In addition, this is achieved while avoiding a complicated circuit configuration of the digital video signal processing portion and an increase in power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a data receiving apparatus according to any one of claims 1 to 6 of the present application.

FIG. 2: 2: 1 used in the example shown in FIG. 1
It is a conceptual diagram used for description of a multiplexer part.

FIG. 3: 2: 1 used in the example shown in FIG. 1
It is a table | surface figure used for description of a multiplexer part.

FIG. 4 shows an example of identification code detection and detection in the example shown in FIG.
6 is a flowchart provided for describing the operation of a control signal transmission unit.

FIG. 5 is a block diagram showing an example of a data transmission device for transmitting composite serial data received by the example shown in FIG. 1;

FIG. 6 is a time chart for explaining an example of the data transmission apparatus shown in FIG. 5;

FIG. 7 is a time chart for explaining an example of the data transmission apparatus shown in FIG. 5;

FIG. 8 is a conceptual diagram provided for describing an example of a data format of a digital video signal.

FIG. 9 is a conceptual diagram illustrating an example of a data format of a digital video signal.

[Explanation of symbols]

20: receiving unit, 21: bit separating unit, 2
2, 23 ... 2: 1 multiplexer section, 24 ...
Identification code detection / control signal transmission unit, 25, 26 ...
S / P converter

Continued on the front page F term (reference) 5C025 AA30 BA01 BA14 BA20 BA22 CB05 5C063 AA06 AB03 AB05 AB11 AC01 CA23 CA36 5K028 AA07 EE03 KK03 KK16 MM08 MM17 NN05 SS16

Claims (6)

[Claims] 1. A parallel / serial conversion is performed on each of two digital video signals having identification code data inserted in at least one of them, and a bit is added to the first and second serial data obtained by the parallel / serial conversion. A receiving unit that receives composite serial data formed by performing the multiplexing and combining process; and a bit separation unit that performs a bit separation process on the composite serial data received by the receiving unit to obtain first and second reproduced serial data. And first and second reproduced serial data obtained from the bit separation unit and a first selection control signal.
A first 2: 1 multiplexer for transmitting one of the first and second reproduced serial data in response to the selection control signal of the first and second, and first and second reproduced serial data obtained from the bit separation unit. And a second selection control signal, and a second 2: 1 multiplexer section for transmitting the other of the first and second reproduced serial data according to the second selection control signal; A first serial / parallel converter for performing serial / parallel conversion on the reproduced serial data sent from the first 2: 1 multiplexer to obtain a first reproduced digital video signal; A second serial / parallel converter for performing serial / parallel conversion on the reproduced serial data sent from the multiplexer unit to obtain a second reproduced digital video signal; 1 obtained from the serial / parallel converter
The presence / absence of the inserted identification code data is detected for the reproduced digital video signal of the second or the second reproduced digital video signal obtained from the second serial / parallel converter, and the first and second selection control signals are detected. Is transmitted as a signal corresponding to the result of the above detection.
And a control signal transmission unit. 2. An identification code detecting / control signal transmitting section comprising:
And the second selection control signal, the first and second 2: 1
2. The data receiving apparatus according to claim 1, wherein said multiplexer section causes said first reproduced digital video signal obtained from said first serial / parallel conversion section to be in a state accompanied by identification code data. 3. The first serial / parallel conversion section includes a first serial / parallel conversion section.
3. The data receiving apparatus according to claim 2, wherein the reproduced digital video signal is obtained by inserting identification code data into a line blanking period portion. 4. An identification code detecting / control signal transmitting section comprising:
And the second selection control signal, the first and second 2: 1
2. The data receiving apparatus according to claim 1, wherein said multiplexer section causes said second reproduced digital video signal obtained from said second serial / parallel conversion section to take a state in which said second reproduced digital video signal accompanies identification code data. 5. A second serial / parallel converter, comprising:
5. The data receiving apparatus according to claim 4, wherein the reproduced digital video signal is obtained by inserting identification code data into a line blanking period portion. 6. An identification code detection / control signal transmission section comprising:
And the second selection control signal is selectively set to a low level and a high level, and the first selection control signal is set to a high level and a low level. When switching from one of a state taking a level and a state taking a low level to the other, the first 2:
The one multiplexer switches from a state in which one of the first and second reproduced serial data is transmitted to a state in which the other is transmitted, and switches the state in which the second selection control signal takes the low level and the high level. When switching from one of the states to the other, the second 2: 1 multiplexer switches from a state of transmitting the other of the first and second reproduced serial data to a state of transmitting one of the first and second reproduced serial data. The data receiving device according to claim 1, wherein: