JP2001358339A - Semiconductor device having insulated gate bipolar transistor - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device provided with an insulated gate bipolar transistor having a high latch-up resistance and operating at a low on-voltage in a normal state. A IGBT100 of the present embodiment is a composite IGBT connected in parallel and a second IGBT2 of pnp type with the first IGBT1 high threshold voltage _{V TH2} of the pnp type with a low threshold voltage _{V TH1.} Second IGBT2
Threshold voltage V is the threshold voltage _{V TH 2} of the first IGBT1
It is set higher on the order of 1 V than _TH1 . I
Since the threshold voltage of the GBT 100 matches the threshold voltage of the first IGBT, the ON voltage does not increase. When the load is short-circuited, the current value of the saturation collector current is lower than that of the first IGBT 1, so that the load short-circuit tolerance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an insulated gate bipolar transistor (IGBT).

[0002]

2. Description of the Related Art As a switching semiconductor device having a large current capacity and a low saturation voltage (low on-voltage), an insulated gate bipolar transistor (IGBT) also known as a conductivity modulation type transistor is known. Conventionally, as shown in FIG. 16, the semiconductor structure of this pnp type IGBT is composed of ap ⁺ type collector layer (minority carrier injection layer) 2 having a collector electrode 1 connected to the back surface, and a A stacked n ⁺ -type buffer layer 3, an n ⁻ -type conductivity modulation layer (n base) 4 formed by epitaxial growth on the buffer layer 3, and a gate insulating film on the surface of the conductivity modulation layer 4. And a p-type emitter layer (p) formed in a well shape on the surface of the conductivity modulation layer 4 by a self-alignment method using the gate electrode 6 as a mask. Base) 7
And a well-shaped n ⁺ formed by using an aluminum emitter electrode 8 formed on the emitter layer 7.
Source layer 9.

In such an IGBT having a vertical DMOS structure, when a positive potential is applied to the gate electrode 6 with respect to the emitter electrode 8, the p-type as a channel diffusion layer (back gate) immediately below the gate electrode 6 is formed. An n-channel of an inversion layer is formed on the surface of the emitter layer 7 through which electrons (the majority carriers of the n ⁻ -type conductivity modulation layer 4) are transmitted from the emitter electrode 8 and the source layer 9 through the channel. Is injected into. In response, holes (n
^- for type minority carriers in the conductivity modulation layer 4) is injected into the conductivity modulation layer 4, the electric conductivity of the conductivity modulation layer 4 is rapidly increased, pnp Totanjisuta turns on and a large current flows Low on-voltage (low collector-emitter voltage).

Meanwhile, in the load short-circuit or the like, diffusion resistance beneath portions of the source layer 9 hole current I _H is increasing rapidly flowing through the beneath portion of the source layer 9 to the emitter electrode 8 of the emitter layer 7 (p When the base resistance) voltage drop across r _B increases, p-type pn junction between the emitter layer 7 and the n ⁺ -type source layer 9 of will be forward biased, the parasitic transistor (n ^- -type conductivity modulation layer 4, Latch-up of an npn-type transistor including a p-type emitter layer 7 and an n ⁺ -type source layer 9 is likely to occur. Therefore, the breakdown strength (latch-up strength) of a load short circuit is low.

Here, in order to improve the latch-up resistance, the current amplification factor h of the parasitic npn-type transistor is increased.
It is effective to lower _FE . For that purpose, it is necessary to reduce the impurity concentration of the p-type emitter layer 7 or the impurity concentration of the n ⁺ -type source layer 9. In the former case, it is inconvenient becomes rather higher diffusion resistance r _B of the emitter layer 7. In the latter case, the contact resistance between the source layer 9 and the emitter electrode 8 increases as it is.

Therefore, a structure shown in FIG. 17 has been proposed as a structure for increasing the latch-up withstand capability when a load is short-circuited. First, the IGBT structure shown in FIG.
The emitter electrode 8 is not in direct contact with the stripe-shaped source layer 9 running in the gate width (channel width) direction of the gate electrode 6, but rather in a plurality of branch portions 9 a extending from the source layer 9 in a comb shape. emitter electrode 8 is in contact conductive, diffusion resistance r _S is parasitic in the constricted portion of each branch portion 9a.

As described above, the source layer 9 and the emitter electrode 8
Spreading the resistance r _S is equivalently interposed the IGBT semiconductor structure, hole current I _H flowing in the emitter electrode 8 through the beneath portion of the source layer 9 of the emitter layer 7, such as during load short-circuit surge between the Therefore, even if the voltage drop of the diffusion resistance r _B increases, the electron current I flowing through the source layer 9 at the same time
_{Since E} also increases sharply and the voltage drop of the diffusion resistor r _S also increases, the pn junction of the emitter layer 7 and the source layer 9 is less likely to be forward-biased due to antagonism of the voltage drop of both diffusion resistors. In addition, the latch-up of the parasitic npn transistor is less likely to occur. For this reason, the breakdown strength of a load short circuit increases.

On the other hand, in the IGBT structure shown in FIG. 17B, a plurality of island-shaped source layers 9b are discretely formed in the direction of the gate width (channel width) of the gate electrode 6 so as to straddle these. It has a structure in which an emitter electrode 8 is formed,
It is called a partial channel structure. In this partial channel type structure, there is no conduction with the emitter electrode 8 only in the portion between the source layers 9b with respect to the channel immediately below the gate electrode 6, and as a result, similar to the structure of FIG.
Diffusion resistance r _S between source layer 9b and emitter electrode 8
Is parasitic. Even in such a structure, the resistance to breakdown of a load short circuit is improved by antagonizing the voltage drop of the diffusion resistance.

[0009]

However, FIG.
The IGBT structure shown in FIGS. 1A and 1B has the following problems.

That is, attention is paid only to an overvoltage period such as a load short circuit.
Then, the diffusion resistance r of the source layer 9 is obtained._S Voltage drop due to
It is effective to increase the latch-up tolerance by increasing
However, in a normal ON state (non-overvoltage period), the diffusion resistance r
_SThe electron current flows through and the voltage drop continues
Naturally, the ON voltage (saturated collector voltage)
V_{CE (sat)}And the ON loss increases
Great.

[0011] In view of the above problems, an object of the present invention is to improve the semiconductor structure or electrical characteristics,
It is an object of the present invention to provide a semiconductor device having an insulated gate bipolar transistor having a high latch-up resistance and operating at a low on-voltage in a normal state.

[0012]

Means for Solving the Problems To solve the above problems, circuit means of the present invention include a first IGBT of a first conductivity type, which is current-controlled by a gate voltage, and a first I IGBT.
A second IGBT of the first conductivity type, which is connected in parallel to the GBT and is current-controlled by the gate voltage, as a monolithic, and has a threshold voltage V of the second IGBT;
_{It is characterized in that TH2} is set higher than the threshold voltage V _TH1 of the first IGBT on the order of 1V.
Since the threshold voltage of this composite IGBT matches the low threshold voltage of the first IGBT, there is no problem in the normal on / off operation, and the on-voltage does not increase. In addition, when the load is short-circuited, the current value of the saturation collector current is lower than that of the first IGBT 1, so that the load short-circuit withstand capability is improved.

Further, the present invention can adopt an embodiment in which the ON resistance of the first IGBT is set higher than the ON resistance of the second IGBT. Since the transconductance of IGBT1 is smaller than that of IGBT2, the composite IGBT can suppress the overcurrent at the time of load short-circuit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a sectional view showing an IGBT semiconductor structure according to a first embodiment of the present invention.

The IGBT semiconductor structure of the present embodiment is of a pnp type, and has a p ⁺ -type collector layer (minority carrier injection layer) 2 having a collector electrode 1 connected to the back surface, and a collector layer 2.
N ⁺ -type buffer layer 3 stacked on the buffer layer 3, and n ⁻ formed on the buffer layer 3 by epitaxial growth.
Conductivity modulation layer (n base) 4, p ⁺ -type deep well-shaped main emitter region (p base) 7 a formed on the surface of conductivity modulation layer 4, and surface of conductivity modulation layer 4 A gate electrode 6 made of polysilicon formed with a gate insulating film 5 interposed therebetween, a p-type circumscribed emitter region 7b adjacent to the outside of the shallow portion on the surface side of the well end of the main emitter layer 7a, and a circumscribed emitter region 7b A shallow n-type source region 9A formed on the surface of the substrate, an n ⁺ -type source contact region 9B formed on the surface of the main emitter layer 7a so as to be connected to the n-type source region 9A, An emitter electrode 8 made of aluminum is in ohmic contact with both the region 9B and the main emitter region 7a.

That is, the IGBT structure of this embodiment is different from the conventional IGBT structure shown in FIG. 16 in that the conventional n ⁺ -type source layer 9 is replaced by a limited-scale source region 9A and an emitter electrode 9A. 8 in that it is divided into a high-concentration source contact region 9B which makes ohmic contact with the source contact region 9B.

[0017] In this embodiment, not the source layer 9A is n ⁺ -type, because that is it from the low-concentration n-type, easily parasitic transistor latch-up in the load short-circuit or the like (n ^- -type conductivity modulation layer 4, p-type circumscribed emitter layer 7b, the current amplification factor _{h FE} of the npn-type transistors) consisting of n-type source region 9A is lower than the conventional structure shown in FIG. 16. For this reason, the latch-up withstand capability is improved, and the breakdown withstand capability when the load is short-circuited is increased. N-type source region 9A
Since the n ⁺ -type source contact region 9B is additionally connected, the contact resistance does not increase, a low on-voltage can be maintained, and the turn-on speed does not decrease.

Further, in this embodiment, the emitter layer 7 is a p-type circumscribed emitter region 7 constituting a channel diffusion layer of the MOS portion.
b and the p ⁺ -type main emitter region 7a, so that the threshold voltage of the MOS portion does not change,
By increasing the concentration of the main emitter region 7a, the diffusion resistance (p-base resistance) r directly below the source / contact layer 9B is increased.
The value of _B has decreased. Therefore, the voltage drop across the diffusion resistance r _B by Hall current I _H of the short circuited load is reduced, the forward biasing of the pn junction between the circumscribed emitter region 9b and the source region 9A can be suppressed, it becomes latch-up difficult to occur, prior , The latch-up resistance is improved.

Next, a method of manufacturing the IGBT semiconductor structure according to the first embodiment will be described.

First, as shown in FIG. 2A, a semiconductor substrate 10 having an n ⁺ -type buffer layer 3 laminated on a p ⁺ -type collector layer 2 is prepared. Next, an n ⁻ type conductivity modulation layer (n base) 4 is formed on the n ⁺ type buffer layer 3 by epitaxial growth. Next, an initial oxidation process is performed to cover the surface of the n ⁻ type conductivity modulation layer 4 with the thick silicon oxide film 11.

Next, as shown in FIG. 2B, an opening 11a for forming the main emitter region 7a in the silicon oxide film 11 is formed by photolithography. Thereafter, boron ions B ⁺ are implanted to dope the acceptor.

Next, as shown in FIG. 2C, drive-in is performed to diffuse and form a well-shaped p ⁺ -type main emitter region 7a. Then, an oxidation process is performed to cover the opening 11a with the thick silicon oxide film 11b.

Next, as shown in FIG. 2D, the central portion of the silicon oxide film 11b on the main emitter region 7a is left as an implantation mask 11c by photolithography.

Next, as shown in FIG. 2 (e), after performing a gate oxidation process to form a gate insulating film 5, a polysilicon film is formed between the adjacent main emitter regions 7a by photolithography. The gate electrode 6 is formed.

Next, as shown in FIG.
Using oxide film 11c and gate electrode 6 as a mask
Boron ion B⁺Ion implantation
(Channel doping) and dope the acceptor
I do. Thereafter, a channel drive is performed and p⁺Lord of
A p-type region is diffused into a shallow portion at the well end of the emitter region 7a.
The circumscribed emitter region 7
b is formed. Note that p ⁺Type main emitter region 7a
Since the p-type region overlaps the shallow part of the well end, the main emitter region
7a has an inscribed emitter region 7c⁺⁺High concentration area close to mold
Area.

Next, as shown in FIG. 3B, a phosphorus or arsenic donor is implanted at a high concentration by self-alignment using the silicon oxide film 11c and the gate electrode 6 as a mask, and the main emitter region 7a and the A shallow n-type source layer 9 'is formed on the surface of the circumscribed emitter region 7b. As a result, an n-type source region 9A is formed on the surface layer of the circumscribed emitter region 7b, while ap ⁺ type region 9B 'is formed on the surface layer of the inscribed emitter region 7c of the main emitter region 7a.

Next, as shown in FIG. 3C, a phosphor glass (PSG) layer 12 as an interlayer insulating film and a contact hole 8a for the emitter electrode 8 are formed on the gate insulating film 6 by photolithography. Contact hole 8a is opened just above p ⁺ type region 9B '. Thereafter, using the phosphorus glass layer 12 and the silicon oxide film 11c as a mask, a donor of phosphorus or arsenic is ion-implanted again at a high concentration and introduced into the contact hole 8a to increase the concentration of the region inside the n-type source region 9A to n. ⁺ Type source contact layer 9B
To form Immediately below the phosphor glass layer 12 is an n-type source region 9A.
Will remain.

Next, after the silicon oxide film 11c is removed by etching, an emitter electrode 8 made of aluminum is formed as shown in FIG. Note that the collector electrode 1 on the back surface is also formed.

As described above, the manufacturing method of the IGBT structure of this embodiment is different from the conventional process in that the phosphor glass layer 12 of the interlayer insulating film is formed.
Only by adding a step of doping an n-type impurity into the contact hole 8a before the formation of the emitter electrode 8 by using
A high concentration source contact region 9B can be obtained without increasing the concentration of the source region 9A. Moreover, in this method, higher concentrations of p ⁺ -type outside the p ⁺ -type main emitter region 7a Can be obtained, and the reduction of the p-base resistance r _B becomes more remarkable.

FIG. 4 is an enlarged perspective view showing an IGBT semiconductor structure according to a second embodiment of the present invention.
FIG. 5 is a graph showing the relationship between the surface position and the surface concentration in a cross section cut along the line AA 'in FIG.

As in the first embodiment, the IGBT semiconductor structure of the present embodiment is formed so that the circumscribed emitter region 7b adjacent to the outside of the surface of the main emitter region 7a and the surface of the circumscribed emitter region 7b are shallow. It has an n-type source region 9A and an n ⁺ -type source contact region 9B formed shallowly on the surface of the inscribed emitter region 7c. And n
Type source region 9A and n ⁺ type source contact region 9
A comb-shaped bulging portion 7d of the p ⁺ -type main emitter region 7a penetrates to the connection interface with B to the surface. Therefore, the diffusion resistance r _S is parasitic at the narrow portion of the n-type source region 9A sandwiched between the bulging portions 7d. Since the n-type source region 9A is formed in the entire width direction immediately below the gate insulating film 6, when a positive potential is applied to the gate electrode 6, the n-type source region 9A becomes a full width channel immediately below the gate insulating film 6, and the channel resistance is reduced in the first embodiment. It is not different from that of the form.

[0032] In such a structure, even when the potential of the circumscribed emitter region 7b by a voltage drop due to the hole current in the base resistors r _B to the overcurrent in the load short-circuiting is increased, at the same time, the voltage drop across the diffusion resistance r _S by electron current Since the voltage of the n-type source layer 9A rises as compared with the voltage of the emitter electrode 8, the pn junction between the n-type source region 9A and the p-type circumscribed emitter region 7b is further reduced as compared with the first embodiment. Bias is less likely to occur, and the latch-up resistance can be increased. However, non-overcurrent phase (normal state on) the diffusion resistance r _S is to join the on-resistance slightly higher on-resistance than the first embodiment.

Next, a method of manufacturing the IGBT semiconductor structure according to the second embodiment will be described.

First, similarly to the manufacturing method of the first embodiment, as shown in FIG. 2A, a semiconductor substrate 1 in which an n ⁺ -type buffer layer 3 is laminated on a p ⁺ -type collector layer 2.
0 is prepared, and an n ⁻ -type conductivity modulation layer (n base) 4 is formed on the n ⁺ -type buffer layer 3 by epitaxial growth. Then, an initial oxidation treatment is performed, and n ⁻
The surface of the conductivity modulation layer 4 is covered with a thick silicon oxide film 11.

Next, as shown in FIG. 6A, a mask 11 having an opening 11d for forming the main emitter region 7a in the silicon oxide film 11 by photolithography.
forming e. The opening 11d has a rectangular wave-shaped opening edge. Then, boron ions B ⁺ are implanted to dope the acceptor. Drive in,
A well-shaped p ⁺ type main emitter region 7a is formed by diffusion. Since the edge of the mask 11e has a rectangular waveform, the well end of the main emitter region 7a also has a rectangular waveform. Then, an oxidation process is performed to cover the opening 11d with a thick silicon oxide film.

Next, as shown in FIG. 6B, a silicon oxide film is left as a mask 11c for implantation in a central portion above the main emitter region 7a by photolithography.
Then, after the gate insulating film 5 is formed by performing a gate oxidation process, a polysilicon gate electrode 6 is formed on the adjacent main emitter layer 7a by photolithography.

Next, as shown in FIG.
Using oxide film 11c and gate electrode 6 as a mask
Boron ion B⁺Ion implantation
(Channel doping) and dope the acceptor
I do. Thereafter, a channel drive is performed and p⁺Type
A p-type region is diffused into a shallow portion at the well end of the main emitter layer 7a.
The circumscribed emitter region 7
b is formed. Note that p ⁺Of the main emitter region 7a
Since the p-type region overlaps the shallow end of the well, the main emitter region 7
The inscribed emitter region 7c of a⁺⁺High concentration area close to mold
Becomes

Next, as shown in FIG.
Using oxide film 11c and gate electrode 6 as a mask
Foreline allows high concentration of phosphorus or arsenic donors
The main emitter region 7a and the circumscribed emitter region 7b are implanted.
A shallow n-type source region 9 'is formed on the surface layer of FIG. This
The n-type source region 9 is provided on the surface layer of the circumscribed emitter region 7b.
A is formed, but the inscribed emitter of the main emitter region 7a is formed.
The surface of the region 7c has p ⁺A mold region 9B 'is formed.

Next, as shown in FIG. 7B, a phosphor glass (PSG) layer 12 as an interlayer insulating film and a contact hole 8a for the emitter electrode 8 are formed on the gate insulating film 6 by photolithography. Contact hole 8a opens just above p ⁺ -type region layer 9B '. The opening end of the phosphor glass layer 12 is set at a position that alternately crosses the rectangular wave-shaped pn junction surface. Thereafter, using the phosphorus glass layer 12 and the silicon oxide film 11c as a mask, a donor of phosphorus or arsenic is ion-implanted again at a high concentration and introduced into the contact hole 8a, and the region inside the n-type source layer 9 is increased in concentration to n. ⁺
The source contact region 9B of the mold is formed. Immediately below the phosphor glass layer 12, the n-type source region 9A remains. Next, after the silicon oxide film 11c is removed by etching, an emitter electrode 8 made of aluminum is formed as shown in FIG.
In addition, as shown in FIG. 1, a collector electrode 1 on the back surface is also formed.

[Third Embodiment] FIG. 8A is a circuit diagram showing a circuit configuration of an IGBT according to a third embodiment of the present invention, and FIG. 8B is a diagram showing the relationship between the emitter-gate voltage of the IGBT. 4 is a graph showing a relationship between a saturation collector current.

The IGBT 100 of this embodiment has a low threshold voltage V
_This is a composite IGBT in which a pnp first IGBT1 having _TH1 and a pnp second IGBT2 having a high threshold voltage V _TH2 are connected in parallel. The threshold voltage V _TH2 of the second IGBT 2 is equal to the threshold voltage V _TH of the first IGBT 1.
It is set higher than _TH1 . Here, setting the threshold voltage high means that the error of the threshold voltage due to the normal process is within ± 0.3 V, but is much larger than this error range and there is a difference of 1 V order. I do. For example, the low threshold voltage V _TH1 is set to 4V, and the high threshold voltage V _TH2 is set to 8V.

In this example, the element size of the first IGBT 1
The size of the second element is substantially the same. Therefore, this example
Emitter-gate voltage V of the composite IGBT 100 of FIG._GE
Collector current I for_CIs shown in FIG.
The low threshold voltage V_TH1 Characteristics of the first IGBT1
(Dashed line) and high threshold voltage V_TH2Second IGB
It is an intermediate characteristic (solid line) with the characteristic of T2 (broken line).

Normally, in an IC in which only the first IGBT 1 having a low threshold voltage V _TH1 (4 V) is formed, a gate voltage V considerably higher than the threshold voltage V _TH1 is used.
_{Since GE} (for example, 15 V) is applied to the gate, when a load is short-circuited and applied between the emitter and the collector at about the power supply voltage V _CC , an overcurrent flows through the first IGBT 1 and breaks down. On the other hand, in the IC in which only the second IGBT 2 having the high threshold voltage V _TH2 (8 V) is formed, the margin between the threshold voltage V _TH2 and the gate voltage of the normal ON operation is small, so that the ON voltage (saturated collector voltage) Is high, and is not suitable for the switching operation.

However, the composite IGBT 100 of the present embodiment
Since the threshold voltage matches the low threshold voltage V _TH1 , the first IGBT 1
As described above, there is no problem, and the ON voltage does not increase. Further, when the load is shorted than the first IGBT1 the current value of the saturation collector current I _C decreases, load short-circuit withstand capability is improved.

FIG. 9 is a sectional view showing a first semiconductor structure for realizing the composite IGBT 100 of FIG. This semiconductor structure includes a well-shaped p-type thin emitter layer 17a formed on the surface of the n ⁻ type conductivity modulation layer (n base) 4 and a well formed on the surface of the conductivity modulation layer 4 And a heavily doped emitter layer 17b. Since the surface concentration of the emitter layer 17a is lower than the surface concentration of the emitter layer 17b, the portion including the emitter layer 17a constitutes the IGBT 1 having the low threshold voltage V _TH1 , and the portion including the emitter layer 17b includes the high threshold voltage V _TH1.
This constitutes the IGBT 2 of _TH2 . The threshold voltage of the IGBT is different for each p-type well.

FIG. 10 shows the composite IGBT 100 of FIG.
FIG. 4 is a cross-sectional view showing a second semiconductor structure for realizing the above. In this semiconductor structure, a region A in one half of the emitter layer 17 of a single p-type well is formed with a low concentration of p-type, and a region B in the other half is formed with a high concentration of p-type. . The portion including the region A is the IGBT1 having the low threshold voltage V _TH1 .
The portion including the emitter layer 17B constitutes the IGBT 2 having a high threshold voltage V _TH2 .

FIG. 11 shows the composite IGBT 100 of FIG.
FIG. 13 is a cross-sectional view showing a third semiconductor structure for realizing the above. This semiconductor structure has an n ⁻ type conductivity modulation layer (n base) 4.
Has an emitter layer 17 in the form of a plane stripe of a p-type well formed on the surface of the p-type well. The emitter layer 17 has a p-type lightly doped region 17A and a p-type darkly doped region 17B.
Are alternately arranged. The portion including the region 17A of the p-type and light concentration has a low threshold voltage V _TH1 of I
GBT1 constitute a portion including a thick region 17B in the p-type constitute a IGBT2 of high threshold voltage _{V TH2.}

FIG. 12A is a sectional view showing another semiconductor structure for realizing the composite IGBT 100, and FIG. 12B is a graph showing the relationship between the emitter-gate voltage and the saturation collector current in the semiconductor structure. This semiconductor structure includes a well-type p-type lightly doped emitter layer 17 formed on the surface of an n ⁻ -type conductivity modulation layer (n-base) 4.
a, and a well-shaped p formed on the surface of the conductivity modulation layer 4.
Has an emitter layer 17b of the highly concentrated in the mold, the channel length _{L a} of the emitter layer 17a is an emitter layer 17b
It is formed longer than the channel length L _b of the inner. Since the surface concentration of the emitter layer 17a is lower than the surface concentration of the emitter layer 17b, a portion including the emitter layer 17a constitutes the IGBT 1 having a low threshold voltage V _TH1 , and a portion including the emitter layer 17b includes a high threshold voltage V _TH2. IG
BT2 is formed, but the channel length L of IGBT1 is
Since _a is longer than the channel length of IGBT2 _{L b,}
The ON resistance of IGBT1 is larger than that of IGBT2. Therefore, as shown in FIG. 12 (b), the transconductance (g = ΔI _C / ΔV _GE ) of the IGBT 1 is equal to the IGB.
Since it is smaller than that of T2, the composite IGBT 100 of the present example can suppress an overcurrent at the time of load short-circuit, as compared with the semiconductor structure shown in FIGS.

[Fourth Embodiment] FIG. 13 shows a fourth embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a semiconductor structure of an IGBT according to the embodiment. The semiconductor structure of this example has a conductivity modulation layer (n base).
4 is a p-type emitter layer (p
Base) 7, a polysilicon gate electrode 6 and a second gate electrode 16 formed via a gate insulating film 5.
And n ⁺ -type source layers 19 and n ⁺ formed in a well shape on the surface of emitter layer (p base) 7 by a self-alignment method using gate electrodes 6 and 16 as masks.
Type source contact layer 29 and n ⁺ type source
An emitter electrode 18 made of aluminum is in ohmic contact with both the contact layer and the emitter layer 7. The second gate electrode 16 has a source layer 19 and a source
The source layer 19 is formed so as to extend over the contact layer 29, and the source / contact layer 29 constitutes a switch lateral MOSFET 20 functioning as a source.

The gate electrode 6 and the second gate electrode 16
When a positive potential is applied and the IGBT turns on, the switch
Since the horizontal MOSFET 20 is on,
Style I _EIs the n-channel of the switch lateral MOSFET 20
Flow through When a load short circuit occurs, the switch horizontal MO
The SFET 20 operates in the saturation region (non-linear region),
The current is the electron current I_EWill be limited,
Current is difficult to flow. This is due to the high channel resistance
And the potential of the source layer 19 is
18, the source layer 19 and the emitter layer 7
Junction is hardly forward-biased and latch-up withstand capability
Is high.

When the IGBT is off, the switch horizontal MOS
Since the n-channel of the FET 20 has disappeared and the conduction of the source layer 19 to the contact layer 29 has been cut off, the source layer 19 is in a floating state. By the way, in the conventional IGBT DMOS structure shown in FIG. 16, when the potential of the gate electrode 8 drops below the threshold voltage at the time of turn-off, the electron current sharply decreases due to the disappearance of the DMOS channel, and the emitter-collector voltage decreases. During the rapid rise, the pn junction between the source layer 19 and the emitter layer 7 may be forward-biased due to the rise of the hole current component, causing latch-up. However, in this example, at the time of turn-off, the source layer 19 is not grounded and is in a floating state, so that even if the pn junction is forward-biased, latch-up does not occur.

FIG. 14A shows the implementation of the semiconductor structure of FIG.
FIG. 14 (b) is a plan view of FIG.
FIG. 14 is a sectional view taken along the line AA ′ in FIG.
FIG. 14C is cut along the line BB ′ in FIG.
It is a cutting arrow view. n⁺Type source layer 19
A portion corresponding to the channel width inserted just below the edge of the gate electrode 6
19a, and a narrow portion 19b that partially protrudes therefrom.
Become. n⁺Type source contact layer 29 has a narrow portion
Inserted just below the emitter electrode 18 in accordance with 19b
It is a narrow part, and the narrow part 19b and the source contact
The narrow second gate electrode 16 is straddled over the gate layer 29.
Is disgusted. Therefore, the switch lateral MOSFET 20
Channel resistance r_cNot only the narrow portion 19b
Dispersion resistance r_s Are also parasitic. Improves load short-circuit tolerance
You.

FIG. 15A shows a plane pattern of a structure obtained by improving the structure shown in FIG. 14, and FIG.
FIG. 15A is a sectional view taken along the line AA ′ in FIG. 15A, and FIG. 15C is a sectional view taken along the line BB ′ in FIG. In Figure 14, by providing the second gate electrode 16, and the distance is long between the emitter electrode 18 for collecting the source layer 19 and the hole current I _H of the injection source of electron current I _E, the hole The diffusion resistance r _{B in} the path of the current I _H increases. Therefore, it is necessary to still reduce the diffusion resistance r _B. Therefore, in the semiconductor structure of the present embodiment, is provided with a second emitter electrode 28 for collecting only hole current I _H. Therefore, the first emitter electrode 18 serves as an injection source for the electron current _IE only. The second emitter electrode 28 is provided between the narrow portions 19b of the source layer 19. Further, the second gate electrode 26 is formed in a band shape, and the n ⁺ -type source contact layer 39 is also formed in a band shape accordingly. Since the second emitter electrode 28 adjacent to the source layer 19 is formed, and shortened path length of the hole current I _H of the emitter layer within 7, since the drops diffusion resistance r _B, load short-circuit withstand capability further improves.

In each of the above embodiments, a pnp type IG
Although a BT has been described, an npn-type IGBT can be easily obtained by reversing the conductivity type.

[0055]

As described above, the present invention has the following effects. In the present invention, the composite IGBT has a threshold voltage of the first IG.
Since the threshold voltage of the BT matches the low threshold voltage, there is no problem in the normal on / off operation, and the on-voltage does not increase. In addition, when the load is short-circuited, the current value of the saturation collector current is lower than that of the first IGBT 1, so that the load short-circuit withstand capability is improved. In a configuration in which the on-resistance of the first IGBT is set higher than the on-resistance of the second IGBT, the transconductance of IGBT1 is smaller than that of IGBT2, so that the composite IGBT suppresses overcurrent at the time of load short-circuit. be able to.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an IGBT semiconductor structure according to a first embodiment of the present invention.

FIGS. 2A to 2E are process cross-sectional views for explaining each process of the manufacturing method according to the first embodiment.

FIGS. 3A to 3D are process cross-sectional views for explaining each process of the manufacturing method of the first embodiment following the process of FIG. 2;

FIG. 4 is an enlarged perspective view showing an IGBT semiconductor structure according to a second embodiment of the present invention.

FIG. 5 is a graph showing a relationship between a surface concentration and a surface position in a cross section cut along the line AA ′ in FIG. 4;

FIGS. 6A to 6C are cross-sectional perspective views illustrating each step of the manufacturing method according to the second embodiment.

FIGS. 7 (a) and 7 (b) are process cross-sectional perspective views for explaining each process of the manufacturing method of the second embodiment following the process of FIG.

FIG. 8A is an IGB according to a third embodiment of the present invention.
FIG. 4B is a circuit diagram showing a circuit configuration of T, and FIG. 4B is a graph showing the relationship between the emitter-gate voltage and the saturation collector current of the IGBT.

FIG. 9 is a cross-sectional view showing a first semiconductor structure for realizing the composite IGBT of FIG.

FIG. 10 is a sectional view showing a second semiconductor structure for realizing the composite IGBT of FIG.

FIG. 11 is a sectional view showing a third semiconductor structure for realizing the composite IGBT of FIG.

12A is a cross-sectional view showing another semiconductor structure for realizing a composite IGBT, and FIG. 12B is a graph showing the relationship between the emitter-gate voltage and the saturation collector current in the semiconductor structure.

FIG. 13 is a sectional view showing a semiconductor structure of an IGBT according to a fourth embodiment of the present invention.

14A is a plan view showing a plane pattern realizing the semiconductor structure of FIG. 13, FIG. 14B is a sectional view taken along the line AA ′ in FIG. 14A, and FIG. Is B- in (a).
It is the cutting arrow view cut along the B 'line.

15A is a plan view showing a plane pattern of a structure obtained by improving the structure shown in FIG. 14, and FIG. 15B is a plan view showing A- in FIG.
FIG. 3C is a sectional view taken along line A ′, and FIG. 3C is a sectional view taken along line BB ′ in FIG.

FIG. 16 is a cross-sectional view showing a general semiconductor structure of a conventional IGBT.

17A is a sectional perspective view showing a structure in which a diffusion resistance is added to a source side in a conventional IGBT semiconductor structure, and FIG. 17B is a sectional perspective view showing a partial channel structure in a conventional IGBT semiconductor structure. is there.

[Explanation of symbols]

1 ... a collector electrode 2 ... ^{p +} -type collector layer 3 ... ^{n +} -type buffer layer 4 ... n ^- -type conductivity modulation layer 5 ... gate insulating film 6 ... gate electrode 7, 17 ... p-type emitter layer 7a ... ^{p +} -type main Emitter region 7b ... p-type circumscribed emitter region 7c ... p ^++- type inscribed emitter region 7d ... bulging portion 8, 18 ... emitter electrode 8a ... contact hole 9 ... n-type source layer 9A ... n-type source region 9B ... n ⁺ -type Source contact region 10 Semiconductor substrate 11 Silicon oxide film 12 Interlayer insulating film (phosphorus glass layer) 16 Second gate electrode 17a P-type lightly doped emitter layer 17b P-type lightly doped emitter layer 19 ... source layer 19a ... channel width corresponding portions 19b ... narrow portion 28 ... second emitter electrodes 29, 39 ... ^{n +} -type source contact layer a, 17A ... low concentration region B in P-type 17b ... areas of highly concentrated P-type 100 ... composite IGBT V _{TH1 ...} low threshold voltage V _{TH2 ...} high threshold voltage L _a, L b _... channel length.

Claims (2)

[Claims] A first insulated gate bipolar transistor (hereinafter, referred to as an IGBT) of a first conductivity type, which is current-controlled by a gate voltage, is connected in parallel to the first IGBT, and the current is controlled by the gate voltage. And a second IGBT of the first conductivity type to be controlled is monolithic, and the threshold voltage V _TH2 of the second IGBT is equal to the first IGBT.
A semiconductor device comprising an insulated gate bipolar transistor, wherein the semiconductor device is set to be higher than a threshold voltage _{VTH1 of} T on the order of 1V. 2. The first IGBT according to claim 1,
A semiconductor device comprising an insulated gate bipolar transistor, wherein the on-resistance of the second IGBT is set higher than the on-resistance of the second IGBT.