JP2001352038A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To shorten the design period and prevent an increase in the circuit scale of a memory unit. SOLUTION: A signal processing circuit 101, a memory controller 102, a BIST circuit 1 are provided in a logic chip 100.
03, 104, BIST controller 105, EEPR
OM 106, register 107, EX-NOR circuit 10
8. A selection switch 109 is provided. EEPROM 106
Stores a defective address FAD. Register 107
Has a storage area corresponding to the defective address stored in the EEPROM 106. When the address AD from the signal processing circuit 101 matches the defective address FAD stored in the EEPROM 106, the EX-NOR circuit 108
An H level switching signal SW is supplied to the selection switch 109. The selection switch 109 connects the data bus DB1 and the data bus DB2. The register 107 selects an area corresponding to the order NB and enables writing / reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a function of detecting a defective memory cell having a defect and a function of relieving the defective memory cell.

[0002]

2. Description of the Related Art With the improvement in the degree of integration of semiconductor integrated circuits (LSIs), a "multi-chip module" in which functions such as a logic circuit and a memory which have been configured as separate packages are mounted in one package. Design and development of a "system LSI" formed on one chip has been performed.

[0003] Multi-chip modules and system LSIs
The advantage is that power consumption can be reduced,
For example, the processing speed can be improved because the access bandwidth can be widened.

[0004] On the other hand, the disadvantage is that the yield of completed LSIs is reduced. This is because if a defect exists in the memory, the LSI as a whole is determined to be defective even if no defect exists in the logic circuit.

Therefore, in order to improve the yield, a method of providing a redundant circuit in the memory in advance to remedy the defect has been adopted. Furthermore, in order to reduce the inspection cost of the memory, a BIST (Build In
An inspection circuit called “Self Test” is provided.

[0006]

By mounting functions previously realized in a plurality of packages, such as a logic circuit and a memory, in a single package, the number of components required for a set such as a television or a video is increased. Can be reduced. Thereby, the development efficiency of the set can be increased. Therefore, LSI design and development are playing an important role in the development of sets.

[0007] Multi-chip module and system LSI
In this design, the design period is shortened and the cost is reduced by reusing the past design resources.

[0008] However, not all memories existing as design resources in the past have the functions of a redundant circuit and a test circuit. Particularly, memories used for special purposes often do not have these functions. In such a case, in order to improve the yield of the completed LSI, a memory having a function of a redundant circuit or a test circuit must be newly designed from scratch. This leads to a longer design period.

When a memory is provided with a function of a redundant circuit or a test circuit, the circuit scale of the memory is correspondingly increased. This is particularly noticeable in an LSI having a plurality of memories.

[0010]

According to one aspect of the present invention, a semiconductor integrated circuit device includes a memory chip, a signal processing unit, a test unit, a defective address storage unit, a register unit, and a rescue unit. Is provided. Memory chip, signal processing unit,
The inspection unit, the defective address storage unit, the register unit, and the rescue unit are mounted in the same package.

The memory chip has a plurality of memory cells. The signal processing unit is provided outside the memory chip, specifies an address for the memory chip, and writes / reads data to / from a memory cell corresponding to the specified address. The inspection unit is provided outside the memory chip and detects a defective memory cell having a defect among the plurality of memory cells. The defective address storage unit is provided outside the memory chip and stores an address of a defective memory cell detected by the inspection unit. The register section is provided outside the memory chip, and has a storage area associated with the defective address stored in the defective address storage section.
The rescue unit is provided outside the memory chip, and when the address specified by the signal processing unit matches the defective address stored in the defective address storage unit, the signal processing unit registers the defective unit with the corresponding defective address. Write / read data to / from the storage area.

In the above semiconductor integrated circuit device, the inspection unit, the defective address storage unit, the register unit,
And a relief unit. Therefore, in designing a memory chip, the yield of completed semiconductor integrated circuit devices can be reduced even when a memory design resource that does not have a function of detecting a defective memory having a defect and a function of relieving the defective memory is used. Can be improved. Further, since it is not necessary to newly design and develop a memory chip having a function of detecting a defective memory having a defect and a function of relieving the defective memory, the design period can be shortened. In addition, an increase in the circuit size of the memory chip can be prevented.

According to another aspect of the present invention, a semiconductor integrated circuit device includes a memory unit, a signal processing unit, an inspection unit, a defective address storage unit, a register unit, and a rescue unit. The memory section, signal processing section, inspection section, defective address storage section, register section, and rescue section are formed on the same chip.

The memory section has a plurality of memory cells.
The signal processing unit is provided outside the memory unit, specifies an address for the memory unit, and writes / reads data to / from a memory cell corresponding to the specified address. The inspection unit is provided outside the memory unit and detects a defective memory cell having a defect among the plurality of memory cells. The defective address storage unit is provided outside the memory unit and stores an address of a defective memory cell detected by the inspection unit. The register section is provided outside the memory section, and has a storage area associated with the defective address stored in the defective address storage section. The rescue unit is provided outside the memory unit, and when the address specified by the signal processing unit matches the defective address stored in the defective address storage unit, the signal processing unit registers the defective unit with the corresponding defective address. Write / read data to / from the storage area.

In the above-mentioned semiconductor integrated circuit device, an inspection section, a defective address storage section, a register section, and a relief section are provided outside the memory section. Therefore, in designing the memory section, the yield of the completed semiconductor integrated circuit device can be reduced even if the design resources of the memory not having the function of detecting the defective memory having the defect and the function of relieving the defective memory are used. Can be improved. Further, since it is not necessary to newly design and develop a memory unit having a function of detecting a defective memory having a defect and a function of relieving the defective memory, the design period can be shortened.
Further, it is possible to prevent an increase in the circuit scale of the memory unit.

Preferably, the rescue section includes a comparison / determination circuit and a selection switch. The comparison determination circuit determines whether or not the address specified by the signal processing unit matches the defective address stored in the defective address storage unit. The selection switch forms a data path between the register unit and the signal processing unit when the comparison and determination circuit determines that they match.

In the above semiconductor integrated circuit device, when the address specified by the signal processing section matches the defective address stored in the defective address storage section, a data path is formed between the register section and the signal processing section. Is done. Then, the signal processing unit writes / reads data to / from the storage area of the register unit associated with the defective address.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

<Structure> FIG. 1 is a block diagram showing an overall structure of a semiconductor integrated circuit (LSI) according to an embodiment of the present invention. Referring to FIG. 1, this LSI is a multi-chip module in which a logic chip 100 and memory chips 200 and 300 are mounted in the same package 1. As described above, the logic chip 100 and the memory chips 200 and 300 are combined into one package 1 and used as an LSI having one large function.

The logic chip 100 includes the signal processing circuit 1
01, the memory controller 102, and the BIST (Bu
ilt In Self Test) circuits 103 and 10
4, the BIST controller 105, and the EEPROM 1
06, a register 107, and an EX-NOR circuit 108
And a selection switch 109.

The signal processing circuit 101 includes a memory chip 20
0, 300 to write / read data to / from a memory cell corresponding to that address.
Perform reading. The address signal AD includes information related to the memory chips 200 and 300 for writing / reading and addresses of memory cells in the memory chips.

The memory controller 102 receives an address signal AD from the signal processing circuit 101 and, when writing / reading is performed on a memory cell in the memory chip 200, an active selection signal for the memory chip 200. When C1 is applied and writing / reading is performed on a memory cell in the memory chip 300, an active selection signal C2 is applied to the memory chip 300.

The BIST circuit 103 includes the memory chip 20
A defective memory cell having a defect among the memory cells in 0 is detected. The BIST circuit 104 includes the memory chip 300
Detect defective memory cells having a defect among the memory cells in the memory cells.

The BIST controller 105 controls the BIST corresponding to the memory chips 200 and 300 to be inspected.
Activate the circuits 103 and 104 and set the BIST circuit 1
03, 104, the address of the defective memory cell detected is specified.

The EEPROM 106 stores an address (hereinafter, also referred to as a defective address) FAD of a defective memory cell specified by the BIST controller 105. The register 107 has a storage area corresponding to the defective address stored in the EEPROM 106.

The EX-NOR circuit 108 is an exclusive circuit for the address signal AD from the signal processing circuit 101 and the defective address FAD stored in the EEPROM 106.
-Output NOR (exclusive NOR). EX-NO
The output from the R circuit 108 becomes a switching signal SW.

The selection switch 109 responds to a switching signal SW from the EX-NOR circuit 108 to switch the data bus DB
1 and the data bus DB2 or DB3. The data bus DB1 is connected to the signal processing circuit 101 and the selection switch 1
This is a bus for exchanging data with the H.09. The data bus DB2 is a bus for exchanging data between the selection switch DB2 and the register 107. The data bus DB3 is a bus for exchanging data between the selection switch 109 and the memory chips 200 and 300.

Each of memory chips 200 and 300 includes a plurality of memory cells (not shown) arranged in rows and columns in a matrix. Examples of such a memory chip include a DRAM (dynamic random access memory) and an SRAM (static random access memory).

FIG. 2 shows the EEPROM 106 shown in FIG.
FIG. 4 is a diagram showing a correspondence relationship between a defective address stored in the register 107 and a storage area in the register 107. Here, it is assumed that the addresses A and B of the memory chip 200 and the addresses C and D of the memory chip 300 are stored in the EEPROM 106 as defective addresses.

As shown in FIG. 2, each of the defective addresses FAD stored in the EEPROM 106 is associated with an order NB. The association is in accordance with the order stored in the EEPROM 106. That is, the first defective address given from the BIST controller 105 is the address A of the memory chip 200, and is stored in association with the order 1. Similarly, the address B of the memory chip 200 and the addresses C and D of the memory chip 300 given in the 2-4th order are stored in association with the order 2-4, respectively.

On the other hand, also in the register 107, storage areas associated in order are allocated. For example, region A for order 1, region B for order 2,
Region C is assigned to order 3, and region D is assigned to order 4.

As described above, the order of the EEPROM
The defective address stored in 106 and the storage area in register 107 are associated with each other. That is, the address A of the memory chip 200, which is the first defective address given from the BIST controller 105, is stored in the register 10
7 is associated with the area A. Similarly, the memory chip 200 which is the second-fourth defective address is given.
B of the memory chip and addresses C and D of the memory chip 300
Are respectively associated with areas BD in the register 107.

The number of repairable defective memory cells depends on the capacity of the register 107 and the EEPROM 106.

<Operation> Next, the operation of the semiconductor integrated circuit configured as described above will be described. here,
A description will be given of (1) detection of a defective memory cell having a defect and (2) rescue of the defective memory cell. (1) Detection of defective memory cell First, the memory chips 200 and 300 to be tested are selected by the BIST controller 105, and the BIST circuits 103 and 104 corresponding to the selected memory chip.
Is activated.

Activated BIST circuits 103 and 104
Sequentially specifies addresses for the corresponding memory chips 200 and 300 in accordance with a test pattern created internally, and writes data to a memory cell corresponding to the specified address. Next, the written data is read. Then, it is determined whether or not the read data and the data to be written (expected value data) match.

Next, the BIST controller 105
Non-defective products and defective products are determined based on the results of the determination in the BIST circuits 103 and 104.

If the BIST controller 105 determines that the defective memory cell is defective, it specifies the address of a defective memory cell having a defect. The specification of the address of the defective memory cell is performed by the BIST controller 105 alone or together with a CPU (not shown) included in the logic chip 100. The means for specifying the address of the defective memory cell based on the result of the determination by the BIST circuit is a known means, for example, Japanese Patent Application Laid-Open No. H11-317096,
It is disclosed in JP-A-10-302499 and the like.

Next, the specified defective address is the EEP
The data is written to the ROM 106. At this time, as shown in FIG. 2, the information is stored in association with the order.

The reason why the EEPROM 106 is used as a memory for storing a defective address is as follows. That is, normally, the test for detecting a defective memory cell is performed only once before shipment of a finished product, and therefore, the chance of writing the detected result may be one. Therefore, an EEPROM, which is a memory that can be written only once, is used. (2) Relief of defective memory cell Next, relief of a defective memory cell having a defect will be described.

The address AD is output by the signal processing circuit 101.
Is specified. It is assumed that the specified address AD is the address A of the memory chip 200. Signal processing circuit 10
1 of the memory chip 200 designated by
Is supplied to one of the inputs of the EX-NOR circuit 108. The other of the inputs of the EX-NOR circuit 108 includes an EEP
The defective addresses FAD stored in the ROM 106 are sequentially applied. Here, the address is given in order from the defective address corresponding to the order 1. It is also assumed that the EEPROM 106 stores a defective address as shown in FIG. Further, the order N corresponding to the defective address FAD given to the other input of the EX-NOR circuit 108
B is applied to the register 107.

Address AD from signal processing circuit 101
(Here, the address A of the memory chip 200) is EE
When the address matches the defective address FAD stored in the PROM 106 (here, the address A of the memory chip 200 corresponding to the order 1), the EX-NOR circuit 108 switches the H-level (logic high level) switching signal SW to the selection switch 1
09.

In response to the H-level switching signal SW, the selection switch 109 switches between the data bus DB1 and the data bus DB.
2 is connected. Thereby, the signal processing circuit 10
1 and the register 107 form a data path.
Further, in response to the H-level switching signal SW, the register 1
07 selects an area (here, area A) corresponding to the given order NB (here, 1) and makes the area writable / readable. Then, the data from the signal processing circuit 101 is written to the area A of the register 107, or the data stored in the area A is read.
In this way, a defective memory cell having a defect (here, a memory cell corresponding to address A of memory chip 200) is relieved.

Next, a case where the address AD specified by the signal processing circuit 101 does not match any of the defective addresses stored in the EEPROM 106, for example, a case where the address E of the memory chip 200 is specified will be described.

The EX-NOR circuit 108 supplies the selection switch 109 with an L level (logic low level) switching signal SW. In response to the L-level switch signal SW, the selection switch 109 switches the data bus DB1 and the data bus D
B3 is connected. Thereby, the signal processing circuit 1
01 and the memory chips 200 and 300, a data path is formed.

In response to the address AD (here, the address E of the memory chip 200) specified by the signal processing circuit 101, the memory controller 102 sends a selection signal (here, the memory chip 200) for the corresponding memory chip (here, the memory chip 200). Then, the selection signal C1) is activated.
Receiving the activation selection signal C1, the memory chip 200 is activated. Then, data from the signal processing circuit 101 is written to a memory cell corresponding to the address E of the memory chip 200, or data stored in the memory cell is read.

<Effects> As described above, in the semiconductor integrated circuit according to the embodiment of the present invention, the logic chip 100
The BIST circuits 103 and 104, the BIST controller 105, the EEPROM 106, and the register 10
7, EX-NOR circuit 108, selection switch 109
Thus, in designing the memory chips 200 and 300, a completed semiconductor integrated circuit (package) can be used even if a memory design resource that does not have a function of detecting a defective memory cell and a function of relieving it is used. Yield can be improved.

Further, since it is not necessary to newly develop a memory having a function of detecting a defective memory cell and a function of relieving the memory cell, the design period can be shortened. Further, an increase in the circuit scale of the memory chip can be suppressed.

The BIST circuits 103 and 104, BI
The ST controller 105, the EEPROM 106, the register 107, the EX-NOR circuit 108, and the selection switch 109 are provided in one chip 100, but if they are outside the memory chips 200 and 300, they are provided in a plurality of chips. You may.

Although a multi-chip module in which a plurality of chips are mounted in one package has been described, a system LSI in which blocks having a plurality of functions are formed on one chip (see FIG. 1) A logic unit having the same function as the logic chip 100;
The same effects as described above can be obtained for a system LSI in which a memory unit having the same function as the memory chips 200 and 300 is formed on the same chip.

In a multichip module, a system LSI, or the like, since the distance between the memory chip (memory section) and the logic chip (logic section) is short, a function of detecting and relieving a defective memory in the logic chip (logic section) is provided. , There is no problem in terms of signal bandwidth, speed, etc. as compared with the case where these functions are provided in a memory chip (memory section).

[0051]

According to the semiconductor integrated circuit device according to one aspect of the present invention, the inspection unit, the defective address storage unit, the register unit, and the rescue unit are provided outside the memory chip.
In designing a memory chip, even if a memory design resource that does not have a function of detecting a defective memory having a defect and a function of relieving the defective memory is used,
The yield of the completed semiconductor integrated circuit device can be improved. Further, since it is not necessary to newly design and develop a memory chip having a function of detecting a defective memory having a defect and a function of relieving the defective memory, the design period can be shortened. In addition, an increase in the circuit size of the memory chip can be prevented.

In the semiconductor integrated circuit device according to another aspect of the present invention, the inspection unit, the defective address storage unit, the register unit, and the rescue unit are provided outside the memory unit. Even when a memory design resource that does not have a function of detecting a defective memory and a function of relieving the defective memory is used, the yield of the completed semiconductor integrated circuit device can be improved. Further, since it is not necessary to newly design and develop a memory unit having a function of detecting a defective memory having a defect and a function of relieving the defective memory, the design period can be shortened. Further, it is possible to prevent an increase in the circuit scale of the memory unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between a defective address stored in the EEPROM shown in FIG. 1 and a storage area in a register.

[Explanation of symbols]

 1 Package 101 Signal Processing Circuit 103, 104 BIST Circuit 105 BIST Controller 106 EEPROM 107 Register 108 EX-NOR Circuit 109 Selection Switch 200, 300 Memory Chip DB1-DB3 Data Bus

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (3)

[Claims] A memory chip having a plurality of memory cells; an address provided outside the memory chip, designating an address for the memory chip, and writing data to a memory cell corresponding to the designated address. A signal processing unit for performing read / read; a test unit provided outside the memory chip to detect a defective memory cell having a defect among the plurality of memory cells; and a test unit provided outside the memory chip. A defective address storage unit that stores an address of a defective memory cell detected by the memory unit; and a register unit that is provided outside the memory chip and has a storage area that is associated with the defective address stored in the defective address storage unit. An address provided outside the memory chip and designated by the signal processing unit; A rescue unit configured to write / read data to / from the storage area of the register unit associated with the defective address when the address matches the defective address stored in the storage unit. A semiconductor integrated circuit device, wherein the memory chip, the signal processing unit, the inspection unit, the defective address storage unit, the register unit, and the rescue unit are mounted in the same package. 2. A memory unit having a plurality of memory cells, and an address provided outside the memory unit, designating an address to the memory unit, and writing data to a memory cell corresponding to the designated address A signal processing unit for performing read / read; a test unit provided outside the memory unit to detect a defective memory cell having a defect among the plurality of memory cells; and a test unit provided outside the memory unit. A defective address storage unit for storing an address of a defective memory cell detected by the memory unit; and a register unit provided outside the memory unit and having a storage area associated with the defective address stored in the defective address storage unit. A defective address provided outside the memory unit, wherein an address specified by the signal processing unit is stored in the defective address storage unit; And a rescue unit for writing / reading data to / from a storage area of the register unit associated with the defective address when the signal unit matches the defective address. A semiconductor integrated circuit device, wherein the processing unit, the inspection unit, the defective address storage unit, the register unit, and the rescue unit are formed on the same chip. 3. The semiconductor integrated circuit device according to claim 1, wherein the rescue unit matches an address specified by the signal processing unit with a defective address stored in the defective address storage unit. A comparison / judgment circuit for judging whether or not to perform the judgment; and
A semiconductor integrated circuit device, comprising: a selection switch that forms a data path between the register unit and the signal processing unit.