JP2001350668A - Memory readout timing adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory readout timing adjusting circuit automatically adjusting timing and absorbing the difference in characteristic caused by the variation and the aging change with year of every device. SOLUTION: Prescribed data are written at a predetermined address as a check address, then check data are recorded in a written data storage section 12. A timing signal RDT is given from a readout controller 13 to read the check address. The read data RDD are latched at the timing of latch pulse signals A0-An by latching circuits 150-15n, and latched results are compared with the data recorded in the written data storage section 12 by comparing circuits 160-16n. A judging section 17 judges the optimum latch pulse signal based on compared results, and a selecting section 18 selects and outputs the input from the latching circuit corresponding to the optimum latch pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for automatically adjusting signal timing, and more particularly to a memory read timing adjustment circuit for adjusting a latch timing of data read from a memory.

[0002]

2. Description of the Related Art In a conventional general memory read circuit, the access timing to a memory is fixed to a timing determined by design. This fixed timing needs to absorb all variations and aging of each device and each element, and it is difficult to design. Further, when the memory to be accessed is changed due to a design change or the like, it is necessary to review the timing design and change the design of the memory read circuit as needed.

[0003] There is a memory access circuit provided with a dip switch or the like to make it possible to adjust the timing in order to eliminate the difficulty of design and the complexity of design change work, and to increase design flexibility and versatility. The latch timing of the data read from the memory is made variable by setting a dip switch.

[0004] According to this method, it is possible to absorb variations in each device and each element by individually adjusting at the time of shipping test of the device, etc. Can be absorbed.

[0005]

In a conventional memory read timing adjustment circuit using a dip switch or the like, it is necessary to adjust the timing individually in a shipping test of the device or the like in order to absorb variations between devices and elements. This is one of the factors that increase the man-hour.

Further, in order to absorb the aging, it is necessary to readjust the device from time to time after using the device, and the operation is complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory read timing adjustment circuit which automatically adjusts data latch timing to absorb differences in characteristics of devices due to variations between devices and devices and aging. It is.

[0008]

In order to achieve the above object, a memory read timing adjustment circuit according to the present invention is a memory read timing adjustment circuit for adjusting the timing of latching data read from a memory,
A write control unit that writes predetermined data to a predetermined address for checking, a write data storage unit that stores data written to the address by the write control unit, a timing signal for reading data at the address, A read control unit for outputting a latch pulse signal for latching read data read from a memory according to the timing signal, and a latch for delaying the latch pulse signal by different times to generate at least one delayed pulse signal A pulse delay unit, a plurality of latch circuits provided corresponding to the latch pulse signal or the delay pulse signal, and a plurality of latch circuits respectively latching the read data with the corresponding latch pulse signal or the delay pulse signal; Latch the corresponding latch circuit. A plurality of comparator circuits for comparing the data stored in the write data storage unit switch data,
A determination unit that determines an optimal latch timing signal from a latch pulse signal and a delay pulse signal based on a comparison result of a comparison circuit; and a latch circuit corresponding to the optimal latch timing signal based on the determination result of the determination unit. And a selection unit for selecting the output of

Therefore, the present memory read timing adjustment circuit latches the data read from the memory at a plurality of latch timings, determines the optimum latch timing from the normality of each latched data, and automatically applies the latch timing. can do.

Also, since the comparison results of all the latch timing data can be obtained at the same time, the optimum timing can be immediately determined from a plurality of latch results.

Another memory read timing adjustment circuit according to the present invention is a memory read timing adjustment circuit for adjusting the timing of latching data read from a memory, wherein predetermined check data is externally written. A read control unit that outputs a timing signal for reading the data of the inserted address and a latch pulse signal for latching the read data read from the memory by the timing signal, and delays the latch pulse signal by different times from each other A latch pulse delay unit for generating at least one delay pulse signal, and a plurality of latches provided corresponding to the latch pulse signal or the delay pulse signal and respectively latching read data with the corresponding latch pulse signal or the delay pulse signal Circuit and A plurality of comparison circuits provided corresponding to the circuit and comparing the data latched in the corresponding latch circuit with the check data; and an optimum among the latch pulse signal and the delay pulse signal based on a comparison result of the comparison circuit. And a selection unit that selects an output of the latch circuit corresponding to the optimal latch timing signal based on the determination result of the determination unit.

According to this, the read timing can be adjusted even in a configuration in which writing and reading to and from the memory are performed by different devices.

According to an embodiment of the present invention, the determining unit determines a signal of an optimal latch timing for each memory corresponding to the address, and the selecting unit, when reading data from the memory, determines an optimal signal for the memory. A memory read timing adjustment circuit is connected to a plurality of memories for selecting an output of a latch circuit corresponding to a signal of a latch timing, and the address is predetermined for each memory.

According to this, in a circuit configuration for reading data from a plurality of memories, data read from each memory can be latched at an optimum timing.

Still another memory read timing adjustment circuit according to the present invention is a memory read timing adjustment circuit for adjusting a timing at which data read from a memory is latched, wherein a predetermined address for checking is provided at a predetermined address. A write control unit for writing data, a write data storage unit for storing data written to an address by the write control unit, a timing signal for reading data at the address, and data read from the memory by the timing signal. A read control unit for outputting a latch pulse signal for latching, and a read data signal output from the memory by a timing signal being delayed by different times from each other for at least one
A data delay unit for generating one delayed data signal, a plurality of latch circuits provided corresponding to the read data signal or the delayed data signal, and each latching the corresponding read data signal or delayed data signal with a latch pulse signal; A plurality of comparison circuits provided corresponding to the circuits, for comparing the data latched in the corresponding latch circuits with the data stored in the write data storage unit; and a read data signal or delay based on the comparison result of the comparison circuits. It has a judging unit for judging an optimum delay signal from the data signals, and a selecting unit for selecting an output of the latch circuit corresponding to the optimum delay signal based on the judgment result of the judging unit.

Still another memory read timing adjustment circuit according to the present invention is a memory read timing adjustment circuit for adjusting a timing of latching data read from a memory, wherein predetermined check data is externally written. A read control unit that outputs a timing signal for reading the data of the embedded address, and a latch pulse signal for latching the data read from the memory by the timing signal; and a read output from the memory by the timing signal A data delay unit that delays the data signals by different times to generate at least one delayed data signal, and is provided corresponding to the read data signal or the delayed data signal;
A plurality of latch circuits each of which latches a corresponding read data signal or a delayed data signal with a latch pulse signal; and a plurality of latch circuits provided corresponding to the latch circuits and comparing the data latched in the corresponding latch circuit with the check data. A determination circuit that determines an optimum delay signal from a read data signal or a delay data signal based on a comparison result of the comparison circuit, and an optimum delay signal based on a determination result of the determination unit. And a selector for selecting an output of the latch circuit to be operated.

According to an embodiment of the present invention, the judging section judges an optimal delay signal for each memory corresponding to the address, and when selecting data from the memory, the selecting section judges an optimal delay signal for the memory. And a memory read timing adjustment circuit connected to a plurality of memories for selecting the output of the latch circuit corresponding to the above-mentioned signal and having the address predetermined for each memory.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory read timing adjustment circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a memory read timing adjustment circuit according to an embodiment of the present invention
1, a write data storage unit 12, a read control unit 13, a latch pulse delay unit 14, a data latch unit 15, a comparison unit 16, a determination unit 17, and a selection unit 18.

The write control unit 11 outputs a timing signal WRT for writing data to the RAM 1.

The write data storage unit 12 records the data written in the RAM 1 at the time of timing adjustment.

The read control unit 13 receives a timing signal R given to the RAM 1 in order to read data from the RAM 1.
DT and a latch pulse signal A0 for latching data read from the RAM 1 are output.

A latch pulse delay section 14 delays an input signal by a predetermined time and outputs the delayed signal.
, 14n (n is a natural number) are connected in series. The latch pulse signal A0 output from the read control unit 13 is input to the delay circuit 141, and latch pulse signals A1, A2,... An with different delay times are output from the delay circuits 141, 142,. I have.

The data latch section 15 includes a latch circuit 15
, 15n. Latch circuit 15
, 15n are RA signals at the timing of latch pulse signals A0, A1, A2,.
The data read from M1 is latched and output.

The data comparing section 16 includes comparing circuits 160, 1
61, 162,..., 16n. Comparison circuit 16
, 16n compare the outputs of the latch circuits 150, 151, 152,..., 15n with the data recorded in the write data storage unit 12, respectively.

The determination unit 17 includes comparison circuits 160, 161,
The optimum latch pulse signal is determined from the comparison result of 162,..., 16n.

The selector 18 selects and outputs the output of the latch circuit corresponding to the latch pulse signal determined to be optimum by the determiner 17.

Next, the operation of the memory read timing adjustment circuit in FIG. 1 during the timing adjustment will be described. In order to write and read check data at the time of timing adjustment, a predetermined address of the memory 1 is predetermined as a check address.

First, a write address is specified by designating a check address as a write address, and a write timing signal WRT is supplied from the write control unit 11 to the RAM 1 using predetermined check data as write data. At this time, check data is recorded in the write data storage unit 12.

Thereafter, a check address is designated as the read address RDA, and a timing signal RDT is supplied from the read control unit 13 to the RAM 1 to read data.

The latch circuits 150, 151, 152,.
15n, the read data RDD is latched at the timing of the latch pulse signals A0, A1, A2,. Latch circuits 150, 151, 152,..., 15
n (latch result) and the data recorded in the write data storage unit 12 are compared with comparison circuits 160, 161, 162,
.., 16n.

Each of the comparison circuits 160, 161, 162,...
The determination unit 17 notified of the comparison result of 16n determines the optimum latch pulse signal based on the coincidence / mismatch. For example, as an example of the determination method, if there is only one matching circuit, the corresponding latch pulse signal is determined to be optimal. If the matching circuits are continuous, the center of the corresponding latch pulse signal is determined. That is, there is a method of determining the most stable one as the optimum. Further, as another method, if the coincident comparison circuits are continuous, a latch pulse signal having the shortest delay time among the latch pulse signals corresponding thereto is determined to be optimal, and the time required for data reading is shortened as much as possible. There is.

Thereafter, the selector 18 selects and outputs the input from the latch circuit corresponding to the optimal latch pulse signal.

Therefore, the memory read timing adjustment circuit of this embodiment latches the data read from the RAM 1 at a plurality of latch timings, and determines the optimal latch timing from the normality of each latched read data. Since it is automatically applied, the timing conditions at the time of designing the memory read circuit are relaxed, and the degree of freedom in designing is increased.

In addition, a change in the memory due to a design change, a change in the positional relationship between the read circuit and the memory due to a change in the memory mounting position, an increase / decrease in the load on each signal due to the addition / deletion of the memory, a change over time, etc. Even if the optimal timing for latching changes, the operation is automatically adjusted to the optimal timing and stable operation is performed.

Further, the determination unit 17 includes a comparison circuit 160, 1
Since all comparison results can be obtained simultaneously from 61, 162,..., 16n, the optimum timing can be immediately determined from a plurality of latch results, and the timing can be sequentially latched at different timings and adjusted by trial and error. No complicated control is required.

The memory read timing adjusting circuit according to the present embodiment includes, as shown in FIG.
May be external such as another device.

The configuration in which the write data storage unit 12 does not exist may be adopted.

In this case, the memory write timing adjusting circuit is replaced with the check data storage unit 2 storing predetermined check data instead of the write data storage unit 12.
1 and the check data from an external circuit is RA
Written to M1.

The memory read timing adjusting circuit reads the data R read by the read control unit 13.
.., 15n are connected to the latch circuits 150, 151, 152,.
, And the comparators 160, 161, 162,..., 1
In step 6n, the data is compared with the check data stored in the check data storage unit 21.

According to this, the timing can be adjusted even in a system configuration in which writing and reading to and from the RAM 1 are performed by different devices.

Further, the memory read timing adjustment circuit of this embodiment determines a latch pulse signal having an optimum delay for each of a plurality of memories, and determines a latch pulse signal having an optimum delay in accordance with an address at the time of a read operation. A circuit which selects and outputs data latched by a signal may be used.

In this case, the memory read timing adjustment circuit performs the timing adjustment operation a plurality of times for each memory. Then, as shown in FIG. 3, the determination result of the determination unit 21 of each timing adjustment operation is notified to the read control unit 22.
In the memory read operation after all the timing adjustment operations are completed, the read control unit 22 controls the selection of the selection unit 18 according to the address.

According to this configuration, in a configuration in which one memory read circuit reads data from a plurality of memories, the read data from each memory can be latched at the optimal timing, so that the read position depends on the mounting position of the memory. And a stable read operation is possible.

This is particularly effective when the readout circuit and the memory are in different devices, and the positional relationship between the readout circuit and the memory is significantly different for each memory.

Next, a memory read timing adjustment circuit according to another embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, a memory read timing adjustment circuit according to another embodiment of the present invention includes a write control unit 11, a write data storage unit 12, a read control unit 13, a data delay unit 41, a data latch unit 15, Comparison section 1
6, a determination unit 17 and a selection unit 18.

The write control unit 11 outputs a timing signal WRT for writing data to the RAM 1.

The write data storage section 12 records the data written in the RAM 1 at the time of timing adjustment.

The read control unit 13 is provided with a timing signal R to be supplied to the RAM 1 in order to read data from the RAM 1.
DT and a latch pulse signal A for latching data read from the RAM 1 are output.

The data delay section 41 delays the input data by a predetermined time and outputs the data.
, 41n, ..., 41n are connected in series. RA
The data RDD0 read from M1 is the delay circuit 2
11 and the delay circuits 411, 412,
, 41n, data signals RDD1, with different delay times.
RDD2,..., RDDn are output.

The data latch section 15 includes a latch circuit 15
, 15n. Latch circuit 15
, 15n are the timings of the latch pulse signal A, respectively, and the data RDD0, RDD
DD1, RDD2,..., RDDn are latched and output.

The data comparing section 16 includes comparing circuits 160, 1
61, 162,..., 16n. Comparison circuit 16
, 16n compare the outputs of the latch circuits 150, 151, 152,..., 15n with the data recorded in the write data storage unit 12, respectively.

The determination unit 17 includes comparison circuits 160, 161,
The read data with the optimal delay is determined from the comparison result of 162,..., 16n.

The selector 18 selects and outputs the output of the latch circuit corresponding to the read data determined to be optimum by the determiner 17.

Next, the operation of the memory read timing adjustment circuit of FIG. 4 at the time of timing adjustment will be described. As in the circuit of FIG. 1, a predetermined address of the memory 1 is determined in advance as a check address.

First, the write control section 11 supplies a write timing signal WRT to the RAM 1 to write check data to a check address of the RAM 1. At this time, check data is recorded in the write data storage unit 12.

Thereafter, the read control unit 13 sends the RAM 1
To read the data of the check address.

The read data RDD0 and the data RDD1, RDD2,..., RDDn delayed by the delay circuits 411, 412,.
The latch is performed at the timing of the latch pulse signal A in accordance with 0, 151, 152,.

The latch circuits 150, 151, 152,.
15n output (latch result) and write data storage unit 12
Are compared with the data recorded in the comparators 160, 161, 16
, 16n, and the determination unit 17 determines the optimal delay data based on the comparison result.

Thereafter, the selector 18 selects and outputs the input from the latch circuit corresponding to the data with the optimal delay.

Therefore, the memory read timing adjustment circuit of the present embodiment determines the optimum timing relationship among a plurality of data as the timing relationship between the data read from the RAM 1 and the latch timing and automatically applies it. In addition, the timing conditions at the time of designing the memory read circuit are relaxed, and the degree of freedom in design is increased.

Even if the optimum timing for latching data at the time of reading data from the RAM changes, the operation is automatically adjusted to the optimum timing and stable operation is performed.

Further, since all the comparison results can be obtained at the same time, the optimum timing can be determined immediately, and complicated control such as adjustment by trial and error is unnecessary.

[0065]

According to the present invention, data read from a memory is latched at a plurality of latch timings, and the optimum latch timing is determined from the normality of each latched data and automatically applied. Therefore, the timing conditions at the time of designing the memory read circuit are relaxed, and the degree of freedom in design is increased.

Further, even if the optimal timing for latching the data read from the memory changes, the operation is automatically adjusted to the optimal timing and stable operation is performed.

Further, since all the comparison results can be obtained at the same time, the optimum timing can be determined immediately, and complicated control such as adjustment by trial and error is unnecessary.

Further, even in a configuration in which writing and reading to and from the memory are performed by separate devices, the read timing can be adjusted, and a stable reading operation can be performed regardless of the mounting position of the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory read timing adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory read timing adjustment circuit when a write control unit is provided outside;

FIG. 3 is a block diagram illustrating a configuration of a memory read timing adjustment circuit that selects an optimal timing for each of a plurality of memories.

FIG. 4 is a block diagram illustrating a configuration of a memory read timing adjustment circuit according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RAM 11 Write control part 12 Write data storage part 13 Read control part 14 Latch pulse delay part 141-14n Delay circuit 15 Data latch part 150-15n Latch circuit 16 Data comparison part 160-16n Comparison circuit 17 Judgment part 18 Selection part 21 Check data storage unit 31 Judgment unit 32 Read control unit 41 Data delay unit 411-41n Delay circuit

Claims (6)

[Claims] 1. A memory read timing adjustment circuit for adjusting the timing of latching data read from a memory, comprising: a write control unit for writing predetermined data to a predetermined address for checking; A write data storage unit for storing data written to the address by the unit; a timing signal for reading the data at the address; and a latch pulse for latching read data read from the memory by the timing signal. A read control unit that outputs a signal, a latch pulse delay unit that delays the latch pulse signal by different times to generate at least one delayed pulse signal, and is provided corresponding to the latch pulse signal or the delayed pulse signal. The corresponding rack A plurality of latch circuits for respectively latching the read data with a pulse signal or the delayed pulse signal; and a plurality of latch circuits provided corresponding to the latch circuits and stored in the corresponding latch circuits and stored in the write data storage unit. A plurality of comparison circuits that compare the data with the data obtained by the comparison circuit; a determination unit that determines a signal of an optimal latch timing from the latch pulse signal and the delay pulse signal based on a comparison result of the comparison circuit; A memory read timing adjustment circuit including a selection unit that selects an output of the latch circuit corresponding to a signal of an optimal latch timing based on a determination result. 2. A memory read timing adjustment circuit for adjusting a timing of latching data read from a memory, the timing for reading data at an address where predetermined check data is externally written. signal,
And a read control unit for outputting a latch pulse signal for latching read data read from the memory by the timing signal; and generating at least one delayed pulse signal by delaying the latch pulse signal by different times from each other. A plurality of latch circuits provided corresponding to the latch pulse signal or the delay pulse signal and respectively latching the read data with the corresponding latch pulse signal or the delay pulse signal; A plurality of comparison circuits provided corresponding to the circuits and comparing the data latched in the corresponding latch circuit with the check data; and a latch pulse signal and the delay pulse based on a comparison result of the comparison circuit. Of the optimal latch timing A memory read timing adjustment circuit comprising: a determination unit that determines a signal; and a selection unit that selects an output of the latch circuit corresponding to a signal of an optimal latch timing based on a determination result of the determination unit. 3. The determination section determines an optimal latch timing signal for each of the memories corresponding to the address, and the selection section determines a signal of an optimal latch timing for the memory when reading data from the memory. 3. The memory read timing adjustment circuit according to claim 1, wherein an output of the latch circuit corresponding to (b) is selected, and the address is predetermined for each of the memories connected to the plurality of memories. 4. 4. A memory read timing adjustment circuit for adjusting the timing of latching data read from a memory, comprising: a write control unit for writing predetermined data to a predetermined address for checking; A write data storage unit for storing data written to the address by a unit; a timing signal for reading data at the address; and a latch pulse signal for latching data read from the memory by the timing signal. A data delay unit that delays a read data signal output from the memory by the timing signal by different times to generate at least one delayed data signal; and the read data signal or the delay. Data signal A plurality of latch circuits provided correspondingly and respectively latching the corresponding read data signal or the delayed data signal with the latch pulse signal; and a plurality of latch circuits provided corresponding to the latch circuit and latched by the corresponding latch circuit. A plurality of comparison circuits for comparing the read data with the data stored in the write data storage unit, and, based on a comparison result of the comparison circuit, a signal having an optimum delay from the read data signal or the delay data signal. A memory read timing adjustment circuit comprising: a determination unit for determining; and a selection unit that selects an output of the latch circuit corresponding to a signal having an optimal delay based on a determination result of the determination unit. 5. A memory read timing adjustment circuit for adjusting a timing of latching data read from a memory, the timing for reading data at an address where predetermined check data is externally written. signal,
And a read control unit that outputs a latch pulse signal for latching data read from the memory by the timing signal; and a read data signal output from the memory by the timing signal is delayed by different times. A data delay unit that generates at least one delayed data signal; provided in correspondence with the read data signal or the delayed data signal; and latches the corresponding read data signal or the delayed data signal with the latch pulse signal, respectively. A plurality of latch circuits, a plurality of comparison circuits provided corresponding to the latch circuits, for comparing the data latched in the corresponding latch circuits with the check data, based on a comparison result of the comparison circuits, The read data signal or the delay data Memory read timing, comprising: a determination unit that determines an optimal delay signal from data signals; and a selection unit that selects an output of the latch circuit corresponding to the optimal delay signal based on a determination result of the determination unit. Adjustment circuit. 6. The determination unit determines an optimal delay signal for each of the memories corresponding to the address, and the selection unit responds to an optimal delay signal for the memory when reading data from the memory. 6. The memory read timing adjustment circuit according to claim 4, wherein the output of the latch circuit is selected to be connected to the plurality of memories, and the address is predetermined for each of the memories.