JP2001350451A - Liquid crystal device, driving device and driving method thereof, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress flickers caused by low power consumption and parasitic capacitance accumulated in switching elements and wiring at the time of inverting the polarity of a voltage applied to a liquid crystal layer. SOLUTION: A counter electrode Cm is composed two rows of counter electrodes Cma and Cmb to each scanning line Ym. Adjoining pixels of those connected with each scanning line Ym are connected with these two rows of counter electrodes Cma and Cmb differently from each other. This liquid crystal device supplies different potentials to the two rows of counter electrodes Cma and Cmb corresponding to the selected scanning line in synchronization with the selection period for selecting the scanning line by a scanning line drive circuit 20 for supplying a scanning signal to a scanning line Xm a data line driving circuit 22 for supplying a data signal to a data line Yn, and a scanning line driving circuit 20, and is driven by a counter electrode driving circuit 24 for inverting the polarity of a voltage to be applied to each pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal device, a driving device and a driving method thereof, and an electronic apparatus.

[0002]

2. Description of the Related Art At present, active matrix type liquid crystal devices, in particular, TFTs (Thin)
Film Transistor type liquid crystal devices are driven by AC voltage, frame inversion drive, line inversion drive,
Source line inversion driving and dot inversion driving are known. Further, in these driving systems, a counter electrode inversion driving system in which a voltage having a polarity opposite to a voltage applied to the pixel electrode is applied to the counter electrode is used because it leads to a reduction in power consumption. In JP-A-7-160228,
Opposed to each other with the active matrix substrate and a liquid crystal layer as shown in FIG. 10 (a), and is configured with a counter electrode A ₁ ~A _n ~A _N on the counter substrate 110. FIG.
0 (a), the scanning lines Y ₁ to Y ₁ arranged on the active matrix substrate and arranged along the first direction.
Y _m to Y _M, and each of the second data lines X ₁ arranged along the direction of to X _n to X _N, are displayed in broken lines by tracings on the counter substrate 110. The counter electrodes A _{1 to} A _N
Are arranged corresponding to the source lines (data lines X _{1 to} X _N ) and are insulated from each other. In a liquid crystal device having such a counter substrate 110, low voltage driving of the liquid crystal device is realized by performing source line inversion driving for supplying data signal voltages having different polarities to adjacent data lines.

A liquid having the above-described counter substrate 110 is described below.
Crystal unit, source line inversion drive and dot inversion drive
The operation when this is performed will be described. Here, the counter electrode A_cYou
And data line X_cC is an odd number (1,3, ..., N-1),
Counter electrode A_dAnd data line X _dD is an even number (2, 4,
.., N).

First, the operation when the liquid crystal device is driven by dot inversion will be described with reference to the timing chart of FIG.

In a selection period H ₁ of a frame period f ₁ ,
To each of the counter electrodes A _c is supplied with negative voltage-Vcom, the positive polarity data signal voltage + Vd of the reverse and which is supplied to the data line X _c. At the same time, each of the counter electrodes A _d positive polarity voltage + Vcom is supplied. The data line _Xd has the opposite data signal voltage −V
d is supplied.

In the selection period H ₂ of the frame period f ₁ ,
To each of the counter electrodes A _c is supplied with positive voltage + Vcom, negative polarity data signal voltage -Vd opposite and this is the data line X _c are supplied. At the same time, each of the counter electrodes A _d is negative voltage -Vcom is supplied. The data line _Xd has the opposite positive data signal voltage + V
d is supplied.

[0007] Until the following frame period f ₁ selection period H ₃ ~ select period H _M, the above-described operation is performed alternately, the voltage of opposite polarity to each of the neighboring pixels are supplied. Frame period f
In _2, the frame period f ₁ at voltages of opposite polarity than those supplied to each pixel of the previous period, is supplied to each of the selected pixel.

As described above, in each of the selection periods H _{1 to} H _M , the counter electrode A is set to the positive polarity + Vcom or the negative polarity −Vcom.
com alternately.

Here, a more detailed operation will be described with reference to FIG. 12 showing a change in voltage of each pixel corresponding to a certain source line (data line).

FIG. 12 shows a change with time in voltage applied to each pixel corresponding to each of the _M scanning lines Y _{1 to} Y M in a liquid crystal panel composed of M scanning lines. . Each selection period during which the M scanning lines are selected,
H _{1 to} H _M are defined. In addition, here, for convenience,
An example is shown in which ± 5 V is uniformly applied to the liquid crystal. In the scan line Y _1, the selection period H ₁ frame period f _1,
A data signal voltage of +5 V is applied to the data line. In the scanning line Y ₂ is selected during the selection period H _2, during the period of the selection period H _2, -5V data signal voltage is applied to the data line. At this time, in the selection period of H ₂ scan lines Y _1, the polarity of the counter electrode is reversed driven. Thus, for example, when the voltage change due to the parasitic capacitance and the like is ± 0.1 V, the voltage −0.1 V due to the parasitic capacitance accumulated in the TFT 30 and the wiring is added to the pixel, and +4.9.
V. Similarly, in each of the scanning lines Y ₃ to Y _M , the voltage ± 0.1 V due to the parasitic capacitance is added to +5 V or −5 V that is originally applied to the liquid crystal. The voltage applied to the liquid crystal changes due to the voltage caused by the parasitic capacitance, and is recognized as flicker.

When the liquid crystal device is driven by dot inversion as described above, since the counter electrode must be swung every selection period, the electric power for driving the counter electrode increases. Note that this parasitic capacitance is caused by a thin film transistor (TF) as shown in FIG.
T) The capacitance C _GD generated between the gate G and the drain D of the T 30 and the capacitance C _DS generated between the drain D and the source S.

Next, when the liquid crystal device is driven by source line inversion driving, changes in voltage applied to each pixel corresponding to each of the _M scanning lines Y _{1 to} Y _M will be described with reference to FIG. 13 over time. .

[0013] In the frame period f _1, a positive data signal is applied. When the scanning line Y ₁ is selected during the selection period H ₁ , +5 V is applied to the pixel corresponding to the selected scanning line Y _1.
Is applied. When the scanning line Y ₂ is selected during the selection period H ₂ , similarly, a voltage of +5 V is applied to the pixel corresponding to the selected scanning line Y ₂ . However, the voltage Vcom of the counter electrode in synchronization with the selection period H ₁ frame period f _1, must be changed. For this reason, every time the polarity of the counter electrode changes, a voltage due to the parasitic capacitance or the like is applied to the liquid crystal.

In FIG. 13, a voltage change caused by a parasitic capacitance or the like is ± 0.1 V as an example. Therefore,
During the selection period H ₁ of the scanning line Y _2, the voltage applied to the liquid crystal is −5 V, which is +0.1 V due to the parasitic capacitance.
And -4.9V. Similarly, the scanning line Y ₃ is selected in the selection period H _3, even during the period of the selection period H _2, a voltage applied originally to the liquid crystal -5
The parasitic capacitance value +0.1 V is added to V, and it is -4.9 V. Similarly, in each of the scanning lines Y ₄ to Y _M , a voltage change of the liquid crystal occurs due to the parasitic capacitance. Due to this parasitic capacitance, a period occurs in which the voltage applied to the liquid crystal changes. This change in voltage causes flicker and uneven display due to vertical luminance gradient.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal device which solves the problem of low power consumption and the fact that the voltage to be applied to the liquid crystal is changed due to parasitic capacitance or the like and is recognized as flicker. An object of the present invention is to provide a driving device and a driving method thereof, and an electronic device.

[0016]

In order to solve the above-mentioned problems, a liquid crystal device according to one embodiment of the present invention is a method of scanning M rows (M is an integer of 2 or more) arranged along a first direction. Lines and,
N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction, one of the M rows of scanning lines, and one of the N columns of data lines. The connected M × N switching means, the M × N pixel electrodes respectively connected to one of the M × N switching means, and the M × N pixel electrodes via a liquid crystal layer. M × N opposing pixel electrodes arranged opposite to each other, scanning line driving means for supplying a scanning signal for selecting at least one of the M scanning lines to the M scanning lines, A data line driving unit that supplies a data signal to each of the N columns of data lines; a polarity inversion unit that inverts the polarity of a voltage applied to the liquid crystal layer; And M rows of first wirings and M rows of second wirings, Supplying a potential from each of the M rows of first wirings to odd-numbered opposing pixel electrodes in each row corresponding to the M rows of scanning lines, and from each of the M rows of second wirings, Supplying a potential different from the potential supplied to the first wirings of the M rows to the even-numbered opposing pixel electrodes in each row corresponding to the M scanning lines;
By the scanning line driving means, in synchronization with a selection period for selecting the at least one scanning line, the potential supplied to each of the first wiring and the second wiring corresponding to the selected scanning line is changed. It is characterized by further comprising means for changing. The invention of claim 5 defines a driving device for a liquid crystal device, and the invention of claim 8 defines a driving method of a liquid crystal device.

According to such a liquid crystal device, its driving device and its driving method of the present invention, when inverting the polarity of the voltage applied to the liquid crystal layer, it is synchronized with the timing when each scanning line is selected. Thus, the voltage applied to the opposing pixel electrode is changed. Note that two wirings are arranged corresponding to one scanning line. In each of the N opposing pixel electrodes corresponding to the one scanning line, a potential is supplied to the odd-numbered opposing pixel electrodes and the even-numbered opposing pixel electrodes from different wirings. By synchronizing the timing at which the potential is supplied from the wiring with the selection period, flicker due to the influence of the switching means and the parasitic capacitance accumulated in the wiring can be suppressed.

In the liquid crystal device according to the present invention, the M
In each of the first wirings in a row, different wirings are supplied to adjacent wirings in a frame period. In this case, for example, when the liquid crystal device is driven by dot inversion, flicker due to the influence of the parasitic capacitance accumulated in the switching means and the wiring can be suppressed as compared with the related art. Further, the counter electrode can be driven at a low frequency, and power consumption can be reduced.

In the liquid crystal device according to the present invention, the M
In each of the first wirings in a row, the wirings arranged adjacent to each other are supplied with the same potential in a frame period. In this case, for example, when the liquid crystal device is driven by the source line, flicker due to the influence of the parasitic capacitance accumulated in the switching means and the wiring can be suppressed as compared with the related art.

Further, in the liquid crystal device according to the present invention, the polarity inverting means is supplied with an input signal of the first logical information or the second logical information, and is sequentially shifted by the first shift register; An input signal having a logic opposite to that of the input signal supplied to the first shift register is supplied, and the input signal is sequentially shifted from the second shift register, and from the first and second shift registers for each selection period. A potential selection circuit that selects a potential to be supplied to each of the first wiring in the M rows and the second wiring in the M rows based on the supplied first logic information or the second logic information; It is characterized by having.

In this way, when the data signal voltage to the liquid crystal device is converted into an alternating current and the polarity is inverted, the potential of the opposite pixel electrode can be changed at the same time.

In the liquid crystal device substrate according to the present invention,
M rows (M is an integer of 2 or more) of scanning lines arranged along a first direction, and N (N is a natural number) columns arranged along a second direction intersecting the first direction Data lines and
M × N switching means respectively connected to one of the M rows of scanning lines and one of the N columns of data lines;
A substrate facing an active matrix substrate having one of the M × N switching means and M × N pixel electrodes connected thereto via a liquid crystal layer, and M × N counter pixel electrodes arranged to face each of the M × N pixel electrodes and a first of M rows connecting odd-numbered counter pixel electrodes in each of the M scanning lines. , And M rows of second lines connecting the even-numbered opposing pixel electrodes in each of the M rows of scanning lines, and the first wiring of the M rows and the second wiring of the M rows Are characterized by being insulated from each other.

By using the substrate having such a structure in the liquid crystal device according to the present invention, it is possible to easily control the potential supplied to the counter pixel electrode for each scanning line.

Further, the liquid crystal device according to the present invention can be applied to electronic equipment.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a liquid crystal device according to the present invention.

This liquid crystal device includes a liquid crystal panel 10, a signal control circuit section 12, a gradation voltage circuit section 14, a power supply circuit section 16,
It comprises a scanning line driving circuit 20, a data line driving circuit 22, and a counter electrode driving circuit 24. In FIG. 1, pixels formed on the liquid crystal panel 10 are denoted by P (1,1) to P (1,1).
Defined by P (m, n) to P (M, N). Each of m, n, and M is a natural number. Each scanning line is represented by Y, and each data line is represented by X. This scanning line Y
When only a specific scanning line or data line among the data lines X is designated, Y ₁ , Y ₂ ,... Y _m ,.
Y _M, or _{X 1, X 2, ...,} X n, ..., specified as X _N. The general name of the counter electrode is represented by C. Of the counter electrode C, each counter _{electrode, C 1, C 2, ...} , C m, ..., represent a C _M, if further specify only certain counter electrode,
_{C 1a, C 1b, C 2a} , C 2b, ..., C ma, C mb, ..., C Ma,
_Expressed as C _Mb .

FIG. 5 shows the connection relationship between the counter electrode C and the pixel P (m, n). FIGS. 5 (a) shows a formed on the active matrix, a structure of a scan line Y ₁ and the data line X ₁ pixel provided at the intersection of the P (1, 1). Pixel P (1,
1) A pixel electrode 3 provided at the drain of the TFT 30
2 and a storage capacitor 42. Other pixels have the same configuration as the pixel P (1,1). FIG. 5B shows a counter substrate 100 provided with the active matrix substrate and a liquid crystal layer interposed therebetween. Counter substrate 10
On the 0, M × N counter pixel electrodes 102 are provided corresponding to each of the M × N pixels. Further, on the opposing substrate 100, M opposing electrodes C _ma connected and wired to the pixels P (m, n _c ) (where n _c is an odd number), and the pixels P (m, n _d ) ( ( _nd is an even number) and M counter electrodes _Cmb connected and wired respectively.

The liquid crystal panel 10 is composed of (M × N) pixels. In the liquid crystal panel 10, in a certain pixel (1,1), the data lines X ₁ to the source of TFT30 is, scan lines Y ₁ are respectively connected to the gate G. The data lines X _{1 to} X _N are driven by the data line driving circuit 22, and the scanning lines Y _{1 to} Y _M are driven by the scanning line driving circuit 20. The pixel electrode 32 is provided on the drain D of the TFT 30. One end of the pixel electrode 32 is connected to a pixel capacitor 40 charged with a voltage applied to the liquid crystal layer and a storage capacitor 42 for storing data. The other ends of the pixel capacitance 40 and the storage capacitance 42 are connected to a counter electrode C
Connected to _one . Here, the counter electrode C ₁ includes counter electrodes C _1a and C _1b , and the other ends of the pixel capacitor 40 and the storage capacitor 42 are connected to the counter electrode C 1
Connected to _1a .

In the liquid crystal panel 10, (M × N) pixels having the same configuration as the pixel P (1, 1) as described above are formed. The pixel _{P (m, n c) (} n c is an odd number) in the other end of the counter electrode C _ma of the pixel capacitor 40 and the storage capacitor 42, the pixel _{P (m, n d) (} n d is an even number), the pixel The other _ends of the capacitance 40 and the storage capacitance 42 are connected to the counter electrode _Cmb , respectively.

The liquid crystal device shown in FIG. 1 is supplied with power, a data signal, a synchronization signal, and a clock signal from outside.

The signal control circuit section 12 receives the clock signal CL
K 1, the data signal Da and the horizontal synchronization signal Hsync are supplied to the data line drive circuit 22. The data signal Da is
For example, it is a digital signal for representing approximately 16.770,000 colors with 8-bit RGB signals. The data line driving circuit 22 latches the data signal Da at the timing of the clock signal CLK1. The horizontal synchronizing signal Hsync is supplied to the data line driving circuit 22 in synchronization with the latching of the data signal Da for one line. Based on the horizontal synchronizing signal Hsync, the latched data signal Da for one line is converted into an analog signal based on the reference voltage from the grayscale voltage circuit unit 14, then subjected to impedance conversion and supplied to each of the data lines X. Is done.

The signal control circuit section 12 supplies the clock signal CLK2 and the vertical synchronization signal Vsync to the scanning line drive circuit 20. The scanning line driving circuit 20 sequentially selects the scanning lines Y at the timing of the clock signal CLK2.
Switch. A scanning signal voltage for turning on the gate of the TFT 30 connected to the scanning line is applied during a selection period in which a specific scanning line Y is selected. Note that this scanning signal voltage is defined as a scanning signal S. The scanning signal S is defined as S ₁ , S ₂ ,..., S _m ,..., S _M sequentially from the scanning signal S ₁ supplied in the _first selection period H ₁ of the frame period. The data signal voltage Vd output from the data line driving circuit 22 is supplied to each of the data lines X in synchronization with the scanning signal S. One frame period after all the scanning lines X have been scanned, the vertical synchronizing signal Vsync is supplied to the scanning line driving circuit 20, and again the _first scanning line Y ₁
Are sequentially scanned.

Further, the signal control circuit section 12 includes a clock signal CLK2 and a polarity inversion signal F, as described later.
R is supplied to the counter electrode drive circuit 24.

The power supply circuit section 16 includes a gradation voltage circuit section 14,
Power is supplied to the scanning line driving circuit 20, the data line driving circuit 22, and the counter electrode driving circuit 24. For example, the counter electrode drive circuit 24 supplies two types of voltages to the counter electrode C based on the supplied power, for example, a voltage of positive polarity + Vcom and a voltage of negative polarity -Vcom.

The counter electrode drive circuit 24 includes, for example, a shift register group 54 and a potential selection circuit 56 as shown in FIG.
It is composed of Although not shown, the potential selection circuit 56 includes a level shifter, a driver, and the like.

The shift register group 54 is composed of, for example, M registers connected in series. In each of the shift registers 50 and 52, each register is denoted by a suffix 1 to M.

Each time the clock signal CLK2 is supplied to the shift register group 54, the information stored in the shift registers 50 and 52 is shifted. Shift register 50
Is converted into an analog signal by the potential selection circuit 56, amplified to a required voltage level, and supplied to each of the counter electrodes C.

Here, when the clock signal CLK2 is input to the shift register group 54, the change with time t to (t +
M) is shown in FIG. In FIG. 3, information “0” indicates a negative voltage −Vcom from the counter electrode driving circuit 24, and information “1” indicates a positive voltage + Vcom from the counter electrode driving circuit 24 and the counter electrodes C ₁ to C ₁ . supplied to each of the C _M. This information “0” or “1” is the polarity inversion signal F
Determined by R. For example, in the present embodiment, since the liquid crystal device is driven by the dot inversion method, adjacent pixels have different polarities. That is, the pixel connected to the counter electrode C _1a and the pixel connected to the counter electrode C _1b have different polarities. Further, the pixel connected to the counter electrode _C1a and the pixel connected to the counter electrode _C2a have different polarities. Therefore, the shift register 50
And the shift register 52 are supplied with different information by the polarity inversion signal FR.

The operation of the counter electrode drive circuit 24 when the liquid crystal device is driven by the dot inversion method will be described below.

At time t, information "1" is uniformly input to the shift register 50 and information "0" is uniformly input to the shift register 52, respectively. At time (t + 1), the clock signal CLK2 causes the register 50-
The information "1" of 1 is shifted to the register 50-2.
Information “0” of the register 52-1 is shifted to the register 52-2 by the clock signal CLK2. At the same time, the inverted information "0" is supplied to the register 50-1 and the inverted information "1" is supplied to the register 52-1 by the polarity inversion signal FR. At time t + 2, the information is further shifted by one stage by the clock signal CLK2, and the inverted information “0” is stored in the register 50-1 by the polarity inversion signal FR in the register 5
The inverted information “1” is supplied to 2-1. Similarly, until the time (t + M), the register 50-
M and each of the registers 52-M is supplied with the inversion information. As a result, the information of all the registers is inverted at the time (t + M) as compared with the time t.

Now, the timing chart of FIG. 4 will be described using the liquid crystal device of FIG. FIG. 4 shows a timing chart when the liquid crystal device according to the present invention is driven by the dot inversion method.

The scanning line Y ₁ is selected in the selection period H ₁ by the scanning signal S ₁ supplied at the beginning of the frame period f ₁ . A positive data signal voltage + Vd is supplied to each of the data lines X _c (c is an odd number). In synchronization with this, the counter electrode C _1a negative voltage -Vcom is supplied. Further, a data signal voltage −Vd of negative polarity is supplied to each of the data lines X _d (d is an even number). In synchronization with this, a positive voltage + Vcom is supplied to the counter electrode C _1b .

Next, the scanning signal S ₂ causes the selection period H _2.
Scanning line Y ₂ is selected. A data signal voltage -Vd of negative polarity is supplied to each of the data lines _Xc (c is an odd number). In synchronization with this, the counter electrode C _2a positive voltage + Vco
m is supplied. Further, a positive data signal voltage + Vd is supplied to each of the data lines X _d (d is an even number). In synchronization with this, the voltage of negative polarity to the counter electrode C _2b-Vcom
Is supplied.

Similarly, from the counter electrode driving circuit 24,
The timing at which the voltage −Vcom is supplied to each of the counter electrodes C is synchronized with each of the scanning signals S _{3 to} S _M. In a similar timing even frame period f _2,
The counter electrode drive circuit 24 is driven.

As described above, in the present embodiment, when inverting the polarity of the voltage applied to the liquid crystal layer, the voltage applied to the counter electrode is changed in synchronization with the timing when each scanning line is selected. I have. Such an operation uses the liquid crystal panel 10 configured with two counter electrodes _Cma and _Cmb for each scanning line, and the counter electrodes C of adjacent pixels are connected to different counter electrodes, respectively. This can be achieved by:
When the liquid crystal device is driven by dot inversion as described above, voltage fluctuation due to the influence of the switching means and the parasitic capacitance accumulated in the wiring can be eliminated, and flicker caused by this voltage fluctuation can be reduced. Can be suppressed. Further, each driving cycle of the counter electrode can be set to two frame periods. Therefore, the counter electrode can be driven at a low frequency, and power consumption can be reduced.

(Second Embodiment) The operation of the liquid crystal device according to this embodiment will be described with reference to the timing chart of FIG. FIG. 6 shows a timing chart when the liquid crystal device according to the present invention is driven by the source line inversion method. However, FIG. 6 for convenience, shows for each change of the pixels connected to the corresponding data lines X _1.

The scanning line Y ₁ is selected in the selection period H ₁ by the scanning signal S ₁ supplied at the beginning of the frame period f ₁ . Positive data signal voltage + Vd is supplied to the data line X _1. In synchronization with this, the counter electrode C _1a negative voltage -Vcom is supplied.

[0049] Then, by the scanning signal S _2, the selection period H ₂
Scanning line Y ₂ is selected. Positive data signal voltage + Vd is supplied to the data line X _1. In synchronization with this, the counter electrode C _2a negative voltage -Vcom is supplied.

Similarly, in the frame period f ₁ ,
The timing at which the voltage −Vcom is supplied from the counter electrode driving circuit 24 to each of the counter electrodes C _{3a to} C _Ma is synchronized with each of the scanning signals S _{3 to} S _M. In a similar timing even frame period f _2, the counter electrode driving circuit 24 is driven.

As described above, in the present embodiment, when inverting the polarity of the voltage applied to the liquid crystal layer, the voltage applied to the counter electrode is changed in synchronization with the timing when each of the scanning lines Y is selected. I have. Such an operation uses the liquid crystal panel 10 configured with two counter electrodes _Cma and _Cmb for each scanning line, and the counter electrodes C of adjacent pixels are connected to different counter electrodes, respectively. This can be achieved by:
When the liquid crystal device is driven by the source line inversion as described above, the voltage fluctuation due to the influence of the switching device and the parasitic capacitance accumulated in the wiring can be eliminated as compared with the related art, and the flicker caused by the voltage fluctuation can be eliminated. Can be suppressed.

(Third Embodiment) FIG. 7 shows a liquid crystal device according to a third embodiment of the present invention.

A data signal, a synchronization signal, and a clock signal are supplied to the signal control circuit unit 112. The signal control circuit unit 112 includes a clock signal CLKX, a horizontal synchronization signal Hs
yn1 and data signal Db are transmitted to data line drive circuit 12
Feed to 2. Further, the signal control circuit unit 112 supplies the clock signal CLKY and the vertical synchronization signal Vsync1 to the scanning line driving circuit 120. Also, the signal control circuit unit 1
12 denotes a polarity inversion signal FR and a clock signal CLK.
Y is supplied to the counter electrode drive circuit 124. The gray scale voltage circuit section 114 supplies a reference voltage to the data line drive circuit 122 as in the case of the gray scale voltage circuit section 14 described above. The power supply circuit unit 116 supplies power to each device for driving the liquid crystal device, similarly to the power supply circuit unit 16 described above.

Here, the vertical synchronization signal Vsync1 is 1
This signal is used to determine each subfield defined by dividing a field (one frame). The polarity inversion signal FR supplies a signal whose level has been inverted to the counter electrode driving circuit 124 for each subfield. Clock signal C
LKY is a signal for defining the horizontal scanning period S. The horizontal synchronization signal Hsync1 is a clock signal CLK.
X causes the data line drive circuit 122 to output one line of each R
This signal is output after the GB data signal Db is latched. Although not shown, the signal control circuit section 112 has a counter for counting the vertical synchronization signal Vsync1, and a signal supplied as the polarity inversion signal FR is determined based on the result of the counter.

Here, the concept of the subfield will be described below.

In this embodiment, for example, it is assumed that the liquid crystal device shown in FIG. 7 can display eight gradations. That is, the data signal Db is composed of three RGB bits. In such a liquid crystal device according to the present embodiment, the voltage applied to the liquid crystal layer is, for example, only two values of voltages V0 (“L” level) and V7 (“H” level). In the case of a normally white liquid crystal panel, the transmittance becomes 100% when a voltage V0 is applied to the liquid crystal layer over the entire period of one field, and the transmittance becomes 0% when a voltage V7 is applied.
Becomes Further, in one field, the voltage V is applied to the liquid crystal layer.
By controlling the ratio between the period in which 0 is applied and the period in which the voltage V7 is applied, a voltage corresponding to halftone can be applied to the liquid crystal layer. Therefore, one field f is divided into seven periods in order to separate the period in which the voltage V0 is applied to the liquid crystal layer from the period in which the voltage V7 is applied. The divided period, is defined as a subfield Sf ₁ ~Sf _7.

For example, when the gradation data is (001) (when gradation display is performed with a pixel transmittance of 14.3%), if the voltage of the counter electrode C is 0 V, the selected pixel is , the voltage V7 is applied in the sub-field Sf _1. On the other hand, in the other subfields Sf ₂ - SF _7, the voltage V0 is applied. Here, the effective voltage value is obtained by a square root obtained by averaging the square of the instantaneous voltage value over one cycle (one field). That is, subfield Sf ₁ is, if it is set so that with respect to one field f and (V1 / V7) ^2, the effective voltage applied to the liquid crystal layer in one field f becomes V1.

As described above, the subfields Sf _{1 to} Sf ₇
Is set, and a voltage corresponding to the gradation data is applied to the liquid crystal layer, so that only two voltages V0 and V7 are supplied to the liquid crystal layer. Key display becomes possible.

The signal control circuit 112 converts the supplied RGB 3-bit data signal into a binary signal Ds for each of the subfields Sf _{1 to} Sf ₇ . The binary signal Ds is supplied to the data line driving circuit 122, and one of the voltages V0 and V7 is applied to the liquid crystal layer as the data signal voltage Vd.

FIG. 8 shows voltage waveforms of gradation data (000) to (111) applied to the liquid crystal layer. Corresponding to each of the gradation data, the respective period of subfield Sf ₁ - SF _7, the voltage V7 ( "H") or the voltage V0
(“L”) is applied to the liquid crystal layer. For example, if the gradation data (001), in the order of the subfields Sf ₁ - SF _7, so that the (HLLLLLL) is applied to the liquid crystal layer.

FIG. 9 is a timing chart showing the operation of the liquid crystal device shown in FIG.

In each subfield, the scanning signal S
₁ period p which to S _M is supplied is set to be shorter than the subfield Sf ₃ which is set as the shortest subfield period.

In the subfield Sf ₁ , the data signal voltage + Vd is supplied to each of the data lines X _c (c is an odd number) during the selection period H ₁ during which the scanning signal S ₁ is supplied. A voltage −Vcom having a polarity opposite to the data signal voltage + Vd is supplied from the common electrode driving circuit 124 to the common electrode C ₁ a. At the same time, the data signal voltage -Vd is supplied to each of the data lines _Xd (d is an even number). A voltage + Vcom having a polarity opposite to the data signal voltage −Vd is supplied from the counter electrode driving circuit 124 to the counter electrode C _1b .

In the selection period H ₂ during which the scanning signal S ₂ is supplied, the data signal voltage −Vd is supplied to each of the data lines X _c (c is an odd number). A voltage + Vcom having a polarity opposite to the data signal voltage −Vd is supplied from the counter electrode driving circuit 124 to the counter electrode C _2a . At the same time, the data line X _d (d
(Even numbers) are supplied with the data signal voltage + Vd. A voltage −Vcom having a polarity opposite to the data signal voltage + Vd is supplied from the counter electrode drive circuit 124 to the counter electrode C _2b .

Similarly, the polarity of the counter electrode changes in synchronization with the selection period H _M during which the scanning signal S _M is supplied. Such an operation, in the frame period f, performed in subfield Sf ₁ ~Sf _7. In the frame period f _2, and the polarity of each pixel in the previous period frame periods f _1, different voltages are supplied to.

In driving the liquid crystal device as described above,
It is possible to suppress a change in the voltage applied to the liquid crystal layer due to a parasitic capacitance or the like, which occurs when the polarity of the counter electrode C is inverted by the polarity inversion signal FR in synchronization with the beginning of the frame period.

Further, conventionally, when the voltage of the common electrode is inverted, the frequency for driving the common electrode driving circuit 124 is proportionally increased because the frame period f is divided into a plurality of subfields. Become. However, in the present embodiment, since the counter electrodes C have a structure as shown in FIG. 5, each counter electrode can be driven when the corresponding scanning line is selected. Therefore, the frequency at which the common electrode is driven by the common electrode driving circuit 124 can be suppressed, and power consumption can be reduced.

In the above embodiment, the scanning line Y is set to 1
Although it was selected one by one, even when selecting and driving a plurality of scanning lines, by synchronizing with the selection period of the scanning line, by driving the counter electrode of each row corresponding to the selected scanning line,
Similar effects can be obtained.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-mentioned TFT type liquid crystal device, but is also applicable to an image display device using a plasma display device or the like.

The present invention can be applied to all electronic devices having a liquid crystal device. For example, various electronic devices such as a mobile phone, a game device, an electronic organizer, a personal computer, a word processor, a television, and a car navigation device are exemplified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a liquid crystal device according to a first embodiment.

FIG. 2 is a diagram illustrating an example of a configuration of a counter electrode driving circuit of the liquid crystal device of FIG. 1;

FIG. 3 is a diagram for explaining an operation of the counter electrode drive circuit of FIG. 2;

FIG. 4 is a diagram showing a timing chart of the operation of the liquid crystal device of FIG. 1;

FIG. 5A is a diagram showing pixels formed on an active matrix substrate. (B) is a diagram showing a counter electrode substrate used in the present invention.

FIG. 6 is a diagram showing a timing chart of the operation of the liquid crystal device according to the second embodiment.

FIG. 7 is a diagram illustrating a liquid crystal device according to a third embodiment.

8 is a diagram illustrating an example of a data signal Ds generated by a signal control circuit unit of the liquid crystal device in FIG.

9 is a diagram showing a timing chart of the operation of the liquid crystal device of FIG. 7;

FIG. 10 is a diagram showing a configuration of a conventional counter electrode substrate.

11 is a diagram showing a timing chart when the liquid crystal device is driven by dot inversion using the counter electrode substrate shown in FIG. 10;

12 is a diagram showing another timing chart when the liquid crystal device is driven by dot inversion using the counter electrode substrate shown in FIG. 10;

13 is a diagram showing a timing chart when the liquid crystal device is driven by source line inversion driving using the counter electrode substrate shown in FIG. 10;

FIG. 14 is a diagram illustrating a parasitic capacitance of a TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal panel 12, 112 Signal control circuit part 14, 114 Gray scale voltage circuit part 16, 116 Power supply circuit part 20, 120 Scan line drive circuit 22, 122 Data line drive circuit 24, 124 Counter electrode drive circuit 30 TFT 32 Pixel electrode Reference Signs List 40 pixel capacitance 42 holding capacitance 50, 52 shift register 54 shift register group 56 potential selection circuit unit 100, 110 opposing substrate 102 opposing pixel electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 624C 624 G02F 1/136 500 F term (Reference) 2H092 JA24 JB22 JB31 NA23 2H093 NA31 NA43 NA51 NC03 NC09 NC11 NC16 NC29 ND10 ND39 5C006 AA22 AB01 AC02 AC24 AC25 AC26 AF64 AF69 BB16 BC03 BC06 BC13 FA22 FA23 FA37 FA47 5C080 AA10 BB05 CC03 DD05 DD06 DD26 EE24 FF12 JJ02 JJ03 JJ04 KK02 KK43

Claims (8)

[Claims] 1. An M-row (M-row) arranged along a first direction.
Is an integer of 2 or more), N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction, and one of the M rows of scan lines. M × N switching means respectively connected to one of the N data lines; M × N pixel electrodes respectively connected to one of the M × N switching means; And M × N opposing pixel electrodes arranged to face each of the M × N pixel electrodes through the memory cell, and a scanning signal for selecting at least one of the M rows of scanning lines. Scanning line driving means for supplying a scanning line; data line driving means for supplying a data signal to each of the N columns of data lines; polarity inversion means for inverting the polarity of a voltage applied to the liquid crystal layer; A first arrangement of M rows arranged corresponding to each of the M rows of scanning lines. And a second wiring of M rows, and supplying a potential from each of the first wirings of the M rows to odd-numbered opposing pixel electrodes in each row corresponding to the M scanning lines; From each of the M rows of second wirings, a potential different from the potential supplied to the M rows of first wirings is applied to an even-numbered counter pixel electrode in each row corresponding to the M rows of scanning lines. The polarity inverting means includes a first wiring and a second wiring corresponding to the selected scanning line, synchronized by the scanning line driving means with a selection period for selecting the at least one scanning line. A liquid crystal device further comprising a means for changing a potential supplied to each of the wirings. 2. The wiring according to claim 1, wherein different ones of the first wirings in the M rows are supplied to adjacent wirings within a frame period. Liquid crystal devices. 3. The wiring according to claim 1, wherein the same wiring is supplied to adjacent wirings among the first wirings in the M rows in a frame period. Liquid crystal devices. 4. The first shift register according to claim 1, wherein the polarity inverting unit is supplied with an input signal of first logical information or second logical information and sequentially shifted, and An input signal having a logic opposite to that of the input signal supplied to the register is supplied, and the second shift register is sequentially shifted, and is supplied from the first and second shift registers every selection period. Based on the first logical information or the second logical information, a first wiring of the M rows and the M
A potential selection circuit for selecting a potential supplied to each of the second wirings in the row. 5. M rows (M) arranged along a first direction.
Is an integer of 2 or more), N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction, and one of the M rows of scan lines. M × N switching means respectively connected to one of the N data lines; M × N pixel electrodes respectively connected to one of the M × N switching means; And supplying an electric potential to odd-numbered opposing pixel electrodes in each of the M scanning lines, and M × N opposing pixel electrodes arranged to face each of the M × N pixel electrodes In each of the M rows of the first wirings and the M rows of the scanning lines, the M-th row of the M-th row supplies a potential different from the potential supplied to the odd-numbered counter pixel electrodes to the even-numbered counter pixel electrodes. A driving device for driving a liquid crystal display panel having two wirings, Scanning line driving means for supplying a scanning signal for selecting at least one of the lines to the M scanning lines; and the scanning line driving means for synchronizing with a selection period for selecting the at least one scanning line. And a polarity inversion means for changing a potential supplied to each of the first wiring and the second wiring corresponding to the selected scanning line. 6. An electronic apparatus comprising the liquid crystal device according to claim 1. 7. M rows (M rows) arranged along a first direction.
Is an integer of 2 or more), N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction, and one of the M rows of scan lines. An active matrix having M × N switching means respectively connected to one of the N columns of data lines, and M × N pixel electrodes respectively connected to one of the M × N switching means; A substrate facing a substrate with a liquid crystal layer interposed therebetween, and M × N counter pixel electrodes arranged to face each of the M × N pixel electrodes with the liquid crystal layer interposed therebetween; In each of the M scanning lines, a first wiring of M rows connecting odd-numbered counter pixel electrodes, and a first wiring of M rows connecting even-numbered counter pixel electrodes in each row of the M scanning lines. 2 lines, the first lines in the M rows and the second lines in the M rows. A substrate, wherein each of the lines is insulated from each other. 8. M rows (M rows) arranged along a first direction.
Is an integer of 2 or more), N (N is a natural number) columns of data lines arranged along a second direction intersecting the first direction, and one of the M rows of scan lines. M × N switching means respectively connected to one of the N data lines; M × N pixel electrodes respectively connected to one of the M × N switching means; And supplying an electric potential to odd-numbered opposing pixel electrodes in each of the M scanning lines, and M × N opposing pixel electrodes arranged to face each of the M × N pixel electrodes In each of the M rows of the first wirings and the M rows of the scanning lines, the M rows of the M rows that supply the even-numbered counter pixel electrodes with a potential different from the potential supplied to the odd-numbered counter pixel electrodes. A driving method for a liquid crystal device having two wirings, wherein at least the M scanning lines are provided. A scan signal for selecting one is supplied to the M rows of scan lines, and a first wiring corresponding to the selected scan line is synchronized with a selection period for selecting the at least one scan line. A driving method, wherein a potential supplied to each of the second wirings is changed.