JP2001350159A - Liquid crystal display device and manufacturing method thereof - Google Patents
Liquid crystal display device and manufacturing method thereofInfo
- Publication number
- JP2001350159A JP2001350159A JP2000174190A JP2000174190A JP2001350159A JP 2001350159 A JP2001350159 A JP 2001350159A JP 2000174190 A JP2000174190 A JP 2000174190A JP 2000174190 A JP2000174190 A JP 2000174190A JP 2001350159 A JP2001350159 A JP 2001350159A
- Authority
- JP
- Japan
- Prior art keywords
- film
- liquid crystal
- wiring
- alloy film
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】
【課題】Al配線の使用に際し、ヒロックを抑制し、透
明導電膜と良好な電気的接触が可能で、配線の断面の端
部の形状をテーパ状にし、簡易な工程で製造歩留まりの
高い液晶表示装置の提供。
【解決手段】液晶表示装置で、一対の基板のすくなくと
も一方の上に配置した電極群は、少なくとも複数のゲー
ト配線と、複数のゲート配線に交差するように形成され
た複数のデータ配線とにより構成され、複数のゲート配
線と複数のデータ配線のそれぞれの交点に対応して薄膜
トランジスタが配置され、ゲート配線とデータ配線の少
なくとも一方は、Al合金膜と前記Al合金膜上にAl
以外の金属種の上層膜を有する積層配線で構成され、積
層配線を覆う絶縁膜に形成したコンタクトホールを介し
てAl合金膜と透明導電膜が接続された構成であり、A
l合金膜中の添加元素の濃度分布は、Al合金膜の内層
部より表層部において高いという構成。
(57) [Summary] When using Al wiring, hillocks are suppressed, good electrical contact with the transparent conductive film is possible, and the shape of the end of the cross section of the wiring is tapered, and a simple process is used. Provide liquid crystal display devices with high production yield. In a liquid crystal display device, an electrode group arranged on at least one of a pair of substrates includes at least a plurality of gate wirings and a plurality of data wirings formed so as to intersect the plurality of gate wirings. A thin film transistor is disposed at each intersection of the plurality of gate lines and the plurality of data lines, and at least one of the gate line and the data line includes an Al alloy film and an Al film on the Al alloy film.
And a transparent conductive film formed by connecting an Al alloy film and a transparent conductive film through a contact hole formed in an insulating film covering the stacked wiring.
The structure in which the concentration distribution of the additional element in the 1 alloy film is higher in the surface layer portion than in the inner layer portion of the Al alloy film.
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は薄膜トランジスタ
(TFT)によって駆動するアクティブマトリクス型液
晶表示装置(TFT−LCD)及びその製造方法に関す
る。The present invention relates to an active matrix type liquid crystal display (TFT-LCD) driven by a thin film transistor (TFT) and a method of manufacturing the same.
【0002】[0002]
【従来の技術】薄型化・軽量化・高精細化が図れる画像
表示装置として、従来のブラウン管に比べ、薄膜トラン
ジスタ駆動液晶表示装置(TFT−LCD)の市場が拡
大している。TFT−LCDとは、ガラス基板上に形成
したゲート配線,ゲート絶縁膜,データ配線,ゲート配
線とデータ配線の交点付近に作製された薄膜トランジス
タ,絶縁性保護膜,薄膜トランジスタに接続された透明
電極と、対向基板と、前記ガラス基板と対向基板との間
に狭持された液晶層などから構成されている。2. Description of the Related Art The market for a thin film transistor driven liquid crystal display (TFT-LCD) has been expanding as an image display device which can be made thinner, lighter and more precise than a conventional cathode ray tube. The TFT-LCD includes a gate wiring formed on a glass substrate, a gate insulating film, a data wiring, a thin film transistor formed near an intersection of the gate wiring and the data wiring, an insulating protective film, and a transparent electrode connected to the thin film transistor; It comprises a counter substrate and a liquid crystal layer sandwiched between the glass substrate and the counter substrate.
【0003】近年、TFT−LCDの画面の大型化,高
精細化が進行するにつれ、配線材料の性能に対する低抵
抗,低応力,加工性といった要請は厳しくなりつつあ
る。そこで低抵抗,低応力であるAlが主たる配線材料
として使用されている。しかしながら、Alは、耐熱性
に欠け加熱により表面にヒロックが発生することや透明
導電膜(例えばITO:Indium-Tin-Oxide)との電気的
接触が粗悪であるという問題がある。In recent years, as the size of a TFT-LCD screen has increased and the definition has increased, the demands on the performance of wiring materials, such as low resistance, low stress, and workability, have been increasing. Therefore, Al having low resistance and low stress is used as a main wiring material. However, Al lacks heat resistance and has a problem that hillocks are generated on the surface by heating and that electrical contact with a transparent conductive film (for example, ITO: Indium-Tin-Oxide) is poor.
【0004】これらの問題を解決する方法として、Al
膜の上層に透明導電膜との電気的接触性の良いMoを積
層し、Alの引張応力をMoの圧縮応力で緩和させるこ
とによりヒロックを抑制する方法(特開平11−745
37号公報)、Al配線表面を透明導電膜との電気的接
触性の良い高融点金属にて被覆するクラッド構造をとる
方法(例えば特開平6−120503号公報),Alそ
のものの耐熱性をあげるためにAlを合金化する方法
(特開平7−45555号公報)に加え、透明導電膜と
の電気的接続性の良いMo合金を上層として積層させる
方法(例えば特開平4−20930号公報)がある。As a method for solving these problems, Al
A method for suppressing hillocks by laminating Mo having good electrical contact with the transparent conductive film on the film and relaxing the tensile stress of Al by the compressive stress of Mo (Japanese Patent Laid-Open No. 11-745).
No. 37), a method of forming a clad structure in which the surface of an Al wiring is coated with a high melting point metal having good electrical contact with a transparent conductive film (for example, JP-A-6-120503), to improve the heat resistance of Al itself. For this purpose, in addition to a method of alloying Al (Japanese Patent Application Laid-Open No. 7-45555), a method of laminating a Mo alloy having good electrical connectivity with a transparent conductive film as an upper layer (for example, Japanese Patent Application Laid-Open No. Hei 4-20930). is there.
【0005】[0005]
【発明が解決しようとする課題】Alを配線に使用する
場合、Alのヒロック生成を抑制し、透明導電膜との電
気的接触を低くとることの他、絶縁膜のカバレッジを良
好にし生産歩留を上げるため、配線の断面端部形状をテ
ーパ状とすること、工程の簡略化,プロセスマージンの
確保が強く望まれる。When Al is used for wiring, hillock formation of Al is suppressed, electrical contact with the transparent conductive film is reduced, and the coverage of the insulating film is improved to improve the production yield. Therefore, it is strongly desired that the cross-sectional end of the wiring be tapered, the process be simplified, and a process margin be ensured.
【0006】しかしながら、従来技術であげたこれらの
方法でAlをTFT−LCDに適用する際、それぞれ、
特有の問題をもつ。However, when Al is applied to a TFT-LCD by these methods described in the prior art,
It has unique problems.
【0007】Al膜の上層に透明導電膜との電気的接触
性の良いMoを積層し、Alの引張応力をMoの圧縮応
力で緩和させることによりヒロックを抑制する方法で
は、Alの応力特性を緩和するために十分な厚膜の上層
Moを必要とする。しかしながら、上層を厚膜化するこ
とにより、配線全体が厚膜化し、さらに配線の上層Mo
の断面形状をテーパ制御することが困難であるため、配
線を覆う絶縁膜のカバレッジが低下し、ひいてはそれに
起因した配線ショートの発生頻度が増し、生産歩留が低
下する。In a method in which Mo having good electrical contact with the transparent conductive film is laminated on the Al film and the tensile stress of Al is relaxed by the compressive stress of Mo, the hillock is suppressed. It requires a sufficiently thick upper layer Mo to relax. However, by increasing the thickness of the upper layer, the thickness of the entire wiring is increased, and the upper layer Mo of the wiring is further increased.
Since it is difficult to control the cross-sectional shape of the wiring, the coverage of the insulating film covering the wiring is reduced, and as a result, the frequency of short-circuiting of the wiring is increased, and the production yield is reduced.
【0008】Al配線表面を透明導電膜との電気的接触
性の良い高融点金属にて被覆するクラッド構造をとる方
法では、Al配線パターン形成後に上層高融点金属膜を
形成するためのホトリソグラフィが1回増えるので工程
が複雑になり生産性が低下する。In a method of forming a clad structure in which the surface of an Al wiring is covered with a refractory metal having good electrical contact with a transparent conductive film, photolithography for forming an upper refractory metal film after forming an Al wiring pattern is performed. Since it increases once, the process becomes complicated and productivity decreases.
【0009】Alそのものの耐熱性をあげるためにAl
を合金化する方法に加え、透明導電膜との電気的接続性
の良いMo合金を上層として積層させる方法は、配線を
覆う絶縁膜のコンタクトホール(絶縁膜に他配線または
電極と電気的な接続をするために空ける穴:以下コンタ
クトホールと呼ぶ)をドライエッチングで形成するため
に上層Mo合金にドライエッチング耐性を必要とし、上
層MoへのCr添加、または上層の厚膜化によりドライ
エッチング耐性を確保する必要がある。しかし、上層M
o合金へCr添加する方法では、Mo合金のエッチング
レートが低下するため配線断面を良好なテーパ形状に制
御することが非常に困難となる。また良好なテーパ形状
が得られる最適条件を見出したとしても、やはりそのプ
ロセスマージンは狭く、大型基板で面内均一に形状を維
持するのが困難であり、そのため、配線ショート等の発
生頻度が増し、生産歩留が低下する。また、厚膜化は先
に述べた理由で同様に生産歩留が低下する。In order to improve the heat resistance of Al itself,
In addition to the method of alloying, a method of laminating a Mo alloy having a good electrical connection with the transparent conductive film as an upper layer is performed by using a contact hole of an insulating film covering the wiring (the insulating film is electrically connected to another wiring or an electrode. The upper Mo alloy must have dry etching resistance in order to form a hole to be formed by performing dry etching (hereinafter referred to as a contact hole), and the dry etching resistance is increased by adding Cr to the upper Mo or increasing the thickness of the upper layer. Need to secure. However, the upper layer M
In the method of adding Cr to the o-alloy, the etching rate of the Mo alloy is reduced, so that it is very difficult to control the cross section of the wiring to a favorable taper shape. Even if the optimum conditions for obtaining a good taper shape are found, the process margin is still narrow, and it is difficult to maintain a uniform shape on the surface of a large-sized substrate. As a result, the production yield decreases. Also, increasing the film thickness similarly lowers the production yield for the reasons described above.
【0010】本発明の目的は、Al配線の使用に際し、
ヒロックを抑制し、透明導電膜と良好な電気的接触が可
能で、配線の断面の端部の形状をテーパ状にし、簡易な
工程で製造歩留まりの高い液晶表示装置を提供すること
にある。[0010] An object of the present invention is to provide a method for using Al wiring,
It is an object of the present invention to provide a liquid crystal display device which can suppress hillocks, make good electrical contact with a transparent conductive film, taper the shape of a cross-sectional end of a wiring, and have a high production yield in a simple process.
【0011】[0011]
【課題を解決するための手段】本発明の一つの実施態様
によれば、少なくとも一方が透明な一対の基板と、一対
の基板間に挟持された液晶層と、一対の基板の少なくと
も一方の上に配置した電極群とを有し、電極群により液
晶層の液晶を動かして表示を制御する液晶表示装置で、
一対の基板上に配置した電極群は、少なくとも複数のゲ
ート配線と、複数のゲート配線に交差するように形成さ
れた複数のデータ配線とにより構成され、複数のゲート
配線と複数のデータ配線のそれぞれの交点に対応して薄
膜トランジスタが配置され、ゲート配線とデータ配線の
少なくとも一方は、Al合金膜と前記Al合金膜上にA
l以外の金属種の上層膜を有する積層配線で構成され、
積層配線を覆う絶縁膜に形成したコンタクトホールを介
してAl合金膜と透明導電膜が接続された構成であり、
Al合金膜中の添加元素の濃度分布は、Al合金膜の内
層部より表層部において高いというものである。According to one embodiment of the present invention, at least one of a pair of transparent substrates, a liquid crystal layer sandwiched between the pair of substrates, and at least one of the pair of substrates. A liquid crystal display device having an electrode group arranged in the liquid crystal layer and controlling display by moving liquid crystal of a liquid crystal layer by the electrode group.
The electrode group arranged on the pair of substrates includes at least a plurality of gate wirings and a plurality of data wirings formed so as to intersect the plurality of gate wirings. Each of the plurality of gate wirings and the plurality of data wirings A thin film transistor is arranged corresponding to the intersection of the gate wiring and the data wiring, and at least one of the gate wiring and the data wiring is formed on the Al alloy film and the A
a stacked wiring having an upper layer film of a metal type other than l.
A structure in which the Al alloy film and the transparent conductive film are connected via a contact hole formed in the insulating film covering the stacked wiring,
The concentration distribution of the additive element in the Al alloy film is higher in the surface layer than in the inner layer of the Al alloy film.
【0012】これによりAlを配線材料として使用する
際、ヒロックを抑制し、Al合金膜中の表層部での酸化
を防ぐため、Al配線と透明導電膜と良好な電気的接触
が可能な液晶表示装置を提供することができるというも
のである。Thus, when Al is used as a wiring material, hillocks are suppressed and oxidation at the surface layer portion of the Al alloy film is prevented, so that a liquid crystal display capable of making good electrical contact between the Al wiring and the transparent conductive film. An apparatus can be provided.
【0013】また、Al合金膜に添加される元素の濃度
を調整することにより、Al合金膜中の表層部での添加
元素の濃度分布をより高めることができるというもので
ある。これにより、Al合金膜の表層部での酸化をより
防ぐことができ、Al合金膜と透明導電膜との電気的接
触がより良好になるというものである。Further, by adjusting the concentration of the element added to the Al alloy film, the concentration distribution of the added element in the surface layer portion in the Al alloy film can be further improved. As a result, oxidation of the Al alloy film in the surface layer portion can be further prevented, and the electrical contact between the Al alloy film and the transparent conductive film becomes better.
【0014】また、積層配線の上層膜の膜厚を50nm
以下とし、さらにAl合金膜の断面の端部の形状をテー
パ状とすることにより、積層配線を覆う絶縁膜のカバレ
ッジが向上し、配線ショートの不良がより少なくするこ
とができる。Further, the thickness of the upper layer film of the laminated wiring is set to 50 nm.
By making the shape of the end of the cross section of the Al alloy film tapered, the coverage of the insulating film covering the laminated wiring is improved, and the short-circuit failure can be further reduced.
【0015】さらに、上層膜がMoを主成分とする合金
とする。これにより、Al合金膜と上層膜が一括エッチ
ング可能となり、より簡略な工程となる。Further, the upper layer film is made of an alloy containing Mo as a main component. Thereby, the Al alloy film and the upper layer film can be collectively etched, and the process becomes simpler.
【0016】さらに、積層配線はAl合金膜の下に他金
属種の下層膜を有する積層配線とする。これによりAl
合金配線と半導体層との電気的接続がより良くなる。Further, the laminated wiring is a laminated wiring having a lower layer film of another metal type under the Al alloy film. This allows Al
The electrical connection between the alloy wiring and the semiconductor layer is improved.
【0017】本発明の別の実施態様によれば、少なくと
も一方が透明な一対の基板と、一対の基板間に挟持され
た液晶層と、一対の基板の少なくとも一方の上に配置し
た電極群とを有し、電極群により液晶層の液晶を動かし
て表示を制御する液晶表示装置で、一対の基板上に配置
した電極群は、少なくとも複数のゲート配線と、複数の
ゲート配線に交差するように形成された複数のデータ配
線とにより構成され、複数のゲート配線と複数のデータ
配線のそれぞれの交点に対応して薄膜トランジスタが配
置され、ゲート配線の上部には絶縁膜を介して半導体層
を形成し、データ配線,ドレイン電極及びソース電極
は、Al合金膜とAl合金膜上にAl以外の金属種の上
層膜を有する積層配線で構成されており、積層配線を覆
う絶縁膜に形成したコンタクトホールを介してAl合金
膜と透明導電膜が接続されており、Al合金膜中の添加
元素の濃度分布が、Al合金膜の内層部より表層部にお
いて高いという構成である。According to another embodiment of the present invention, at least one of a pair of transparent substrates, a liquid crystal layer sandwiched between the pair of substrates, and an electrode group disposed on at least one of the pair of substrates. In a liquid crystal display device which controls display by moving liquid crystal of a liquid crystal layer by an electrode group, an electrode group arranged on a pair of substrates is provided so as to intersect at least a plurality of gate wirings and a plurality of gate wirings. A thin film transistor is formed corresponding to each intersection of the plurality of gate lines and the plurality of data lines, and a semiconductor layer is formed above the gate line via an insulating film. The data wiring, the drain electrode, and the source electrode are composed of an Al alloy film and a laminated wiring having an upper layer film of a metal species other than Al on the Al alloy film, and are formed on an insulating film covering the laminated wiring. Emissions and tact via hole Al alloy film and the transparent conductive film is connected, the concentration distribution of the additive element in the Al alloy film, a configuration that higher in the surface layer portion than the inner layer portion of the Al alloy film.
【0018】[0018]
【発明の実施の形態】本発明による様々な実施態様につ
いて実施例により説明する。 (実施例1)本実施例は、Al合金膜と上層膜との二層
積層膜を液晶表示装置のゲート配線、Al合金膜と上層
膜と下層膜との三層積層膜をデータ配線に適用して、ゲ
ート配線およびデータ配線と透明導電膜との電気的接触
と、ゲート配線とデータ配線との間の絶縁特性を評価し
た例である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments according to the present invention will be described by way of examples. (Embodiment 1) In this embodiment, a two-layer laminated film of an Al alloy film and an upper film is applied to a gate wiring of a liquid crystal display device, and a three-layer laminated film of an Al alloy film, an upper film and a lower film is applied to data wiring. In this example, the electrical contact between the gate wiring and the data wiring and the transparent conductive film and the insulation properties between the gate wiring and the data wiring were evaluated.
【0019】図1は液晶表示装置の概略を示す平面図で
ある。画素部30に対し、ゲート配線1に繋がるゲート
配線端子群31とデータ配線2に繋がるデータ配線端子
群32が図のように配置される。FIG. 1 is a plan view schematically showing a liquid crystal display device. In the pixel section 30, a group of gate wiring terminals 31 connected to the gate wiring 1 and a group of data wiring terminals 32 connected to the data wiring 2 are arranged as shown in the figure.
【0020】図2(a)はゲート配線1とデータ配線2
の交差付近にある薄膜トランジスタと、図2(b)はゲ
ート配線端子取りだし部の断面図である。その作製方法
を以下に示す。FIG. 2A shows a gate wiring 1 and a data wiring 2.
2B is a cross-sectional view of the thin film transistor near the intersection of FIG. The manufacturing method is described below.
【0021】DCスパッタ法によりガラス基板10上
に、Al合金膜101としてAl−2at%Ndを、上
層膜102としてMoを連続して堆積した。基板温度は
120℃とした。続いてホトリソグラフィにより積層膜
上にレジストパターンを形成し、りん酸,硝酸,酢酸,
純水の混合液によりAl合金膜101と上層膜102を
エッチングして、ゲート配線1を形成した。On a glass substrate 10, Al-2 at% Nd as an Al alloy film 101 and Mo as an upper film 102 were successively deposited on a glass substrate 10 by DC sputtering. The substrate temperature was 120 ° C. Subsequently, a resist pattern is formed on the laminated film by photolithography, and phosphoric acid, nitric acid, acetic acid,
The gate wiring 1 was formed by etching the Al alloy film 101 and the upper film 102 with a mixed solution of pure water.
【0022】次に、プラズマCVD装置にて、基板温度
300℃でゲート絶縁膜5としてSiNと、半導体層6
として非晶質Siと、n+ 半導体層7としてPをドープ
した非晶質Siを連続して堆積した。続いてホトリソグ
ラフィによりレジストパターンを形成し、半導体層6と
n+ 半導体層7をドライエッチングして島状に加工し
た。Next, at a substrate temperature of 300 ° C., SiN as a gate insulating film 5 and a semiconductor layer
, Amorphous silicon doped with P as the n + semiconductor layer 7 was continuously deposited. Subsequently, a resist pattern was formed by photolithography, and the semiconductor layer 6 and the n + semiconductor layer 7 were processed into an island shape by dry etching.
【0023】次に、DCスパッタ法により下層膜30
3,403としてMoを、Al合金膜301,401と
してAl−2at%Ndを、上層膜302,402とし
てMoを連続して堆積した。基板温度は120℃とし
た。ホトリソグラフィにより積層膜上によりレジストパ
ターンを形成し、りん酸,硝酸,酢酸,純水の混合液に
て下層膜303,403,Al合金膜301,401,
上層膜302,402をエッチングし、データ配線2,
ソース電極3,ドレイン電極4を形成した。さらに、n
+ 半導体層7をドライエッチングした。Next, the lower film 30 is formed by DC sputtering.
Mo was continuously deposited as 3,403, Al-2 at% Nd as Al alloy films 301 and 401, and Mo as upper films 302 and 402. The substrate temperature was 120 ° C. A resist pattern is formed on the laminated film by photolithography, and the lower films 303 and 403, the Al alloy films 301 and 401, and the mixed solution of phosphoric acid, nitric acid, acetic acid and pure water are used.
The upper layers 302 and 402 are etched to form data wirings 2 and 2.
Source electrode 3 and drain electrode 4 were formed. Furthermore, n
+ The semiconductor layer 7 was dry-etched.
【0024】さらに、プラズマCVD装置にて、基板温
度250℃で保護膜8としてSiNを堆積した。ホトリ
ソグラフィによりレジストパターンを形成し、ゲート配
線端子部のコンタクトホール21ではゲート絶縁膜5と
保護膜8と上層膜102を、薄膜トランジスタ部のコン
タクトホール20では保護膜8,上層膜302,402を
ドライエッチングした。ドライエッチング後は純水にて
充分に洗浄した。Further, SiN was deposited as a protective film 8 at a substrate temperature of 250 ° C. by a plasma CVD apparatus. A resist pattern is formed by photolithography, and the gate insulating film 5, the protective film 8 and the upper film 102 are dried in the contact hole 21 of the gate wiring terminal portion, and the protective film 8, the upper film 302 and 402 are dried in the contact hole 20 of the thin film transistor portion. Etched. After the dry etching, the substrate was sufficiently washed with pure water.
【0025】この後、DCスパッタ装置にて、透明導電
膜9としてITOを基板温度215℃で堆積した。ホト
リソグラフィによりレジストパターンを形成しITOを
エッチングして透明導電膜9を形成した。以上の工程に
より、液晶表示装置のTFTが作製された。Thereafter, ITO was deposited as a transparent conductive film 9 at a substrate temperature of 215 ° C. by a DC sputtering apparatus. A resist pattern was formed by photolithography, and the ITO was etched to form a transparent conductive film 9. Through the above steps, a TFT for a liquid crystal display device was manufactured.
【0026】表1は、ゲート配線の上層膜の膜厚をパラ
メータとして作製した液晶表示パネルに対して、ゲート
配線とデータ配線のAl合金配線膜と透明導電膜との電
気的接触の有無と、ゲート配線とデータ配線との間の絶
縁特性を調べた結果を示す。Table 1 shows whether or not there is electrical contact between the Al alloy wiring film of the gate wiring and the data wiring and the transparent conductive film for the liquid crystal display panel manufactured using the thickness of the upper layer film of the gate wiring as a parameter. 4 shows the result of examining the insulation characteristics between a gate wiring and a data wiring.
【0027】[0027]
【表1】 [Table 1]
【0028】Al合金膜と透明導電膜との電気的接触は
膜厚に関係なく一定の低い値が得られた。膜厚は上層膜
が100nm以上である場合ショートパネル数が非常に
多くゲート絶縁膜のカバレッジが悪いことが分かる。上
層膜の膜厚範囲は50nm以下、好ましくは20nmが
良い。また、上層膜がない場合は、Al合金膜と透明導
電膜との電気的接続は不可能であった。A constant low value was obtained for the electrical contact between the Al alloy film and the transparent conductive film regardless of the film thickness. It can be seen that when the thickness of the upper layer is 100 nm or more, the number of short panels is very large and the coverage of the gate insulating film is poor. The thickness range of the upper layer film is 50 nm or less, preferably 20 nm. Also, when there was no upper layer film, electrical connection between the Al alloy film and the transparent conductive film was impossible.
【0029】本実施例ではMoを上層膜としたが、上層
膜を他の高融点金属とした場合も同様の結果が得られ
た。In this embodiment, Mo is used as the upper layer film. However, similar results were obtained when the upper layer film was made of another refractory metal.
【0030】また、本実施例では、Al合金膜をAl−
2at%Ndとしたが、NdはAlに対する固溶限が
0.01at% と非常に小さい元素である。同様にAl
に対する固溶限の小さい元素であるY,La,Ce,P
r,Sm,Eu,Gd,Tb,Dy,Ho,Er,T
m,Yb,Luを添加したAl合金膜を採用した場合に
も本実施例と同様の結果が得られた。 (実施例2)本実施例は、実施例1で作製した液晶表示
装置のAl合金膜(Al−2at%Nd)と透明導電膜
(ITO)が電気的接触をする図2のコンタクトホール
20において、Al合金膜401と透明導電膜9が直接
接触している部分を深さ方向にオージェ電子分光法にて
組成分析をした結果を図3(a)に、また積層配線を純
Alにして同様に作製した液晶表示装置のコンタクトホ
ールにおいて、Al膜と透明導電膜が直接接触している
部分を深さ方向にオージェ電子分光法にて組成分析をし
た結果を図3(b)に示す。In this embodiment, the Al alloy film is
Although 2 at% Nd was used, Nd is an element whose solid solubility limit with respect to Al is as small as 0.01 at%. Similarly, Al
, La, Ce, P, which are elements having a small solid solubility limit for
r, Sm, Eu, Gd, Tb, Dy, Ho, Er, T
The same results as in this example were obtained when an Al alloy film to which m, Yb, and Lu were added was employed. (Embodiment 2) In the present embodiment, the contact hole 20 of FIG. 2 where the Al alloy film (Al-2 at% Nd) and the transparent conductive film (ITO) of the liquid crystal display device manufactured in Embodiment 1 make electrical contact. FIG. 3 (a) shows the result of composition analysis of the portion where the Al alloy film 401 and the transparent conductive film 9 are in direct contact by Auger electron spectroscopy in the depth direction. FIG. 3 (b) shows the result of composition analysis by Auger electron spectroscopy in the depth direction of the portion where the Al film and the transparent conductive film are in direct contact in the contact hole of the liquid crystal display device manufactured in FIG.
【0031】図3(a)では透明導電膜の構成元素であ
るIn,OがAl合金膜界面において濃度が低くなり、
替わりにAl合金膜の構成元素であるAl,Ndが検出
され、表層部において濃度の高い領域が存在する。ま
た、上層膜に用いたMoは検出されなかったが、これ
は、コンタクトホールを形成するドライエッチング時に
除去されたと考えられる。図3(b)では図中の破線と
破線の間の領域で酸素の濃度が高くなり、またAl膜の
表面近傍で酸素が検出され、これはAl酸化膜(アルミ
ナ)である。以上から次のことがいえる。In FIG. 3A, the concentrations of In and O, which are constituent elements of the transparent conductive film, decrease at the interface of the Al alloy film.
Instead, Al and Nd, which are constituent elements of the Al alloy film, are detected, and a high concentration region exists in the surface layer. Further, although Mo used for the upper layer film was not detected, it is considered that this was removed during dry etching for forming a contact hole. In FIG. 3B, the oxygen concentration is high in the region between the broken lines in the figure, and oxygen is detected near the surface of the Al film, which is an Al oxide film (alumina). From the above, the following can be said.
【0032】まず、後述する図6(a)の構成は、Al
合金膜への酸素の分布が非常に少なく、Al合金膜の添
加元素であるNdの濃度が高い表層部でITOと接触し
ている構成である。図6(b)の構成は、Al合金膜と
ITOとの接触部に高い絶縁性を持つAl酸化膜(アル
ミナ)があるという構成である。First, the structure shown in FIG.
The configuration is such that the distribution of oxygen in the alloy film is very small, and the surface layer portion where the concentration of Nd as an additive element of the Al alloy film is high is in contact with ITO. The configuration shown in FIG. 6B is a configuration in which a contact portion between the Al alloy film and the ITO has an Al oxide film (alumina) having a high insulating property.
【0033】図6(a)のNdの濃度分布が高い表層部
が、Al合金膜の酸化を防止しているため、Al合金膜
と透明導電膜との電気的接続が可能であると推察され
る。また、図6(b)のAl酸化膜(アルミナ)はコン
タクトホール21を形成後、装置から大気中へ出した時
に自然酸化膜として形成されたか、または、酸化物であ
るITOとAl膜を積層することによりITOの酸素が
Al膜側に拡散したものと推察される。いずれにしても
Al膜表面に酸化を防止する層がないためにAl膜と透
明導電膜との電気的接触が不可能であると推察される。Since the surface layer portion having a high Nd concentration distribution in FIG. 6A prevents oxidation of the Al alloy film, it is presumed that electrical connection between the Al alloy film and the transparent conductive film is possible. You. The Al oxide film (alumina) in FIG. 6B is formed as a natural oxide film when the contact hole 21 is formed and the device is brought into the atmosphere after the contact hole 21 is formed, or an ITO oxide and an Al film are laminated. It is presumed that oxygen in the ITO diffused toward the Al film side. In any case, it is inferred that electrical contact between the Al film and the transparent conductive film is impossible because there is no layer for preventing oxidation on the surface of the Al film.
【0034】更に、実施例1で作製したAl合金配線の
断面を透過電子顕微鏡により断面観察をし、Al合金膜
と上層膜との界面について組成分析をした。図4は、図
2(a)におけるAの領域を拡大して透過電子顕微鏡で
観察した結果の概略図である。図中の黒丸と丸の中の数
字はエネルギ分散型X線分析での観察ポイントとポイン
ト番号であり、表2に元素分析結果を示す。Further, the cross section of the Al alloy wiring prepared in Example 1 was observed with a transmission electron microscope, and the composition of the interface between the Al alloy film and the upper layer film was analyzed. FIG. 4 is a schematic diagram showing the result of enlarging the region A in FIG. 2A and observing it with a transmission electron microscope. In the figure, black circles and numbers in the circles represent observation points and point numbers in energy dispersive X-ray analysis, and Table 2 shows the results of elemental analysis.
【0035】[0035]
【表2】 [Table 2]
【0036】この結果は、固溶限以上にNd元素を添加
されたAl合金膜は、Ndの濃度分布が内層部で低く、
表層部33で高い領域をもつという図3のオージェ電子
分光法の分析結果を支持するものである。 (実施例3)本実施例では、Al合金膜と透明導電膜と
の電気的接触を、Al合金膜を被覆する絶縁膜の堆積時
の基板温度をパラメータとして調べた例である。This result indicates that the Al alloy film to which the Nd element is added in excess of the solid solubility limit has a low Nd concentration distribution in the inner layer,
It supports the analysis result of Auger electron spectroscopy in FIG. 3 that the surface layer portion 33 has a high area. (Embodiment 3) In this embodiment, the electrical contact between the Al alloy film and the transparent conductive film is examined using the substrate temperature at the time of deposition of the insulating film covering the Al alloy film as a parameter.
【0037】図5は、Al合金配線50と透明導電膜5
2との電気的接触の検討をする配線パターンの平面の概
略図である。4ヶ所の電極パット53を使い、四端子針
法にてコンタクトホール54部分での電気的接触を評価
した。FIG. 5 shows the Al alloy wiring 50 and the transparent conductive film 5.
FIG. 4 is a schematic plan view of a wiring pattern for examining electrical contact with the wiring pattern 2; Using four electrode pads 53, electrical contact at the contact hole 54 was evaluated by a four-terminal needle method.
【0038】図6(a),(b)は、図5のA−A′に
おけるコンタクトホール54での断面の概略図である。
図6(a)は、Al合金配線が上層膜とAl合金膜の積
層である場合、図6(b)はAl合金配線がAl合金膜
の単層である場合である。以下にその作製方法を示す。FIGS. 6A and 6B are schematic views of a cross section taken along the line AA 'in FIG.
FIG. 6A shows the case where the Al alloy wiring is a laminate of the upper layer film and the Al alloy film, and FIG. 6B shows the case where the Al alloy wiring is a single layer of the Al alloy film. The manufacturing method is described below.
【0039】DCスパッタ法により、ガラス基板55上
に、Al合金膜501としてAl−2at%Ndを堆積
した。積層膜の場合、更に連続して、上層膜502とし
てMoを連続して堆積した。基板温度は120℃とし
た。続いてホトリソグラフィにより積層膜上にレジスト
パターンを形成し、りん酸,硝酸,酢酸,純水の混合液
によりAl合金膜501をエッチングして、Al合金配
線50を形成した。積層膜では上層膜502もエッチン
グした。次に、プラズマCVD装置にて、絶縁膜51と
してSiNを堆積した。ここで、絶縁膜を堆積する基板
温度をパラメータとした。続いてホトリソグラフィによ
りレジストパターンを形成し絶縁膜51をドライエッチ
ングしてコンタクトホール54を形成した。積層配線の
場合、絶縁膜51と上層膜502をドライエッチングし
た。この後、DCスパッタ装置にて、透明導電膜52と
してITOを基板温度215℃で堆積した。続いてホト
リソグラフィによりレジストパターンを形成しITOを
エッチングして透明導電膜52を形成した。Al-2 at% Nd was deposited as an Al alloy film 501 on the glass substrate 55 by DC sputtering. In the case of a laminated film, Mo was further continuously deposited as the upper layer film 502. The substrate temperature was 120 ° C. Subsequently, a resist pattern was formed on the laminated film by photolithography, and the Al alloy film 501 was etched with a mixed solution of phosphoric acid, nitric acid, acetic acid, and pure water to form an Al alloy wiring 50. In the laminated film, the upper film 502 was also etched. Next, SiN was deposited as an insulating film 51 by a plasma CVD apparatus. Here, the substrate temperature for depositing the insulating film was used as a parameter. Subsequently, a resist pattern was formed by photolithography, and the insulating film 51 was dry-etched to form a contact hole. In the case of a stacked wiring, the insulating film 51 and the upper film 502 were dry-etched. Thereafter, ITO was deposited as a transparent conductive film 52 at a substrate temperature of 215 ° C. by a DC sputtering apparatus. Subsequently, a resist pattern was formed by photolithography, and the ITO was etched to form a transparent conductive film 52.
【0040】表3に結果を示す。表中の、×は不可、○
は良、◎は極めて良の意味である。Table 3 shows the results. In the table, × is not allowed, ○
Means good, and ◎ means very good.
【0041】[0041]
【表3】 [Table 3]
【0042】Al合金配線が単層の場合、どの絶縁膜堆
積時の基板温度でも透明導電膜との接触が不可能であっ
た。これは、実施例2でも記述したように、Al合金膜
を堆積後に装置から大気中へ出すだけでAl膜表面には
絶縁物である緻密なAl酸化膜(アルミナ)が形成され
るためと推察される。このことは実施例1の結果にも表
れている。When the Al alloy wiring was a single layer, contact with the transparent conductive film was impossible at any substrate temperature at the time of depositing any insulating film. This is presumably because, as described in the second embodiment, a dense Al oxide film (alumina), which is an insulator, is formed on the surface of the Al film simply by putting the Al alloy film out of the apparatus after the deposition, and then putting the film into the atmosphere. Is done. This is also shown in the results of Example 1.
【0043】Al合金配線が積層の場合において、絶縁
膜堆積時の基板温度が200℃以上、好ましくは250
℃以上、でAl合金膜と透明導電膜との電気的接触が可
能になる。これは、連続して堆積した上層膜のために酸
化されないAl合金膜の表面において、絶縁膜堆積時の
基板加熱によりAl合金膜中の添加元素の濃度分布が表
層部で高くなり、これが酸化防止のバリアとなって、上
層膜がコンタクトホール形成時に除去されても、酸化さ
れ難いと推察される。また、絶縁膜堆積時の基板温度が
高いと、Al合金膜中の添加元素が表層部に移動し易く
なるため、添加元素の濃度が表層部で更に高くなり、更
に酸化されにくくなると推察される。When the Al alloy wiring is laminated, the substrate temperature at the time of depositing the insulating film is 200 ° C. or more, preferably 250 ° C.
At a temperature equal to or higher than 0 ° C., electrical contact between the Al alloy film and the transparent conductive film becomes possible. This is because, on the surface of the Al alloy film that is not oxidized because of the continuously deposited upper layer film, the concentration distribution of the added element in the Al alloy film is increased in the surface layer due to the heating of the substrate during the deposition of the insulating film. It is presumed that even if the upper layer film is removed during the formation of the contact hole, it is hardly oxidized. In addition, when the substrate temperature during the deposition of the insulating film is high, the additional element in the Al alloy film easily moves to the surface layer, and thus the concentration of the additional element is further increased in the surface layer, and it is presumed that the oxidation becomes more difficult. .
【0044】本実施例は上層膜をMoとしたが、上層膜
をMo以外の金属とした場合も同様にAl合金膜中の添
加元素の濃度分布が表層部で高くなり酸化防止の結果が
得られ、Al合金膜と透明導電膜の電気的接触が可能で
あった。In this embodiment, the upper layer film is made of Mo. However, when the upper layer film is made of a metal other than Mo, the concentration distribution of the added element in the Al alloy film is similarly increased in the surface layer, and the result of preventing oxidation is obtained. As a result, electrical contact between the Al alloy film and the transparent conductive film was possible.
【0045】また、本実施例では、Al合金膜をAlに
対する固溶限が0.01at% と非常に小さい元素であ
るNdとの合金であるAl−2at%Ndとした。同様
にAlに対する固溶限の小さい元素であるY,La,C
e,Pr,Sm,Eu,Gd,Tb,Dy,Ho,E
r,Tm,Yb,Luを添加したAl合金膜を採用した
場合にも本実施例と同様にAl合金膜中の添加元素の濃
度分布が表層部で高くなり酸化防止の結果が得られ、A
l合金膜と透明導電膜の電気的接触が可能であった。In this embodiment, the Al alloy film is made of Al-2 at% Nd, which is an alloy of Nd which is a very small element having a solid solubility limit of 0.01 at% for Al. Similarly, Y, La, and C, which are elements having a small solid solubility limit with respect to Al,
e, Pr, Sm, Eu, Gd, Tb, Dy, Ho, E
Even when an Al alloy film to which r, Tm, Yb, and Lu are added is employed, the concentration distribution of the added element in the Al alloy film is increased in the surface layer portion as in this embodiment, and the result of oxidation prevention is obtained.
Electrical contact between the 1 alloy film and the transparent conductive film was possible.
【0046】また、単層においても、Al合金膜を堆積
後、大気中に出す前に、真空を破ることなく連続して還
元性、または、超高真空雰囲気でAl合金膜表面を酸化
させることなく熱処理し、Al合金中の添加元素の濃度
を表層部で高くしておくことでAl合金表面の酸化を防
止でき、透明導電膜との電気的接触は可能であった。 (実施例4)本実施例は、Al合金膜と透明導電膜との
電気的接触について、Al合金膜に添加する元素量をパ
ラメータとして調べた例である。Even in the case of a single layer, after depositing the Al alloy film, it is necessary to continuously reduce or oxidize the surface of the Al alloy film in an ultra-high vacuum atmosphere before breaking the vacuum into the atmosphere. By performing heat treatment without increasing the concentration of the additional element in the Al alloy in the surface layer portion, oxidation of the Al alloy surface could be prevented, and electrical contact with the transparent conductive film was possible. (Embodiment 4) This embodiment is an example in which electrical contact between an Al alloy film and a transparent conductive film was examined using the amount of elements added to the Al alloy film as a parameter.
【0047】実施例3と同様に図5のような配線パター
ンを作製し、Al合金配線50は、DCスパッタ法によ
り基板温度120℃にて、Al合金膜501と、上層膜
502としてMoを連続して堆積した。Alに対するNd
添加量をパラメータとした。また、絶縁膜堆積時の基板
温度は300℃とした。これを用いて4ヶ所の電極パッ
ト53を使い、四端子針法にてコンタクトホール54部
分での電気的接触を評価した。結果を表4に示す。表中
の、×は不可、○は良、◎は極めて良の意味である。A wiring pattern as shown in FIG. 5 was prepared in the same manner as in Example 3. The Al alloy wiring 50 was formed by DC sputtering at a substrate temperature of 120 ° C. and an Al alloy film 501 and an upper layer film.
Mo was continuously deposited as 502. Nd for Al
The addition amount was used as a parameter. The substrate temperature during the deposition of the insulating film was set to 300 ° C. Using this, the electrical contact at the contact hole 54 was evaluated by a four-terminal needle method using four electrode pads 53. Table 4 shows the results. In the table, x means not good, o means good, and ◎ means extremely good.
【0048】[0048]
【表4】 [Table 4]
【0049】Nd添加量が0.2at% 以上であれば電
気的接触が良好であり、好ましくは0.8at%以上で
電気的接触が更に良好になる。When the amount of Nd added is 0.2 at% or more, the electrical contact is good, and when it is 0.8 at% or more, the electrical contact is further improved.
【0050】これは、Al合金膜中の添加元素であるN
dの表層部での濃度分布の高さがNd添加量に依存して
高くなるため、酸化防止の結果が良くなり、Al合金膜
と透明導電膜との電気的接触が更に良好になると推察さ
れる。また、Nd添加無し、すなわち純Alでは電気的
接触が不可能である。これは、コンタクトホール形成
後、装置から大気中へ出したときに、またはITOとの
接触により、Al合金膜表面が酸化してしまうためであ
ると推察される。This is because N, which is an additive element in the Al alloy film,
Since the height of the concentration distribution of d in the surface layer increases depending on the amount of Nd added, the result of antioxidation is improved, and it is presumed that the electrical contact between the Al alloy film and the transparent conductive film is further improved. You. Further, no electrical contact is possible with no Nd addition, that is, pure Al. It is presumed that this is because the surface of the Al alloy film is oxidized when the device is brought into the air after forming the contact hole or when the device comes into contact with ITO.
【0051】本実施例は上層膜をMoとしたが、上層膜
をMo以外の金属とした場合も同様にAl合金膜中の添
加元素の濃度分布が表層部で高くなり酸化防止の結果が
得られ、Al合金膜と透明導電膜の電気的接触が可能で
あった。In the present embodiment, the upper layer film was made of Mo. However, when the upper layer film was made of a metal other than Mo, the concentration distribution of the added element in the Al alloy film was similarly increased in the surface layer, and the result of preventing oxidation was obtained. As a result, electrical contact between the Al alloy film and the transparent conductive film was possible.
【0052】また、本実施例では、Al合金膜をAlに
対する固溶限が0.01at% と非常に小さい元素であ
るNdとの合金とした。同様にAlに対する固溶限の小
さい元素であるY,La,Ce,Pr,Sm,Eu,G
d,Tb,Dy,Ho,Er,Tm,Yb、Luを添加
したAl合金膜を採用した場合にも本実施例と同様にA
l合金膜中の添加元素の濃度分布が表層部で高くなり酸
化防止の結果が得られ、Al合金膜と透明導電膜の電気
的接触が可能であった。 (実施例5)本実施例は、Al合金配線の上層膜のMo
合金の組成をパラメータとして、配線断面の形状を調べ
た例である。In this embodiment, the Al alloy film is made of an alloy of Nd, an element whose solid solubility limit with respect to Al is as small as 0.01 at%. Similarly, Y, La, Ce, Pr, Sm, Eu, and G, which are elements having a small solid solubility limit for Al.
In the case where an Al alloy film to which d, Tb, Dy, Ho, Er, Tm, Yb, and Lu are added is employed, A
The concentration distribution of the added element in the l-alloy film was increased in the surface layer portion, and the result of oxidation prevention was obtained, and electrical contact between the Al alloy film and the transparent conductive film was possible. (Embodiment 5) In this embodiment, the Mo film of the upper layer film of the Al alloy wiring is used.
This is an example of examining the shape of a wiring cross section using the composition of the alloy as a parameter.
【0053】DCスパッタ法にて、ガラス基板41上
に、Al合金膜42としてAl−2at%Ndを膜厚2
00nm、上層膜43としてMo合金を膜厚20nmを
連続して形成した。基板温度は120℃とした。続いて
ホトリソグラフィにて積層膜の上にレジストパターンを
形成し、りん酸,硝酸,酢酸,純水の混合液によって一
括エッチングして、Al合金配線44を形成し、その断
面形状を電子顕微鏡にて観察した。By a DC sputtering method, Al-2 at% Nd having a film thickness of 2 as an Al alloy film 42 is formed on a glass substrate 41.
A Mo alloy having a thickness of 20 nm was continuously formed as the upper layer 43. The substrate temperature was 120 ° C. Subsequently, a resist pattern is formed on the laminated film by photolithography, and the resist pattern is collectively etched with a mixed solution of phosphoric acid, nitric acid, acetic acid, and pure water to form an Al alloy wiring 44. And observed.
【0054】図7(a),(b)にAl合金配線の断面
の概略図を示す。Al合金膜のテーパ角度と庇の有無を
観察した。テーパ角度はAl合金膜42の端部45の角
度であり、庇とは図7(b)にあるように上層膜43が
Al合金膜42より突き出た状態を指す。表5に観察結
果を示す。FIGS. 7A and 7B are schematic views of a cross section of the Al alloy wiring. The taper angle of the Al alloy film and the presence or absence of an eave were observed. The taper angle is the angle of the end 45 of the Al alloy film 42, and the eaves indicate a state in which the upper film 43 protrudes from the Al alloy film 42 as shown in FIG. 7B. Table 5 shows the observation results.
【0055】[0055]
【表5】 [Table 5]
【0056】Mo合金にドライエッチング耐性を付与す
るためには、Crをある程度の量(約3wt%以上)M
oに添加する必要がある。しかしながら、Mo−3wt
%Crを上層膜としたAl合金膜との積層配線の場合
は、庇が発生し、積層配線を覆う絶縁膜のカバレッジが
低下する。この庇発生の原因は、ドライエッチング耐性
を持たせるだけ添加すると、ウェットエッチングレート
が低下してしまうためである。一方、Mo合金のドライ
エッチング耐性を必要条件としなければ、MoへのC
r,W,Nb,Ta等を適当量添加することにより、庇
を発生させること無しにテーパ形状制御が可能になる。In order to impart dry etching resistance to the Mo alloy, Cr must be added to a certain amount (about 3 wt% or more).
need to be added to o. However, Mo-3wt
In the case of a laminated wiring with an Al alloy film having% Cr as the upper layer film, an eaves are generated, and the coverage of the insulating film covering the laminated wiring is reduced. The cause of this eaves generation is that the wet etching rate is reduced if it is added only to have dry etching resistance. On the other hand, if the dry etching resistance of the Mo alloy is not a necessary condition, C
By adding an appropriate amount of r, W, Nb, Ta, or the like, the taper shape can be controlled without generating an eave.
【0057】このような本発明の実施例により、従来、
Al配線の適用に際し、ヒロック生成,透明導電膜との
電気的接触が粗悪,積層配線での断面形状制御が困難と
いう問題点を解消できる。更にAl合金膜のテーパ形状
を任意に制御することが可能であり、これにより、プロ
セスに適合する配線形状を自由に設計することができ
る。According to the embodiment of the present invention,
When the Al wiring is used, the problems of hillock generation, poor electrical contact with the transparent conductive film, and difficulty in controlling the cross-sectional shape of the laminated wiring can be solved. Further, it is possible to arbitrarily control the tapered shape of the Al alloy film, whereby the wiring shape suitable for the process can be freely designed.
【0058】従って、プロセス裕度が高く、配線形状も
安定して制御可能であるため電極間ショートなども無い
ため生産歩留が高くなり、安価に液晶表示装置を提供す
ることができる。Accordingly, the process margin is high, the wiring shape can be controlled stably, and there is no short circuit between the electrodes, so that the production yield is increased and the liquid crystal display device can be provided at low cost.
【0059】[0059]
【発明の効果】本発明により、生産歩留まりのよい液晶
表示装置を提供することができる。According to the present invention, a liquid crystal display device having a good production yield can be provided.
【図1】本発明による液晶表示装置の概略を示す平面図
である。FIG. 1 is a plan view schematically showing a liquid crystal display device according to the present invention.
【図2】本発明による液晶表示装置の薄膜トランジスタ
部分とゲート端子部の断面図である。FIG. 2 is a sectional view of a thin film transistor portion and a gate terminal portion of the liquid crystal display device according to the present invention.
【図3】図1のコンタクトホール20のAl合金膜40
1と透明導電膜9が直接接触している部分の深さ方向の
元素分析結果と、積層配線を純Alにして同様に作成し
た液晶表示装置のコンタクトホールのAl膜と透明導電
膜が直接接触している部分の深さ方向の元素分析結果を
示す概略図である。FIG. 3 shows an Al alloy film 40 in the contact hole 20 of FIG.
Elemental analysis results in the depth direction of a portion where the transparent conductive film 9 and the transparent conductive film 1 are in direct contact with each other. It is the schematic which shows the elemental analysis result of the depth direction of the part which performs.
【図4】図1のAの領域を観察した概略図を示す。FIG. 4 is a schematic view showing a region A of FIG. 1 observed.
【図5】実施例3における電気的接触の検討をする配線
パターンの平面の概略図を示す。FIG. 5 is a schematic plan view of a wiring pattern for examining electrical contact in a third embodiment.
【図6】図5におけるA−A′の断面の概略図を示す。FIG. 6 is a schematic view of a cross section taken along line AA ′ in FIG. 5;
【図7】実施例5における配線断面の概略図を示す。FIG. 7 is a schematic view of a cross section of a wiring according to a fifth embodiment.
1…ゲート配線、2…データ配線、3…ソース電極、4
…ドレイン電極、5…ゲート絶縁膜、6…半導体層、7
…n+ 半導体層、8…保護膜、9,52…透明導電膜、
10…ガラス基板、20…コンタクトホール(薄膜トラ
ンジスタ部)、21…コンタクトホール(ゲート端子出
し部)、30…画素部、31…ゲート配線端子群、32
…データ配線端子群、33…Al合金膜の表層部、41
…ガラス基板、42,501…Al合金膜、43,50
2…上層膜、44…Al合金配線、45…Al合金膜の
端部、50…Al合金配線、51…絶縁膜、53…電極
パット、54…コンタクトホール、101…Al合金膜
(ゲート配線部)、102…上層膜(ゲート配線部)、
301…Al合金膜(ソース電極部)、302…上層膜
(ソース電極部)、303…下層膜(ソース電極部)、
401…Al合金膜(ドレイン電極部)、402…上層
膜(ドレイン電極部)、403…下層膜(ドレイン電極
部)。DESCRIPTION OF SYMBOLS 1 ... Gate wiring, 2 ... Data wiring, 3 ... Source electrode, 4
... Drain electrode, 5 ... Gate insulating film, 6 ... Semiconductor layer, 7
... n + semiconductor layer, 8 ... protective film, 9, 52 ... transparent conductive film,
DESCRIPTION OF SYMBOLS 10 ... Glass substrate, 20 ... Contact hole (thin film transistor part), 21 ... Contact hole (gate terminal lead part), 30 ... Pixel part, 31 ... Gate wiring terminal group, 32
... data wiring terminal group, 33 ... surface part of Al alloy film, 41
... Glass substrate, 42,501 ... Al alloy film, 43,50
2 upper layer film, 44 Al alloy wiring, 45 end of Al alloy film, 50 Al alloy wiring, 51 insulating film, 53 electrode pad, 54 contact hole, 101 Al alloy film (gate wiring portion) ), 102 ... upper layer film (gate wiring portion),
301: Al alloy film (source electrode portion), 302: upper layer film (source electrode portion), 303: lower layer film (source electrode portion),
Reference numeral 401 denotes an Al alloy film (drain electrode portion), 402 denotes an upper layer film (drain electrode portion), and 403 denotes a lower layer film (drain electrode portion).
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/786 H01L 29/78 616U 616V 617U 617M (72)発明者 佐藤 健史 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 日高 貴志夫 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 鬼沢 賢一 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 Fターム(参考) 2H092 JA26 JA34 JA37 JA41 JA44 JA46 JB24 JB33 KA05 KA18 KB04 MA05 MA08 MA17 MA37 NA27 5C094 AA21 AA42 AA43 BA03 BA43 CA19 DA13 EA03 EA04 EA05 EA07 FA02 FB02 FB12 GB01 JA08 5F033 GG04 HH10 HH20 HH38 JJ01 JJ38 KK10 KK20 MM05 MM08 MM19 NN17 PP15 QQ08 QQ09 QQ11 QQ19 RR06 SS15 VV06 VV15 WW02 WW03 WW04 XX02 XX09 XX16 XX20 XX31 5F110 AA26 AA30 BB01 CC07 DD02 EE04 EE06 EE14 EE23 EE44 FF03 FF30 GG02 GG15 GG45 HK04 HK06 HK09 HK16 HK22 HK25 HK35 HL07 HL23 NN02 NN24 NN35 NN72 QQ05 QQ09──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 29/786 H01L 29/78 616U 616V 617U 617M (72) Inventor Takeshi Sato 7-chome, Omikacho, Hitachi City, Ibaraki Prefecture No. 1-1 Inside Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Takao Hidaka 1-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Kenichi Onizawa Ibaraki Prefecture 7-1-1, Omika-cho, Hitachi City F-term in Hitachi Research Laboratory, Hitachi Ltd. (Reference) 2H092 JA26 JA34 JA37 JA41 JA44 JA46 JB24 JB33 KA05 KA18 KB04 MA05 MA08 MA17 MA37 NA27 5C094 AA21 AA42 AA43 BA03 BA43 CA19 DA13 EA03EA04 EA05 EA07 FA02 FB02 FB12 GB01 JA08 5F033 GG04 HH10 HH20 HH38 JJ01 JJ38 KK10 KK20 MM05 MM08 MM19 NN17 PP15 QQ0 8 QQ09 QQ11 QQ19 RR06 SS15 VV06 VV15 WW02 WW03 WW04 XX02 XX09 XX16 XX20 XX31 5F110 AA26 AA30 BB01 CC07 DD02 EE04 EE06 EE14 EE23 EE44 FF03 FF30 GG02 GG15 NG45 HK45 HK45 HK04 HK45 HK04 HK45
Claims (18)
一対の基板間に挟持された液晶層と、前記一対の基板の
少なくとも一方の上に配置した電極群とを有し、前記電
極群により前記液晶層の液晶を動かして表示を制御する
液晶表示装置において、 前記一対の基板の少なくとも一方の基板上に配置した前
記電極群は、少なくとも複数のゲート配線と、該複数の
ゲート配線に交差するように形成された複数のデータ配
線とにより構成され、 前記複数のゲート配線と前記複数のデータ配線のそれぞ
れの交点に対応して薄膜トランジスタが配置され、 前記ゲート配線と前記データ配線の少なくとも一方は、
Al合金膜と前記Al合金膜上にAl以外の金属種の上
層膜を有する積層配線で構成され、 前記積層配線を覆う絶縁膜に形成したコンタクトホール
を介して前記Al合金膜と透明導電膜が接続された構成
であり、 前記Al合金膜中の添加元素の濃度分布は、Al合金膜
の内層部より表層部において高い液晶表示装置。An electrode group disposed on at least one of the pair of substrates; a liquid crystal layer sandwiched between the pair of substrates; and an electrode group disposed on at least one of the pair of substrates. A liquid crystal display device that controls display by moving liquid crystal in the liquid crystal layer, wherein the electrode group disposed on at least one of the pair of substrates intersects at least a plurality of gate wirings and the plurality of gate wirings. A plurality of data wirings formed so as to form a plurality of data wirings, and a thin film transistor is arranged at each intersection of the plurality of gate wirings and the plurality of data wirings. At least one of the gate wirings and the data wirings ,
An Al alloy film and a multilayer wiring having an upper layer film of a metal type other than Al on the Al alloy film, wherein the Al alloy film and the transparent conductive film are formed through a contact hole formed in an insulating film covering the multilayer wiring. A liquid crystal display device having a connection structure, wherein the concentration distribution of the additive element in the Al alloy film is higher in a surface layer portion than in an inner layer portion of the Al alloy film.
が、固溶限以上である請求項1の液晶表示装置。2. The liquid crystal display device according to claim 1, wherein the concentration of the element added to the Al alloy film is equal to or higher than the solid solubility limit.
の固溶限が、0.1at% 以下である請求項1の液晶表
示装置。3. The liquid crystal display device according to claim 1, wherein an element added to said Al alloy film has a solid solubility limit in Al of 0.1 at% or less.
r,Nd,Sm,Eu,Gd,Tb,Dy,Ho,E
r,Tm,Yb,Luのうち少なくとも1種類以上を合
計で0.2at%以上添加している請求項1の液晶表示装
置。4. The Al alloy film is made of Y, La, Ce, P
r, Nd, Sm, Eu, Gd, Tb, Dy, Ho, E
2. The liquid crystal display device according to claim 1, wherein at least one of r, Tm, Yb, and Lu is added in a total amount of 0.2 at% or more.
下である請求項1の液晶表示装置。5. The liquid crystal display device according to claim 1, wherein the thickness of the upper layer film of said laminated wiring is 50 nm or less.
ある請求項1の液晶表示装置。6. The liquid crystal display device according to claim 1, wherein said upper layer film is an alloy containing Mo as a main component.
なくとも一方の配線は、前記Al合金膜の下に他金属種
の下層膜を有する積層配線である請求項1の液晶表示装
置。7. The liquid crystal display device according to claim 1, wherein at least one of the data wiring and the gate wiring is a laminated wiring having a lower layer film of another metal type under the Al alloy film.
側に近いほど幅広のテーパ状である請求項1の液晶表示
装置。8. The liquid crystal display device according to claim 1, wherein the end of the cross section of the Al alloy film has a tapered shape that is wider as it is closer to the substrate side.
一対の基板間に挟持された液晶層と、前記一対の基板の
少なくとも一方の上に配置した電極群とを有し、前記電
極群により前記液晶層の液晶を動かして表示を制御する
液晶表示装置において、 前記一対の基板上の少なくとも一方の基板上に配置した
前記電極群は、少なくとも複数のゲート配線と、該複数
のゲート配線に交差するように形成された複数のデータ
配線とにより構成され、 前記複数のゲート配線と前記複数のデータ配線のそれぞ
れの交点に対応して薄膜トランジスタが配置され、 前記ゲート配線の上部には絶縁膜を介して半導体層を形
成し、 前記データ配線,ドレイン電極及びソース電極は、Al
合金膜と該Al合金膜上にAl以外の金属種の上層膜を
有する積層配線で構成されており、 前記積層配線を覆う絶縁膜に形成したコンタクトホール
を介して前記Al合金膜と透明導電膜が接続されてお
り、 前記Al合金膜中の添加元素の濃度分布が、Al合金膜
の内層部より表層部において高い液晶表示装置。9. The electrode group comprising: a pair of substrates, at least one of which is transparent; a liquid crystal layer sandwiched between the pair of substrates; and an electrode group disposed on at least one of the pair of substrates. In the liquid crystal display device that controls display by moving the liquid crystal of the liquid crystal layer, the electrode group disposed on at least one of the pair of substrates includes at least a plurality of gate wirings and a plurality of gate wirings. A plurality of data lines formed so as to intersect; a thin film transistor is arranged corresponding to each of intersections of the plurality of gate lines and the plurality of data lines; A data layer, a drain electrode and a source electrode are formed of Al.
An aluminum alloy film and a layered wiring having an upper layer film of a metal species other than Al on the Al alloy film, wherein the Al alloy film and the transparent conductive film are formed through a contact hole formed in an insulating film covering the stacked wiring. Wherein the concentration distribution of the added element in the Al alloy film is higher in the surface layer portion than in the inner layer portion of the Al alloy film.
が、固溶限以上である請求項1の液晶表示装置。10. The liquid crystal display device according to claim 1, wherein the concentration of the element added to the Al alloy film is equal to or higher than the solid solubility limit.
への固溶限が、0.1at% 以下である請求項1の液晶
表示装置。11. The element Al added to the Al alloy film.
2. The liquid crystal display device according to claim 1, wherein a solid solubility limit of the liquid crystal is 0.1 at% or less.
r,Nd,Sm,Eu,Gd,Tb,Dy,Ho,E
r,Tm,Yb,Luのうち少なくとも1種類以上を合
計で0.2at%以上添加している請求項1の液晶表示装
置。12. The Al alloy film is made of Y, La, Ce, P
r, Nd, Sm, Eu, Gd, Tb, Dy, Ho, E
2. The liquid crystal display device according to claim 1, wherein at least one of r, Tm, Yb, and Lu is added in a total amount of 0.2 at% or more.
以下である請求項1の液晶表示装置。13. A film thickness of an upper layer film of said laminated wiring is 50 nm.
2. The liquid crystal display device according to claim 1, wherein:
である請求項1の液晶表示装置。14. The liquid crystal display device according to claim 1, wherein said upper film is an alloy containing Mo as a main component.
少なくとも一方の配線は、前記Al合金膜の下に他金属
種の下層膜を有する積層配線である請求項1の液晶表示
装置。15. The liquid crystal display device according to claim 1, wherein at least one of the data wiring and the gate wiring is a stacked wiring having a lower layer film of another metal type under the Al alloy film.
板側に近いほど幅広のテーパ状である請求項1の液晶表
示装置。16. The liquid crystal display device according to claim 1, wherein the end of the cross section of the Al alloy film has a tapered shape that becomes wider as it approaches the substrate side.
上に形成した上層膜の真空を破ることなく連続して堆積
する工程と、 前記ゲート配線を覆う絶縁膜を200℃以上の基板温度
で堆積する工程と、 前記絶縁膜と前記上層膜をドライエッチングにて除去し
てコンタクトホールを形成する工程を有する液晶表示装
置の製造方法。17. A step of continuously depositing a gate wiring without breaking a vacuum of an Al alloy film and an upper film formed on the Al alloy film, and forming an insulating film covering the gate wiring on a substrate having a substrate temperature of 200 ° C. or more. And a step of forming a contact hole by removing the insulating film and the upper layer film by dry etching.
極の下層膜,Al合金膜及び上層膜の真空を破ることな
く連続して堆積する工程と、 前記データ配線,ドレイン電極及びソース電極を覆う絶
縁膜を200℃以上の基板温度で堆積する工程と、 前記絶縁膜と前記上層膜をドライエッチングにて除去し
てコンタクトホールを形成する工程を有する液晶表示装
置の製造方法。18. A process for continuously depositing a lower layer film, an Al alloy film and an upper layer film of a data wiring, a drain electrode and a source electrode without breaking a vacuum, and an insulating film covering the data wiring, the drain electrode and the source electrode. And a step of forming a contact hole by removing the insulating film and the upper layer film by dry etching.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000174190A JP2001350159A (en) | 2000-06-06 | 2000-06-06 | Liquid crystal display device and manufacturing method thereof |
| KR1020000052051A KR20010112030A (en) | 2000-06-06 | 2000-09-04 | Liquid crystal display device and process for producing the same |
| TW089118169A TW528912B (en) | 2000-06-06 | 2000-09-05 | Liquid crystal display device and process for producing the same |
| CN00126331A CN1327168A (en) | 2000-06-06 | 2000-09-05 | Liquid crystal display device and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000174190A JP2001350159A (en) | 2000-06-06 | 2000-06-06 | Liquid crystal display device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001350159A true JP2001350159A (en) | 2001-12-21 |
Family
ID=18676269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000174190A Pending JP2001350159A (en) | 2000-06-06 | 2000-06-06 | Liquid crystal display device and manufacturing method thereof |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2001350159A (en) |
| KR (1) | KR20010112030A (en) |
| CN (1) | CN1327168A (en) |
| TW (1) | TW528912B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303003A (en) * | 2004-04-12 | 2005-10-27 | Kobe Steel Ltd | Display device and manufacturing method thereof |
| US7009749B2 (en) | 2002-03-11 | 2006-03-07 | Sanyo Electric Co., Ltd. | Optical element and manufacturing method therefor |
| JP2006100856A (en) * | 2002-12-19 | 2006-04-13 | Kobe Steel Ltd | Display device, method of manufacturing the same, and sputtering target |
| US7166921B2 (en) | 2003-11-20 | 2007-01-23 | Hitachi Metals, Ltd. | Aluminum alloy film for wiring and sputter target material for forming the film |
| WO2008032786A1 (en) * | 2006-09-15 | 2008-03-20 | Kabushiki Kaisha Kobe Seiko Sho | Display device |
| US7928575B2 (en) | 2002-12-19 | 2011-04-19 | Kobe Steel, Ltd. | Electronic device, method of manufacture of the same, and sputtering target |
| US7952123B2 (en) | 2005-12-02 | 2011-05-31 | Kobe Steel, Ltd. | Thin film transistor substrate and display device |
| JP2011171053A (en) * | 2010-02-17 | 2011-09-01 | Hitachi Displays Ltd | Display device |
| US8053083B2 (en) | 2007-06-26 | 2011-11-08 | Kobe Steel, Ltd. | Layered structure and its manufacturing method |
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|---|---|---|---|---|
| KR20030016051A (en) | 2001-08-20 | 2003-02-26 | 삼성전자주식회사 | Thin film transistor array panel for a liquid crystal display and a manufacturing method thereof |
| CN1309036C (en) * | 2004-12-13 | 2007-04-04 | 友达光电股份有限公司 | Manufacturing method of thin film transistor element |
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-
2000
- 2000-06-06 JP JP2000174190A patent/JP2001350159A/en active Pending
- 2000-09-04 KR KR1020000052051A patent/KR20010112030A/en not_active Withdrawn
- 2000-09-05 TW TW089118169A patent/TW528912B/en active
- 2000-09-05 CN CN00126331A patent/CN1327168A/en active Pending
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| US7928575B2 (en) | 2002-12-19 | 2011-04-19 | Kobe Steel, Ltd. | Electronic device, method of manufacture of the same, and sputtering target |
| JP2006100856A (en) * | 2002-12-19 | 2006-04-13 | Kobe Steel Ltd | Display device, method of manufacturing the same, and sputtering target |
| US7166921B2 (en) | 2003-11-20 | 2007-01-23 | Hitachi Metals, Ltd. | Aluminum alloy film for wiring and sputter target material for forming the film |
| JP2005303003A (en) * | 2004-04-12 | 2005-10-27 | Kobe Steel Ltd | Display device and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1327168A (en) | 2001-12-19 |
| KR20010112030A (en) | 2001-12-20 |
| TW528912B (en) | 2003-04-21 |
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