JP2001345420A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of performing stable operation in a wide temperature range. A heater is provided near a differential amplifier.
The normal operation of the differential amplifier 11 in a wide temperature range is ensured by disposing the heater 12a and energizing the heaters 12a and 12b in a low temperature environment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor integrated circuit including an analog circuit formed by using a temperature-dependent element.

[0002]

2. Description of the Related Art In recent years, miniaturization of electronic devices has progressed, and many portable electronic devices have appeared. Formerly, electronic devices were installed in a room equipped with air conditioning equipment and used under a relatively stable temperature environment. Semiconductor devices used in such electronic devices have a narrow temperature range in which operation is guaranteed. In particular, it is rare that operation in a low-temperature environment below 0 ° is guaranteed. It may be used in a high-temperature environment due to heat generated by the semiconductor device itself or heat generated by other devices in the set box, but may not be used in a low-temperature environment that is much lower than room temperature. Because there is no.

On the other hand, it must be assumed that portable electronic devices in recent years are used outdoors in severe winter. In addition, operation in a high-temperature environment such as being left in a car under the scorching sun must be assumed. Further, electronic devices other than portable electronic devices are often installed outside a room without air conditioning equipment, for example, on a telephone pole or the like, due to downsizing of the set box. In any case, operation guarantee over a wide range of temperatures is required.

[0004] Various electrical characteristics of a semiconductor device have temperature dependence. For example, in the case of a MOS transistor, the threshold voltage and the current driving capability have a negative dependency on temperature. FIG. 20 shows a gate voltage (Vg) -drain current (Id) characteristic of a MOS transistor as such an example. In the figure, the characteristic under a high temperature environment is indicated by a solid line, and the characteristic under a low temperature environment is indicated by a broken line.

Generally, in a digital logic circuit,
The operating speed of the circuit decreases as the threshold voltage of the transistor increases, and the operating speed of the circuit increases as the driving capability increases. In a low-temperature environment, these effects cancel each other, and the speed of the circuit is slightly increased. Conversely, when the threshold voltage decreases, the circuit speed increases, and when the driving capability decreases, the circuit speed decreases. In a high-temperature environment, these effects cancel each other, and the speed of the circuit is slightly reduced. In designing a digital logic circuit, it is important that the response speed of the circuit can achieve a target value. Therefore, in the digital logic circuit, it is not necessary to pay attention to the operating characteristics under a high-temperature environment and pay much attention to the operating characteristics under a low-temperature environment.

On the other hand, in an analog circuit,
The amount of deterioration in circuit characteristics due to an increase in the threshold voltage of a transistor is much larger than that of a digital circuit.
An example will be described with a differential amplifier shown in FIG. In order for the differential amplifier to operate accurately and stably, the input terminal I
It is preferable that the potentials of N1 and IN2 be in the range of 2 Vtn to VCC-Vtp. Here, Vtn is NMOS
The gate threshold voltages of the transistors QN1, QN2, QN3, and Vtp are the PMOS transistors QP1, QP
This is the gate threshold voltage (absolute value) of P2.

[0007] The threshold voltage of a transistor rises at low temperatures. Therefore, the preferred input voltage range VCC-2
Vtn-Vtp decreases as the temperature decreases. That is, in an analog circuit, it is necessary to design a circuit while paying sufficient attention to operation in a low-temperature environment.

It is difficult to guarantee the operation of a semiconductor memory over a wide temperature range. Specifically, the case of a DRAM will be described with reference to FIGS. DRA
As shown in FIG. 22, the M cell includes one NMOS transistor and one capacitor. Data is stored in the form of charge transferred to a capacitor via a MOS transistor. Data reading is performed by giving the "H" level to the selected word line, reading out the charge of the memory cell to the bit line, and detecting and amplifying this by the sense amplifier SA.

FIGS. 23 (a) and 23 (b) show a selected word line W
For memory cells along L1 and unselected word line WL2, bit lines BLt, BLt,
3 shows potential changes of BLc and storage nodes SN1 and SN2. In a high-temperature environment, the threshold voltage of the cell transistor decreases, and therefore, the storage node SN2 and the bit line B in the non-selected cell in the direction indicated by arrow B in FIG.
The leakage current during Lc increases. That is, it becomes difficult to hold the charge stored in the capacitor at a high temperature.

Conversely, at low temperatures, the threshold voltage Vtn of the cell transistor increases. The high potential state of the bit line is VB
LH, when the potential of the selected word line is VWLH, VBLH or VWLH is applied to the capacitor of the selected cell.
The lower one of -Vtn is transferred. Therefore, in a low-temperature environment, it becomes difficult to charge the capacitor to a high potential state as indicated by an arrow A in FIG. In order to clear these two contradictory conditions, it is necessary to accurately control the threshold voltage of the cell transistor in the manufacturing process and to make the word line high potential VWLH sufficiently high. But each has its limitations,
Therefore, the operating temperature range of a semiconductor memory such as a DRAM is narrower than that of a digital logic circuit or the like.

[0011]

As described above, analog circuits and semiconductor memories have a problem that it is difficult to guarantee operation in a wide temperature range. 2. Description of the Related Art Small electronic devices such as portable devices use highly integrated semiconductor integrated circuits. These are called system-on-chip (SOC), and digital logic and analog circuits,
A semiconductor memory such as a DRAM is integrated. As described above, since digital logic circuits, analog circuits, and semiconductor memories have different temperature characteristics, it is difficult to operate all circuits stably over a wide temperature range.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of performing stable operation in a wide temperature range.

[0013]

A semiconductor device according to the present invention is characterized by having an analog circuit constituted by using a temperature-dependent element, and a heater arranged near the analog circuit. I do.

According to the present invention, by raising the temperature near the analog circuit which becomes unstable in a low-temperature environment by the heater, it is possible to guarantee the stable operation of the analog circuit even in a low-temperature environment. . In particular, when the analog circuit is a differential amplifier whose operation becomes unstable due to an input offset in a low temperature environment, a heater can be arranged near the differential amplifier to realize a stable operation. An analog circuit is a differential amplifier, a current mirror circuit including a plurality of transistors whose gates are commonly controlled by an output of the differential amplifier, and a current is constantly supplied by each transistor of the current mirror circuit. When a plurality of current paths are provided, by arranging a heater near the current mirror circuit which causes unstable operation in a low-temperature environment, stable operation of the analog circuit can be realized.

In the present invention, preferably, (a) a power-on control circuit for controlling the power supply to the heater for a certain period of time immediately after power-on is provided, or (b) a temperature near the analog circuit is sensed. A temperature sensor for controlling the heater to be energized at a certain temperature or lower. Further, in the present invention, an element in which a current constantly flows in an analog circuit can be used as the heater.

The power-on control circuit includes, for example, a power-supply voltage detection circuit for detecting a rise of the power-supply voltage, and a delay circuit for energizing the heater for a predetermined time after the power-on voltage detection circuit detects the power-on. Is done. Furthermore, a control circuit for suppressing the operation of the analog circuit while the power-on control circuit is energizing the heater can be provided.

Further, in the present invention, when the analog circuit constitutes a band gap reference circuit (BGR circuit) including a current mirror circuit, a current detection circuit for detecting a current of the current mirror circuit, and the current detection circuit A kicker circuit for forcibly shifting the transistor of the current mirror circuit to the pentode region when it is detected that the transistor of the current mirror circuit is abnormally stable in the sub-threshold region.
The GR circuit can escape from the abnormally stable state.

The semiconductor device according to the present invention is further characterized by having a memory cell array and a heater disposed on the memory cell array so as to uniformly heat the memory cell array. By arranging and heating the heater on the memory cell array in this manner, it becomes possible to use a semiconductor memory such as a DRAM having a narrow operating temperature range in a wide temperature range.

The semiconductor device according to the present invention further includes a semiconductor chip, a digital logic circuit, a memory cell array, and an analog circuit integrated on the semiconductor chip, and the memory cell array arranged on the memory cell array to uniformly distribute the memory cell array at a low temperature. A first heater for warming the analog circuit, and a second heater arranged near the analog circuit for warming the analog circuit area at a low temperature. Thus, system on chip (SOC)
In a semiconductor device having a structure, a heater is provided in each of an analog circuit portion and a memory cell array portion to adjust the temperature of each region to an optimum state, thereby ensuring stable operation of the system in a wide temperature range. .

An electronic apparatus according to the present invention includes a housing provided with a cooling device for cooling the inside, and an electronic device disposed in the housing.
It has a semiconductor memory with a built-in heater and a digital logic LSI with a radiator disposed in the housing.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows an equivalent circuit of an embodiment in which the present invention is applied to a semiconductor integrated circuit (LSI) including a differential amplifier 11 having a CMOS structure, and FIG. 2 shows a layout thereof. The differential amplifier 11 includes PMOS transistors QP1 and QP2 forming a current mirror load, and a differential NM
OS transistor pair QN1, QN2 and current source NMOS
It is composed of a transistor QN3. In the vicinity of the differential amplifier 11, heaters (electric heaters) 12a and 12b composed of resistors R1 and R2 are arranged.

As shown in FIG. 2, the differential amplifier 11 and
The heaters 12a and 12b composed of the resistors R1 and R2 are integrally formed on the same silicon substrate 10. Although not shown in detail in the figure, the PMOS transistor Q of the differential amplifier 11
P1 and QP2 are NMOS transistors Q in the n-type well.
N1-QN3 is formed in the p-type well. The hatched portion in FIG. 2 indicates a gate electrode. The resistors R1 and R2 are connected to a high resistance diffusion layer (for example, n
Mold layer). Heat generated by passing a current through the resistors R1 and R2 is transmitted to the differential amplifier 11 through the silicon substrate 10.

The effect of this embodiment will be described below with reference to FIG. 3 while clarifying specific problems.
In order for the differential amplifier to operate accurately and stably,
As shown in (a), when the potentials of the input terminals IN1 and IN2 change the threshold value of the NMOS transistor to Vtn and PMO
Assuming that the threshold value of the S transistor is Vtp (absolute value),
It is preferably in the range of VCC-2Vtn-Vtp. However, the power supply voltage has been reduced for the purpose of low power consumption and high device reliability. On the other hand, the threshold voltages Vtn and Vtp of the transistors have not been reduced because the cutoff current needs to be suppressed. Therefore, the voltage range allowed for the input signal becomes narrower as the process technology advances.

For example, at 25 ° C., Vtn = 0.5
A transistor with V, Vtp = 0.6 V is made, and V
Assume that CC is used at 2.5V. Here, since the threshold voltage of the transistor is affected by variations in the manufacturing process, it is assumed that the circuit operates normally even when the threshold voltage increases by 0.1 V. In addition, the power supply voltage Vcc must be designed so that the circuit operates even at VCC = 2.2 V in consideration of the variation in the device used and the voltage drop due to the current flowing through the power supply line. Considering these element allowances and power supply allowances, the preferable input voltage range of the differential amplifier is 0.3 as shown in FIG.
V (= 2.2V−2 × 0.6V−0.7V).

Further, the threshold voltage of a MOS transistor has a temperature dependency. The situation is as shown in FIG.
In order to guarantee operation in a low temperature environment such as -50 ° C,
It is necessary to consider that the threshold value of each transistor rises by about 0.1 V. Considering the rise of the threshold voltage at low temperature, as shown in FIG. 3C, the voltage range allowed for the input signal of the differential amplifier is almost 0V ｛= 2.2V−2 × (0 .6V + 0.1V)-
(0.7V-0.1V)}. In other words, the accuracy and stability of the differential amplifier cannot be expected in a low temperature environment of -50 ° C. as it is.

According to this embodiment, even if -50.degree.
Even in such a low temperature environment, stable operation can be achieved by warming the differential amplifier 11 by the heaters 12a and 12b disposed near the differential amplifier 11. Heater 12
a and 12b can be integratedly formed with transistors as simple circuit elements, and have high resistance to disturbance.
Further, since a complicated element is not required, the manufacturing cost of the chip does not increase. In this embodiment, a differential amplifier has been described. However, similar effects can be obtained by applying the present invention to other analog circuits in which a change in the threshold voltage of a transistor causes deterioration of characteristics.

[Second Embodiment] FIG. 5 shows an equivalent circuit of a main part of an LSI according to a second embodiment. A differential amplifier 11 similar to that of the previous embodiment and a resistor R for heating the same.
1 and R2. In this embodiment, a power-on control circuit 52 for controlling the heaters 12a and 12b to be energized only when the power is turned on is further integrated. The power-on control circuit 52 includes a power supply voltage detection circuit 53 and a delay circuit 54. As a switch controlled by a warm-up signal WARMUP output from the delay circuit 54, NM is connected in series with the heaters 12a and 12b.
OS transistors QN11 and QN12 are inserted.

The operation of the heater control in this embodiment is described as follows.
This will be described with reference to FIG. The power supply voltage detection circuit 53 turns on the PMOS transistor QP14 while the power supply voltage VCC immediately after the power is turned on is about Vtn + Vtp or less,
An output INIT that rises with the power supply voltage VCC is issued. When the power supply voltage becomes higher than approximately Vtn + Vtp, the node N1 becomes "L", the node N2 becomes "H", and the NMOS transistor QN16 turns on the PMOS transistor QP1.
4 is turned off, and the output INIT becomes “L” (= VSS).
become. Output WARMUP of delay circuit 54 also rises substantially according to the power supply voltage while power supply voltage VCC is low. When the output INIT of the power supply voltage detection circuit 53 becomes “L”, charging of the capacitor C1 starts via the PMOS transistor QP15 and the resistor R4, and after a certain time determined by the time constant of the resistor R4 and the capacitor C1, the NMOS C
Transistor QN18 is on, PMOS transistor Q
P16 is turned off, and the output WARMUP becomes "L".

Therefore, the heaters 12a and 12b are turned on for a time determined by the delay circuit 54 after the power is turned on, and then the heaters 12a and 12b are turned off. In general, an analog circuit needs to constantly supply a current even in a standby state, and this current generates heat in the analog circuit itself. Therefore, the analog circuit can operate stably if the power is on. The problem is that the chip immediately after power-on is at the same temperature as the outside air. According to this embodiment, the control is performed such that the heater is energized for a certain period of time immediately after the power is turned on, thereby enabling a transition to a stable operation. Then, by turning off the heater, unnecessary current consumption can be reduced.

[Third Embodiment] FIG. 7 shows a differential amplifier 11 in addition to the power-on control circuit 52 in the second embodiment.
A control circuit 71 for suppressing the operation of the differential amplifier 11
Is provided with a control circuit 72 for suppressing the circuit operation of the entire LSI chip until a stable operation is started. The control circuit 71 is connected to the N terminal inserted into the ground terminal of the differential amplifier 11.
It has a MOS transistor QN21, a PMOS transistor QP21 inserted between an output terminal and a power supply terminal, and an inverter composed of a PMOS transistor QP22 and an NMOS transistor QN22 for controlling these with a signal WARMUP. The control circuit 72 includes a delay circuit 54
And a delay circuit substantially similar to the above.

The operation when the power is turned on in this embodiment is as follows. When the power is turned on, the power supply voltage detection circuit 53 detects this and outputs an output INIT as described above. When the power supply is stabilized and the signal INIT becomes “L”,
After elapse of a time determined by the delay time of the delay circuit 54, the signal WARMUP becomes "L". This signal WARMUP
Is "H", power is supplied to the heaters 12a and 12b as described above. While the heaters 12a and 12b are energized, the NMOS transistor QN of the control circuit 71
21 is off, the ground terminal of the differential amplifier 11 is open, the PMOS transistor QP21 is on, and the output terminal OUT is kept fixed at VCC. That is, the differential amplifier 11 is in a standby state in which the current path is turned off until the differential amplifier 11 is heated to some extent, and the circuit operation is suppressed.

Further, the control circuit 72 outputs a signal WARMUP.
Becomes “L” and the differential amplifier 11 starts operating,
Until the output OUT is stabilized, the ready signal CHP
By RDY (= “L”), other circuits in the chip are also
Circuit operation is suppressed in a standby state in which no current flows.
After a lapse of time determined by the time constant circuit of the control circuit 72, the ready signal CHPRDY = "H" is output, and the entire chip is activated. As described above, in this embodiment, the differential amplifier 11 starts operation after the temperature in the vicinity thereof has risen to some extent, and further performs control such that the operation of the entire chip is started after its output is stabilized. ,
The stable operation of the differential amplifier in a low-temperature environment and the stable operation of the entire integrated circuit chip including the differential amplifier can be achieved.

[Embodiment 4] FIG. 8 shows an embodiment in which the present invention is applied to an LSI including a reference voltage generating circuit (BGR circuit) 80 using a band gap reference circuit. FIG. 9 shows the layout. BGR
The circuit is a circuit that generates a reference voltage that does not depend on the power supply voltage or the temperature. Two current paths 82 and 83 are connected to the drain of the current source PMOS transistor QP33 controlled by the output of the differential amplifier 81. One current path 82 includes a resistor R31 and a diode D1. The other current path 83 includes resistors R32, R33
And a diode D2. The junction area of the other diode D2 is N times that of the other diode D1.
The connection node between the resistor R31 and the diode D1 is fed back to one input terminal a of the differential amplifier 81, and the resistor R3
The connection node between 2 and R33 is fed back to the other input terminal b of the differential amplifier 81.

In this embodiment, in order to guarantee the stable operation of the BGR circuit 80, the resistors R31, R32 and R33 used in the BGR circuit 80 are arranged so as to sandwich the differential amplifier 81 as shown in FIG. Are used as heaters 82a and 82b for heating the differential amplifier 81.
As described above, the BGR circuit 80 outputs a reference voltage that is originally independent of temperature dependency and power supply dependency, but under certain conditions, this basic performance is impaired. To help understand this point, the basic operation of the BGR circuit will be described first.

Generally, a current-voltage characteristic of a diode is expressed by the following equation (1).

[0036]

## EQU1 ## I = Is (e ^{qVf / kT} -1)

Is is a saturation current, Vf is a forward voltage, and k is
Boltzmann's constant (= 1.38 × 10 ^{-twenty three}[J / K]),
q is the amount of electron charge (= 1.6 × 10^-19[C]), T is warm
Degrees. Under the condition of Vf >> kT / q, Equation 1 is more
It is simply represented by Equation 2.

[0038]

## ^EQU2 ## I = Ise ^{qVf / kT}

By further transforming equation (2), equation (3) is obtained.

[0040]

[Number 3] _{Vf = V T ln (I /} Is)

In the differential amplifier 81, the input terminals a and b are held at the same potential. Therefore, the terminal voltage of the diode D1 is Vfa, the terminal voltage of the diode D2 is Vfb, and the resistance R
Assuming that the voltage between the terminals of 33 is dVf, the following relationship is obtained.

[0042]

## EQU4 ## dVf = Vfa-Vfb

Here, the current flowing through the path 82 on the side of the resistor R31 is determined by the resistor R31, and the path 8 on the side of the resistor R32 is determined.
The current flowing through 3 is determined by the resistor R32. Further, since the current on the resistor R32 side is divided into N diodes, the following relationship is obtained.

[0044]

## EQU5 ## dVf = V _T ln (N · R32 / R31)

From the above, the output reference voltage VBGR of the BGR circuit is expressed by the following equation 6 with the built-in voltage of the diode as Vf1.

[0046]

VBGR = Vf1 + dVf (R32 / R33) = Vf1 + (R32 / R33) V _T ln (N · R32 / R31)

[0047] Vf1 has a negative temperature coefficient of -2mV / ℃, V _T has a positive temperature coefficient of 0.086mV / ℃. Therefore, by selecting an appropriate diode area ratio N and an appropriate resistance ratio, the temperature coefficient of the reference voltage VBGR can be made substantially zero. For example, N = 10, R31
= R32 = 600KΩ and R33 = 60KΩ, the temperature coefficient of the reference voltage VBGR becomes almost zero.

It is known that the influence of the variation in the manufacturing process on the forward characteristics of the diode is small. On the other hand, a diffusion layer resistance or a polysilicon resistance is used as the resistance. It is difficult to suppress variations in the manufacturing process of these resistance values. However, since the BGR circuit uses the ratio of the resistances, the influence of the individual resistance variations on the reference voltage is small.
The problem in the BGR circuit is the offset of the differential amplifier 81. As described above, the BGR circuit 80 functions normally on the assumption that the two input terminal voltages Va and Vb of the differential amplifier 81 are the same. If there is a difference between the two input terminal voltages Va and Vb, the output reference voltage is largely distorted. For example, if Vb−Va = 50 mV,
These voltage differences are multiplied by the resistance ratio (R32 / R33), and the reference voltage VBGR rises by 500 mV.

Specifically, the imbalance between the differential NMOS transistors QN31 and QN32 constituting the differential amplifier 81 and the load PMOS transistors QP31 and QP
The imbalance between P32 causes the offset of the differential amplifier 81. In particular, the sub-threshold characteristic of the transistor is an item that is difficult to control. This subthreshold characteristic has temperature dependence as shown in FIG. At room temperature (25 ° C.), as shown in FIG. 10A, the slope of the Vg-Id characteristic is about 100 mV / dec, which is hardly changed on the same chip. However, when the temperature becomes low (−50 ° C.), as shown in FIG. 10B, on the chip, 60 mV / dec to 80 mV / dec.
It is not unusual to show different values between. This is M
This is because the subthreshold characteristic of the OS transistor is sensitive to a slight defect.

Therefore, there occurs a phenomenon that the BGR circuit 80 which normally operates at room temperature or high temperature outputs a completely strange output under low temperature environment. According to this embodiment, as shown in FIG. 9, the resistors R31 to R33 are arranged near the differential amplifier 81, and this is connected to the heaters 82a and 82b.
To warm the differential amplifier 81. This can eliminate unstable operation based on the input offset of the differential amplifier 81 particularly in a low-temperature environment.

[Fifth Embodiment] FIG. 11 shows an LSI including a BGR circuit 110 according to another embodiment. BG
The circuit configuration of the R circuit 110 is slightly different from that of FIG. 8, but the principle configuration is the same as that of FIG. PMOS transistors QP41 whose gates are commonly controlled by the differential amplifier 81,
A current mirror circuit is formed by QP42 and QP43, and current paths 82, 83 and 84 are formed respectively. The current path 82 connected to the PMOS transistor QP41 includes the NMOS transistor QN41 and the diode D1. A current path 82 connected to the PMOS transistor QP42 includes an NMOS transistor QN42, a resistor R42, and a diode D2 (for N diodes D1). A current path 84 connected to the PMOS transistor QP43 includes a resistor R41 and a diode D3.

The PMOS transistor QP41 and the NMOS
The connection node of the transistor QN41 is fed back to one input terminal a of the differential amplifier 81, and the PMOS transistor QN41
The connection node between P42 and NMOS transistor QN42 is fed back to the other input terminal b. Detailed explanation is omitted, but P
By using the connection node between the MOS transistor QP42 and the resistor R41 as an output terminal and appropriately setting the ratio between the resistors R41 and R42, it is possible to generate the reference voltage VBGR without temperature dependency and power source dependency.

The problem in this embodiment is that
PMOS transistor Q forming a current mirror circuit
This is an unbalance of the characteristics of P41 to QP43. The current mirror circuit is a constant current circuit that drives a gate of a plurality of transistors in common, and causes a current determined by a transistor size ratio to flow through them. Generally, when a current mirror circuit is configured, the Vg-Id characteristic 5 shown in FIG.
It is said that it is preferable to use an arc tube region. This is because the influence of variations in transistor characteristics is small.

However, the PMOS transistors QP41 to QP41
Even if QP43 is designed to operate in the pentode region, these PMOS transistors QP41-QP43
Circuit is in the sub-threshold region, the BGR circuit 11
The phenomenon that 0 becomes abnormally stable is seen,
Has been confirmed. This is because the variation in the sub-threshold characteristic is large as shown in FIG. That is, the PMOS transistors QP41, QP
Only when P42 has the same current value in the pentode region,
Between these current paths 82 and 83, Vfa = Vfb +
It is set so that a stable point of dVf is obtained. However, if the sub-threshold characteristics between the PMOS transistors QP41 and QP42 vary, the PM
When the OS transistors QP41 and QP42 have different current values in the subthreshold region shown in FIG.
= Vfb + dVf in some cases. This is abnormal stability.

This abnormal stability is caused by the PMOS transistor Q
Almost no current flows through P41 to QP43, and the output reference voltage is in a low voltage state of VBGR = 0.8V. Moreover, this phenomenon is remarkably observed in a low-temperature environment because the variation in the sub-threshold characteristics of the transistor is larger at a lower temperature. At this time, since almost no current flows through the BGR circuit 110, no heat is generated, and even if time passes, the low temperature state around the circuit is not eliminated, and the BGR circuit 11
0 cannot escape from the abnormal stable state.

Therefore, in this embodiment, the BGR circuit 1
The circuit is devised so that the abnormal stable state can be prevented from being settled, or the abnormal stable state can be automatically exited. Specifically, in the circuit of FIG. 11, a current detection circuit 111 for detecting an abnormally stable current is provided, and the potential of the output node of the differential amplifier 81 is forcibly controlled by the output of the current detection circuit 111. Is provided with a kicker circuit 112 for pulling down.

The current detection circuit 111 includes a PMOS transistor QP44 which forms a current mirror circuit together with the PMOS transistors QP41 to QP43,
And a diode-connected NMOS transistor QN43 to which a current from the transistor QP44 is supplied. When the BGR circuit 110 is in an abnormally stable state where almost no current flows, almost no current flows to the current detection circuit 111, and the current monitor output IMON obtained from the current detection circuit 111 is equal to or lower than the threshold voltage of the NMOS transistor. "L" level.

In the kicker circuit 112, the PMOS transistor QP45 and the resistor R43 constitute a heater. Further, a PMOS transistor QP46 forming a current mirror circuit with the PMOS transistor QP45 and an NMOS transistor QN45 connected to its drain are provided, and a current monitor output IMON is input to a gate of the NMOS transistor QN45. NM whose gate is controlled by the drain of NMOS transistor QN45
The OS transistor QN44 has a drain connected to the differential amplifier 8
1 output node and the source is grounded.

When the BGR circuit 110 is in a normal stable state, the current monitor output IMON is "H" which is equal to or higher than the threshold voltage of the NMOS transistor. At this time, in the kicker circuit 112, the NMOS transistor QN45 is on, the kick signal KICK obtained at its drain is "L", and the NMOS transistor QN44 is off. On the other hand, when the BGR circuit 110 is in the abnormally stable state, the current monitor output IMON is “L”, and the NMOS transistor QN45 is off in the kicker circuit 112;
Therefore, the NMOS transistor QN44 turns on,
The potential of the output node of the differential amplifier 81 is reduced. As a result, the PMOS transistors QP41 to QP44 constituting the current mirror are driven deeply on to shift to the pentode region, and the BGR circuit 110 shifts to a normal stable state.

In the case of this embodiment, the kicker circuit 1
Using the twelve PMOS transistors QP45 and QP44 as heater sources, the PMOS transistors QP41 to QP44
To warm them. This makes it possible to prevent the BGR circuit 110 from settling into abnormal stability in a low-temperature environment, or to more reliably escape from the abnormally stable state.

FIG. 12 specifically shows the PMOS transistor QP45 of the kicker circuit 112 used as a heater.
Is the PM that constitutes the current mirror of the BGR circuit 110.
A layout example is shown in which OS transistors QP41 to QP43 are dispersedly arranged near each other, and a PMOS transistor QP46, which is also used as a heater, is arranged near the PMOS transistor QP44.
As a result, the PMOS transistors QP41 to QP41 constituting the current mirror circuit, which is the cause of the abnormal stability of the circuit,
The entire region of the QP 44 can be warmed, and escape from the abnormally stable state is facilitated.

[Embodiment 6] FIG. 14 shows Embodiment 6 of the present invention.
1 shows a chip layout of an LSI 140.
In the LSI 140, the main part of the semiconductor chip area is the digital logic circuit 141. An analog circuit 142 is arranged around the chip, and heaters 143a and 143b are arranged so as to sandwich the analog circuit 142.
Further, the heaters 143a and 143b are connected to the analog circuit 142.
A temperature sensor 144 is also provided in the vicinity of the analog circuit 142 in order to perform control in accordance with the temperature of the region.

As such a configuration, the analog circuit 142
The heaters 143a and 143b disposed near the analog circuit 142 generate heat under the control of the temperature sensor 144 to warm the analog circuit 142 when the ambient temperature is lower than a certain level. As a result, the analog circuit 142 can operate stably. Since the operation of the digital circuit 141 does not become unstable even in a low temperature environment, it is not necessary to heat this part. Therefore, the heaters 143a, 143a
3b can be arranged, and an increase in power consumption of the entire chip can be suppressed.

Further, the digital logic circuit 141 generally consumes more current at high temperatures. Since the maximum power consumption of the entire chip is defined in the high temperature state, the current consumed by the heaters 143a and 143b at the low temperature does not increase the maximum power consumption of the entire chip.
This is shown in FIG. In FIG. 15, the power consumption of the digital logic circuit 141, the power consumption of the analog circuit 142, and the power consumption of the heaters 143a and 143b are indicated by broken lines, and the total power consumption of the entire chip is indicated by a solid line. Since the power consumption of the heaters 143a and 143b is originally small in the whole chip and becomes large only at a low temperature, it is understood that the power consumption of the whole chip is not significantly affected.

FIG. 16 shows a specific configuration example of the temperature sensor 144 when the analog circuit 142 is the BGR circuit 110 of the above embodiment. The temperature sensor 144 has a PMOS transistor QP51 that forms a current mirror circuit together with the PMOS transistors QP41 to QP44 that form a current mirror circuit of the BGR circuit 110, and a resistor R44 connected to the drain thereof. This resistor R44 is a temperature sensing element,
4 becomes the temperature sensing output Vtherm. The differential amplifier 145 has a temperature sensing output Vtherm and a BGR
By comparing the reference voltage VBGR which is the output of the circuit 110,
It outputs a heater control signal Vcool.

The resistor R44 has a positive temperature coefficient, so that the temperature sensing output Vtherm increases with temperature. On the other hand, the reference voltage VBGR, which is the output of the BGR circuit 110, is controlled so as not to have temperature dependency. Therefore,
When the value of the resistor R44 is set so that the temperature sensing output Vthrm and the reference voltage VBGR intersect at a certain temperature, the control signal Vcool becomes lower than the set temperature.
When the temperature exceeds “H” and the set temperature, the control signal Vcool becomes “L”. If control is performed so that the heater is turned on by the control signal Vcool = “H”, it is possible to control the heater to be energized until the set temperature is reached.

For example, at a set temperature of 25 ° C., Vt
The value of the resistor R44 is selected so that herm = VBGR. Thereby, at a temperature lower than 25 ° C., VBGR>
Vtherm, and the periphery of the analog circuit 142 is warmed. When the temperature exceeds 25 ° C., VBGR <Vtherm
And the heater is turned off. By performing such heater control, it becomes possible to perform the stable operation of the analog circuit while minimizing the power consumption of the heater to a necessary minimum.

[Seventh Embodiment] FIG. 17 shows the present invention.
This is an embodiment applied to a memory LSI including a DRAM cell array 150 as a memory cell array. DRAM
The cell array 150 is usually composed of many sub-cell arrays 151. In such a DRAM cell array 150, an insulating film is formed to cover the signal wiring. A heater 152 is provided on the insulating film. Specifically, the heater 152 is formed in a meandering pattern so as to cover the area of the DRAM cell array 150 evenly. Heater 15
2 has one end connected to a power supply VCC and the other end has a temperature sensor 1
Grounded via an NMOS transistor QN61 controlled by 53.

As the temperature sensor 153, the same one as in the previous embodiment can be used. The temperature sensor 153 turns on the NMOS transistor QN61 at a temperature lower than the set temperature, for example, so that the heater 152 is energized. Thus, when the DRAM cell array 150 is in a low temperature state, it can be uniformly heated as a whole. Therefore, the problem that the writing potential decreases due to the increase in the threshold voltage of the cell transistor, which occurs in a low-temperature environment, is solved. Therefore, the threshold voltage of the cell transistor can be set higher. On the other hand, when the threshold voltage of the transistor is set to be higher, the leakage of the stored charge due to the lowering of the threshold voltage at a high temperature is suppressed, so that the data retention characteristic at a high temperature is improved.

[Eighth Embodiment] FIG. 18 shows an eighth embodiment.
1 shows a configuration of an electronic device 180. A housing 189 of the electronic device 180 is mounted on a board 184 and includes a DRAM 181 which is a semiconductor memory having a built-in heater as described in the seventh embodiment, a digital logic LSI 182 such as a CPU, and an I / O. Interface 18
3 and the like are arranged. Since the digital logic LSI 182 generally generates a large amount of heat, a radiator 186 is attached thereto. In addition, a power supply device 185 is provided in the housing 189, and a cooling device 187 for cooling the entire system is provided in the housing 189.

When such an electronic device 180 is used in a low-temperature environment such as outdoors, the cooling device 187 suffers and the temperature inside the device drops abnormally. At this time, if a DRAM malfunctioning in a low temperature environment is mounted, the entire system malfunctions. In this embodiment, it is guaranteed that the DRAM 181 is warmed by the heater mounted in the chip and operates normally. Thereby, the whole system operates stably in a low temperature environment.

As another method for making this kind of electronic equipment usable in a low-temperature environment, it is easy to mount a device for heating the entire electronic equipment. However, in such a case, extra power is consumed to simultaneously heat the digital logic LSI, the power supply device, and the like which have no problem in the operation in the low temperature environment. In this embodiment, only the DRAM, which is a specific semiconductor device that poses a problem at low temperatures, has a built-in heater, so that the power consumption of the entire device can be suppressed.

[Embodiment 9] FIG. 19 shows a ninth embodiment.
1 shows a chip layout of a system LSI 190. The system LSI 190 is a so-called system-on-chip (SOC), and includes, on a semiconductor chip 191, a DRAM 150 described in the embodiment of FIG.
The circuits in the LSI chip 140 described in the embodiment of FIG. 14 are integrated together. In the DRAM 150, a heater 152 is provided on the cell array. An analog circuit 142 arranged around the digital logic circuit 141
, Heaters 143a and 143 are arranged so as to sandwich this.

In general, many electronic devices using the SOC place importance on portability. Therefore, a wide operating temperature range is required. In addition, for the purpose of stabilizing the operation of the digital logic circuit under a high temperature environment, a device for cooling the entire chip is devised. For example, use of a coating material having a high thermal conductivity, flip chip mounting with a large heat release effect to a substrate, and the like are examples. On the other hand, these contrivances hinder the operation of analog circuits and DRAMs in a low-temperature environment. That is,
Due to the high heat dissipation effect, the chip temperature decreases to the outside air temperature and operation, which makes normal operation of the analog circuit and the DRAM circuit difficult. However, mounting of a heater that raises the temperature of the entire electronic device is not allowed in a portable electronic device that emphasizes battery life.

In the case of this embodiment, as described in the embodiment of FIG. 14, the heaters 143a, 143 arranged around the analog circuit 142 when the system is turned on.
b generates heat, and stable operation of the analog circuit 142 is guaranteed. Although the heaters 143a and 143b are turned off thereafter, the temperature in the vicinity does not decrease due to the heat generated by the analog circuit itself. DRAM on the same chip
150 is warmed by a heater 152 disposed thereon. The heater 152 is controlled by the temperature sensor 153, and is turned on when the temperature of the DRAM 150 is low, and is off when the temperature is high.

Heater 152 arranged in DRAM 150
And a heater 143 arranged near the analog circuit 142
It is significant to make the control modes a and 143b different. That is, in the case of a DRAM, the current consumption in a standby state in which no read or write operation is performed is 1 mA or less. This is much smaller than the standby current in analog circuits, and at this level of current,
The temperature around the DRAM cannot be prevented from lowering. Therefore, it is important for the DRAM to perform heater control while constantly monitoring the ambient temperature.

No heater is provided in the digital logic circuit 141. This is because the operation of the digital logic circuit does not matter even in a low temperature environment. In this way, system L
In SI, the stable operation of the entire system can be assured without consuming unnecessary power by controlling the temperature inside the chip to be the optimum condition according to the circuit elements inside the chip. Become.

[0078]

As described above, according to the present invention, it is possible to provide a semiconductor device which can operate stably in a wide temperature range by incorporating a heater.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a differential amplifier in an LSI according to an embodiment of the present invention.

FIG. 2 is a diagram showing a layout of the differential amplifier according to the embodiment.

FIG. 3 is a diagram illustrating a problem at a low temperature of the differential amplifier according to the embodiment;

FIG. 4 is a diagram showing the temperature dependence of the threshold voltage of a MOS transistor.

FIG. 5 is a diagram showing a configuration of a differential amplifier and a heater control circuit of an LSI according to another embodiment.

FIG. 6 is a diagram showing operation timing of heater control according to the embodiment.

FIG. 7 is a diagram showing a configuration of a differential amplifier and a heater control circuit of an LSI according to another embodiment.

FIG. 8 is a diagram showing an equivalent circuit of a BGR circuit of an LSI according to another embodiment.

FIG. 9 is a diagram showing a layout of the BGR circuit of the embodiment.

FIG. 10 is a diagram illustrating sub-threshold characteristics of a transistor.

FIG. 11 is a diagram showing an equivalent circuit of a BGR circuit of an LSI according to another embodiment.

FIG. 12 is a diagram showing a transistor layout of a main part of the embodiment.

FIG. 13 is a diagram illustrating sub-threshold characteristics for explaining abnormal stability of the BGR circuit.

FIG. 14 is a diagram showing a chip layout of an LSI according to another embodiment.

FIG. 15 is a diagram showing a relationship between power consumption and temperature in the embodiment.

FIG. 16 is a diagram showing an equivalent circuit of a BGR circuit of an LSI according to another embodiment.

FIG. 17 is a diagram showing a layout of a DRAM cell array according to another embodiment.

FIG. 18 is a diagram illustrating a configuration of an electronic device according to another embodiment.

FIG. 19 is a diagram showing a chip layout of a system LSI according to another embodiment.

FIG. 20 is a diagram showing temperature dependence of drain current-gate voltage characteristics of a MOS transistor.

FIG. 21 is a diagram showing a differential amplifier and its input voltage range.

FIG. 22 is a diagram showing an equivalent circuit of a DRAM cell array.

FIG. 23 is a characteristic diagram for describing a problem due to an ambient temperature of a DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Differential amplifier, 12a, 12b ... Heater, 52 ... Power supply control circuit, 53 ... Power supply voltage detection circuit, 54 ... Delay circuit, 71, 72 ... Control circuit, 80 ... BGR circuit, 81
... Differential amplifiers, 82, 83 ... Current paths, R31, R3
2, R33: resistance (also heater), 110: BGR circuit,
111: current detection circuit, 112: kicker circuit, 140:
LSI, 141: digital logic circuit, 142: analog circuit, 143a, 143b: heater, 144: temperature sensor, 150: DRAM cell array, 152: heater,
153: temperature sensor, 190: system LSI.

Claims (16)

[Claims] 1. A semiconductor device comprising: an analog circuit configured using a temperature-dependent element; and a heater disposed near the analog circuit. 2. The semiconductor device according to claim 1, further comprising a power-on control circuit for controlling power supply to said heater for a predetermined time immediately after power-on. 3. The semiconductor device according to claim 1, further comprising a temperature sensor that senses a temperature in the vicinity of the analog circuit and performs control to energize the heater at a certain temperature or lower. 4. The semiconductor device according to claim 1, further comprising a digital logic circuit occupying a main area of the semiconductor chip. 5. The semiconductor device according to claim 1, wherein said analog circuit has a differential amplifier. 6. The analog circuit has a differential amplifier, a current path controlled by an output of the differential amplifier, and a current constantly flowing, and the heater is arranged near the differential amplifier. The semiconductor device according to claim 1, wherein: 7. The analog circuit includes: a differential amplifier; a current mirror circuit including a plurality of transistors whose gates are commonly controlled by an output of the differential amplifier; 2. The semiconductor device according to claim 1, comprising a plurality of current paths to which a current is supplied, and wherein said heater is arranged near said current mirror circuit. 8. The semiconductor device according to claim 1, wherein an element through which a current constantly flows in said analog circuit is used as said heater. 9. A power supply control circuit comprising: a power supply voltage detection circuit for detecting a rise of a power supply voltage; and a delay circuit for energizing the heater for a predetermined time after the power supply voltage detection circuit detects power on. 3. The semiconductor device according to claim 2, comprising: 10. The semiconductor device according to claim 2, further comprising a control circuit for suppressing operation of said analog circuit while said power-on control circuit is energizing said heater. 11. The band gap reference circuit according to claim 7, wherein the differential amplifier, the current mirror circuit, and the plurality of current paths supplied with current by the current mirror circuit constitute a band gap reference circuit. Semiconductor device. 12. A current detection circuit for detecting a current of said current mirror circuit, and said current mirror when the current detection circuit detects that a transistor of said current mirror circuit is abnormally stable in a sub-threshold region. 2. A kicker circuit for forcibly shifting a transistor of the circuit to a pentode region.
2. The semiconductor device according to 1. 13. A semiconductor device comprising: a memory cell array; and a heater disposed on the memory cell array so as to uniformly heat the memory cell array. 14. The semiconductor device according to claim 13, wherein said memory cell array is a DRAM cell array. 15. A semiconductor chip; a digital logic circuit, a memory cell array, and an analog circuit integrated on the semiconductor chip; A semiconductor device comprising: a heater; and a second heater disposed near the analog circuit and configured to heat the analog circuit region at a low temperature. 16. A housing provided with a cooling device for cooling the inside, a semiconductor memory containing a heater disposed in the housing, and a digital logic LSI with a radiator disposed in the housing. An electronic device comprising: