JP2001236032A - Capacitive load drive circuit - Google Patents

Abstract

(57) [Problem] To smoothly change the voltage of a capacitive load at the time of polarity change of a charging voltage without lowering the charging voltage value. SOLUTION: When discharging a positive charge accumulated in a capacitive load C, when a switch S5 is closed, the voltage of the capacitive load C is higher than reference voltages + V1, + V2, so that the outputs of the comparators CMP3, CMP4 are changed. The transistor MP1 and MP2 are both turned on at the L level, the drain current of each transistor becomes the base current of the transistor Q2, a large collector current flows through the transistor Q2, and the charge of the capacitive load C is discharged. With the decrease in the voltage of the capacitive load C, the voltage of the capacitive load C becomes higher than the reference voltage +
When the voltage drops below V1, the output of the comparator CMP3 becomes L
To the H level, the transistor MP1 changes from the on state to the off state, the base current of the transistor Q2 decreases, and the charge of the capacitive load C is discharged according to the reduced base current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive load driving circuit, and more particularly, to a display element, for example, an electrode of a display element having a characteristic of a capacitive load such as a plasma display, an EL display element and a liquid crystal display element. The present invention relates to a capacitive load driving circuit suitable for driving.

[0002]

2. Description of the Related Art Conventionally, when driving an electrode of a display element having a characteristic of a capacitive load such as an EL display element, a DC voltage is converted into a high voltage by utilizing energy of an inductance and an AC voltage is applied to the capacitive load. Is applied.

In a conventional capacitive load driving circuit, a switch is inserted between both ends of an inductance inserted in a DC circuit, each switch is closed, a current flows through the inductance, and then one of the switches is turned on and off a plurality of times. A current flows in one direction to the capacitive load according to the energy generated from the to charge the capacitive load, and the charging generates a high voltage in the capacitive load,
The number of times of charging is counted by a counter, and when the counted value reaches a predetermined number, the one switch is closed and the other switch is turned on and off a plurality of times. A structure is adopted in which a current flows in the direction to charge the battery in the reverse direction, and this charging generates a high voltage in the reverse direction to the capacitive load.
The DC voltage can be converted to a high voltage to apply an AC voltage to the capacitive load.

However, when the polarity of the charging voltage of the capacitive load changes from the positive direction to the negative direction or from the negative direction to the positive direction, noise may be generated in accordance with a high dv / dt.

In view of the above, there has been proposed a device in which a dv / dt characteristic is reduced by providing a discharge circuit for discharging the energy of the capacitive load with a constant current when the polarity of the voltage of the capacitive load changes. As related to this type of technology, for example, JP-A-8-33202 and JP-A-10-105113 are mentioned.

[0006]

In the prior art,
Since the energy of the capacitive load is discharged at a constant current, when the capacity of the capacitive load is small, dv
Although the / dt characteristic can be reduced, when the capacity of the capacitive load is large, even when the energy of the capacitive load is discharged with a constant current, a high dv /
Noise occurs with dt.

In a capacitive load drive circuit without a discharge circuit, a technique is also known in which a resistive load is inserted between the capacitive load and the drive circuit to suppress a high dv / dt at the time of changing the polarity of the charging voltage. According to this method, the charging voltage is reduced by the resistive load not only at the time of changing the polarity of the charging voltage but also at the time of charging.

An object of the present invention is to provide a capacitive load driving circuit that can smoothly change the voltage of a capacitive load when the polarity of the charging voltage is changed without lowering the charging voltage value.

[0009]

To achieve the above object, the present invention provides a capacitive load charging circuit for alternately charging a capacitive load with a positive charge and a negative charge, and a charging voltage for the capacitive load. A capacitive load discharging circuit that discharges the charge stored in the capacitive load at the time of polarity change, wherein the capacitive load discharging circuit adjusts a discharging current according to a charging voltage of the capacitive load. Load drive circuit. It is what constituted.

In configuring the capacitive load drive circuit, the capacitive load discharge circuit may be configured as a capacitive load discharge circuit having a function of adjusting a charge extraction amount according to a charging voltage of the capacitive load.

In configuring each of the capacitive load driving circuits, the capacitive load driving circuit can be configured as a capacitive load discharging circuit having the following elements. (1) Comparison means for comparing the charging voltage of the capacitive load with a plurality of reference voltages having different voltages, and discharge current adjusting means for adjusting the discharge current of the capacitive load according to the comparison result of the comparison means. Having. (2) comparison means for comparing the charging voltage of the capacitive load with a plurality of reference voltages having different voltages, and a discharge current for decreasing the discharge current of the capacitive load in a stepwise manner according to the comparison result of the comparison means Adjusting means.

According to the above-mentioned means, the capacitive load charging circuit and the capacitive load discharging circuit are provided independently, and when the polarity of the charging voltage is changed, the charging voltage of the capacitive load is changed by the capacitive load discharging circuit. , The voltage of the capacitive load can be smoothly changed when the polarity of the charging voltage is changed.

That is, the charging voltage of the capacitive load can be changed in accordance with the optimum dv / dt characteristics, and the occurrence of noise at the time of changing the polarity of the charging voltage can be suppressed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram of a capacitive load drive circuit showing one embodiment of the present invention. In FIG. 1, a capacitive load driving circuit includes a capacitive load charging circuit 10 for alternately charging a capacitive load C with a positive charge and a negative charge, and a capacitive load C for changing the polarity of a charging voltage with respect to the capacitive load C. Load discharge circuit 12 for discharging the charge stored in the circuit
It is provided with.

The capacitive load charging circuit 10 includes a switch S
1, S2, S3, S4, an inductor (coil) L, and diodes D1, D2.
1, a diode D1, and a switch S3 are connected in series to the capacitive load C, and one end of the switch S1 is connected to the positive side of the DC power supply. On the other hand, the switch S2, the diode D2, and the switch S4 are connected in series to the capacitive load C, and one end of the switch S2 is grounded. The inductor L is connected to the cathode of the diode D1 and the anode of the diode D2.

When the switches S3 and S4 are turned off and the switches S1 and S2 are both turned on in the capacitive load charging circuit 10 having the above configuration, a current flows through the inductor L and energy is accumulated in the inductor L. You. Next, when the switch S2 is turned on and off for a predetermined time after the switch S4 is turned on, the energy stored in the inductor L is supplied to the capacitive load C via the diode D2 and the switch S4, and the capacitive load C is charged by a positive charge. The batteries are sequentially charged, and a positive high voltage is generated in the capacitive load C.

After a high voltage is generated from the capacitive load C, the positive charges accumulated in the capacitive load C are discharged for a predetermined time using the capacitive load discharging circuit 12, and then the switches S1 to S4
Is turned off, and then the switches S1 and S2 are turned on, a current flows through the inductor L, and energy is stored in the inductor L. Thereafter, when the switch S3 is turned on and the switch S1 is turned on and off for a certain period of time, the energy stored in the inductor L is supplied to the capacitive load C via a loop including the diode D1, the switch S3, the switch S2, and the capacitive load C. , The negative charge is charged in the capacitive load C,
A negative high voltage is generated from the capacitive load C. Thereafter, the negative charge accumulated in the capacitive load C is discharged using the capacitive load discharge circuit 12, thereby completing one cycle. By repeating this cycle, the capacitive load C, for example,
Electrodes of a display element having a capacitive load characteristic, such as a plasma display, an EL display element, and a liquid crystal display element, can be driven according to a high AC voltage.

On the other hand, the capacitive load discharging circuit 12 includes resistors R1, R2, R3, R4 and a comparator C as a negative discharging circuit for discharging negative charges stored in the capacitive load C.
MP1, CMP2, bipolar transistors Q1, N
MOS transistors (N-channel MOS transistors) MN1 and MN2 are provided as resistors R5, R6, and R3 as discharge circuits for discharging positive charges stored in the capacitive load C.
R7, R8, comparators CMP3 and CMP4, a bipolar transistor Q2, and PMOS transistors (P-channel MOS transistors) MP1 and MP2. It is connected to C.

The resistors R1 and R2 and the resistors R3 and R4 are connected in series and inserted into a negative power supply circuit to generate negative reference voltages having different voltages. Then, a reference voltage -V1 is generated from both ends of the resistor R4, and a reference voltage -V2 is generated from both ends of the resistor R2. These reference voltages are set in a relationship of -V1 <-V2. The comparator CMP1 compares the voltage of the capacitive load C with the reference voltage −V2, and outputs an L or H level signal according to the comparison result to the transistor MN2.
Output. The comparator CMP2 compares the voltage of the capacitive load C with the reference voltage −V1, and outputs an L or H level signal to the transistor MN1 according to the comparison result. That is, the comparators CMP1 and CMP2 are configured as comparing means for comparing the charging voltage of the capacitive load C with the reference voltage.

On the other hand, resistors R5 and R6, resistors R7 and R8
Are connected in series and inserted into a positive power supply circuit to generate a positive reference voltage. The reference voltage + V1 is generated from both ends of the resistor R6, and the reference voltage + V2 is generated from both ends of the resistor R8.
The comparator CMP3 compares the voltage of the capacitive load C with the reference voltage + V1, and outputs an L or H level signal to the transistor MP1 according to the comparison result. The comparator CMP4 compares the voltage of the capacitive load C with the reference voltage + V2, and according to the comparison result, L
Alternatively, an H level signal is output to the transistor MP2. That is, the comparator CMP3,
The CMP4 is configured as a comparison unit that compares the charging voltage of the capacitive load C with a reference voltage.

The transistors MN1 and MN2 are connected in parallel, the source terminal is grounded, and the drain terminal is connected to the base of the transistor Q1. The transistors MP1 and MP2 are connected in parallel with each other, the source terminal is connected to a positive power supply, and the drain terminal is connected to the base of the transistor Q2. Transistors Q1, Q
2 are totem pole connected, and each transistor Q1,
The collector of Q2 is connected to capacitive load C via switch S5. The transistors Q1, Q2 and the transistors MN1, MN2, MP1, MP2 are
Depending on the on / off state of N1 and MN2, transistor Q1
Of the capacitive load C according to the comparison result of the comparators CMP1 and CMP2 or the comparison result of the comparators CMP3 and CMP4. It is configured as a discharge current adjusting means for gradually decreasing the charge.

Next, the operation of discharging the charge of the capacitive load C using the positive discharge circuit after the positive charge is accumulated in the capacitive load C will be described.

When the polarity of the charging voltage of the capacitive load C is changed to the negative side after the voltage of the capacitive load C increases,
When the switch S5 is turned on and closed, since the voltage of the capacitive load C is higher than the reference voltages + V1 and + V2, the outputs of the comparators CMP3 and CMP4 become L level, and both the transistors MP1 and MP2 are turned on. The drain currents of MP1 and MP2 become the base current of transistor Q2, and a large collector current flows through transistor Q2. At this time, the charge stored in the capacitive load C is extracted according to the magnitude of the base current of the transistor Q2.

That is, a discharge current flows according to the magnitude of the base current of the transistor Q2, and the charge stored in the capacitive load C is discharged.

When the charge of the capacitive load C is discharged and the voltage of the capacitive load C decreases and the voltage of the capacitive load C falls below the reference voltage + V1, the output of the comparator CMP3 is inverted from L level to H level. And the transistor MP1
Changes from the on state to the off state. As a result, only the drain current of the transistor MP2 is supplied to the base of the transistor Q2, so that the base current of the transistor Q2 decreases and the discharge current decreases.

That is, as the base current decreases, the amount of charge withdrawn also decreases, and as the base current decreases, the voltage of the capacitive load C gradually decreases.

As described above, when discharging the positive charge stored in the capacitive load C, the charge of the capacitive load C is extracted by two base currents having different levels within a certain discharge time. As compared with the case where the charge of the capacitive load C is extracted according to the base current of the level, even when the capacitance of the capacitive load C changes due to the specification or the like, dv / dt within a certain discharge period can be reduced, and noise can be reduced. Can be suppressed.

That is, when the capacitance of the capacitive load C is increased (when the voltage of the capacitive load C is increased), the time for extracting the electric charge with a large current increases, and conversely, the capacitance of the capacitive load C decreases. When it becomes smaller (when the voltage of the capacitive load becomes lower), the time for extracting the electric charge with a small current becomes longer.

Next, the operation when the negative charge is accumulated in the capacitive load C and then discharged by the negative discharge circuit will be described.

After negative charge is accumulated in the capacitive load C and a negative high voltage is generated from the capacitive load C, the switch S5 is turned on when the polarity of the voltage for switching the capacitive load C to the positive side is changed. When closed, the voltage of the capacitive load C is lower than the reference voltages -V1 and -V2.
1, the output of CMP2 goes to the H level, and the transistors MN1 and MN2 are both turned on.
1. The drain current of MN2 becomes the base current of transistor Q1, and a large collector current flows through transistor Q1. As a result, the charge of the capacitive load C is discharged in accordance with the large base current, and the voltage of the capacitive load C is sequentially reduced.

In the process in which the voltage of the capacitive load C shifts to the 0V side, the voltage of the capacitive load C becomes 0 V from the reference voltage -V1.
The output of the comparator CMP2 is inverted from the H level to the L level, the transistor MN1 changes from the on state to the off state, and the base current of the transistor Q1 decreases.

As described above, when discharging the negative charge stored in the capacitive load C within a predetermined discharge time, the charge stored in the capacitive load C is extracted according to two base currents having different levels. Therefore, compared with the case where the charge of the capacitive load C is extracted in accordance with the base current of a single level, even when the capacitance of the capacitive load C changes due to the specification or the like, dv / dt within a certain discharge period is relaxed. And the generation of noise can be suppressed.

[0033]

As described above, according to the present invention,
When the polarity of the charging voltage is changed, the capacitive load discharging circuit
Since the discharge current is adjusted according to the charge voltage of the capacitive load, the voltage of the capacitive load can be changed smoothly when the polarity of the charge voltage is changed, and noise is suppressed when the polarity of the charge voltage is changed. can do.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a capacitive load drive circuit according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Capacitive load charging circuit 12 Capacitive load discharging circuit S1 to S5 Switch L Inductor D1, D2 Diode C Capacitive load R1 to R8 Resistance CMP1 to CMP4 Comparator Q1, Q2 Bipolar transistor MN1, MN2 NMOS transistor MP1, MP2 PMOS transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Norihiro Kawauchi 3-1-1, Sachimachi, Hitachi-City, Ibaraki Pref. Hitachi, Ltd. Hitachi Works, Ltd. (72) Sang Tanaka 3-3-1 Sachimachi, Hitachi-City, Ibaraki No. 1 F term in Hitachi, Ltd. Hitachi Works (reference) 2H093 NA34 NC35 NC67 ND05 ND10 ND15 5C080 AA05 AA06 BB05 DD12 EE25 FF01 FF09 JJ02

Claims (4)

[Claims] 1. A capacitive load charging circuit for alternately charging a capacitive load with a positive charge and a negative charge, and a capacitor for discharging a charge stored in the capacitive load when a polarity of a charging voltage applied to the capacitive load is changed. And a capacitive load discharge circuit, wherein the capacitive load discharge circuit adjusts a discharge current according to a charging voltage of the capacitive load. 2. A capacitive load charging circuit for alternately charging a capacitive load with a positive charge and a negative charge, and a capacitor for discharging a charge stored in the capacitive load when a polarity of a charging voltage applied to the capacitive load is changed. And a capacitive load discharge circuit, wherein the capacitive load discharge circuit is configured to adjust a charge extraction amount according to a charging voltage of the capacitive load. 3. A capacitive load charging circuit for alternately charging a capacitive load with a positive charge and a negative charge, and a capacitor for discharging a charge stored in the capacitive load when a polarity of a charging voltage applied to the capacitive load is changed. A capacitive load discharging circuit, wherein the capacitive load discharging circuit is configured to compare a charging voltage of the capacitive load with a plurality of reference voltages having different voltages, and the comparing means according to a comparison result of the comparing means. A capacitive load drive circuit comprising: a discharge current adjusting unit that adjusts a discharge current of a capacitive load. 4. A capacitive load charging circuit for alternately charging a capacitive load with a positive charge and a negative charge, and a capacitance for discharging a charge stored in the capacitive load when a polarity of a charging voltage applied to the capacitive load is changed. A capacitive load discharging circuit, wherein the capacitive load discharging circuit is configured to compare a charging voltage of the capacitive load with a plurality of reference voltages having different voltages, and the comparing means according to a comparison result of the comparing means. A capacitive load drive circuit comprising: a discharge current adjusting means for gradually decreasing a discharge current of the capacitive load.